Electrostatic Discharge (esd) Protection Patents (Class 360/323)
  • Patent number: 10338162
    Abstract: A system for magnetic anomaly detection is described. The system may include a nitrogen vacancy (NV) diamond material comprising a plurality of NV centers. A controller modulates a first code packet and controls a first magnetic field generator to apply a first time varying magnetic field at the NV diamond material based on the modulated first code packet. The controller modulates a second code packet and control a second magnetic field generator to apply a second time varying magnetic field at the NV diamond material based on the modulated second code packet, wherein the first code packet and the second code packet are binary sequences which have a low cross correlation with each other. The controller determines a magnitude and direction of the magnetic field at the NV diamond material, and determines a magnetic vector anomaly based on the determined magnitude and direction of the magnetic field.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: July 2, 2019
    Assignee: LOCKHEED MARTIN CORPORATION
    Inventors: Colleen Mary Reynolds, David Nelson Coar, Mary Catherine Chih-Li Decristoforo, Laird Nicholas Egan, Jon C. Russo
  • Patent number: 10197515
    Abstract: A light-trapping geometry enhances the sensitivity of strain, temperature, and/or electromagnetic field measurements using nitrogen vacancies in bulk diamond, which have exterior dimensions on the order of millimeters. In an example light-trapping geometry, a laser beam enters the bulk diamond, which may be at room temperature, through a facet or notch. The beam propagates along a path inside the bulk diamond that includes many total internal reflections off the diamond's surfaces. The NVs inside the bulk diamonds absorb the beam as it propagates. Photodetectors measure the transmitted beam or fluorescence emitted by the NVs. The resulting transmission or emission spectrum represents the NVs' quantum mechanical states, which in turn vary with temperature, magnetic field strength, electric field strength, strain/pressure, etc.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: February 5, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Hannah A. Clevenson, Dirk Robert Englund
  • Patent number: 10008848
    Abstract: ESD protection circuitry that includes one, or more, of the following features, characteristics and/or advantages: (i) use of different “diode types” (for example, Schottky type, PN type, p-type diode-connected field-effect transistor (FET) type, NFET type)) in a series-connected diode set (connected in series with respect to a device-under-protection) and a parallel-connected diode set (connected in parallel with respect to a device-under-protection and the series-connected diode set); (ii) a FET is connected in series with a target device such that the FET's gate can be turned on during normal operation and the FET's gate is resistively coupled to the FET's source; and/or (iii) two FETs are connected in series with a target device such both FETs gates can be turned on during normal operation, one FET's gate is resistively coupled to its source, and the other FET's gate is electrically coupled to its drain.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: June 26, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ephrem G. Gebreselasie, Icko E. T. Iben, Alain Loiseau
  • Patent number: 9778329
    Abstract: A diamond probe is suitable to be attached to an Atomic Force Microscope and is created with a tip that incorporates a one or more Nitrogen Vacancy (NV) centers located near the end of the tip. The probe arm acts as an optical waveguide to propagate the emission from the NV center with high efficiency and a beveled end directs excitation light to the NV center and directs photoluminescence light emanating from the NV center into the probe arm. The probe tip is scanned over an area of a sample with an electric charge, such as a field effect transistor or flash memory. Optically Detected Spin Resonance (ODMR) is measured as the probe tip is scanned over the area of the sample, from which a characteristic of the area of the sample with the electric charge may be determined.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: October 3, 2017
    Assignee: Infinitum Solutions, Inc.
    Inventor: Juergen Heidmann
  • Patent number: 9607640
    Abstract: An apparatus includes a slider of a recording head comprising a plurality of electrical bond pads coupled to bias sources and a ground pad. Each of a plurality of electrical components of the slider is coupled to at least one of the electrical bond pads. At least one of the electrical bond pads is a shared electrical bond pad coupled to at least two of the electrical components. At least one diode is coupled to at least one of the electrical bond pads and at least one of the electrical components.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: March 28, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Declan Macken, Jason Bryce Gadbois, Timothy William Stoebe, Narayanan Ramakrishnan
  • Patent number: 9324942
    Abstract: Providing for a solid state memory cell having a resistive switching memory cell with rectifier characteristics is described herein. By way of example, the solid state memory cell can have one or more layers creating a resistive switching device capable of achieving and maintaining different electrical resistances in response to different voltages applied to the solid state memory cell. Moreover, the solid state memory cell can comprise two or more layers creating a solid state diode device electrically in series with the resistive switching device. The solid state diode device can be configured to permit very low current through the solid state memory cell at voltages less than a breakdown voltage or reverse breakdown voltage. The rectifier characteristics can mitigate sneak path currents in a crossbar memory array, or similar array, facilitating greater sensing margin, reduced likelihood of memory errors, greater die concentration, fast switching times, and other benefits.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: April 26, 2016
    Assignee: CROSSBAR, INC.
    Inventors: Hagop Nazarian, Tanmay Kumar, Sung Hyun Jo
  • Patent number: 9313119
    Abstract: A system for network routing based on resource availability. A network switching element (NSE) may be configured to provide status information to a controller. The controller may be configured to utilize the status information in determining control information that may be provided to the NSE. The NSE may further be configured to assign processing of information flows to processors in the NSE based on the control information. For example, the control information may contain minimum and maximum percent utilization levels for the processors. Information flows may be reassigned to processors that have available processing capacity from processors whose operation is determined not to be in compliance with the minimum and maximum levels. Moreover, inactive processors may be deactivated and alerts may be sent to the controller when the NSE determines that no available processing capacity exists to reassign the flows of processors whose operation is determined to be noncompliant.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: April 12, 2016
    Assignee: Intel Corporation
    Inventor: Iosif Gasparakis
  • Patent number: 9202500
    Abstract: A slider that includes a slider body, the slider body having a trailing edge surface and an opposing leading edge surface; an air bearing surface (ABS) between the trailing edge surface and the leading edge surface; a read/write head located on the trailing edge surface of the slider body; an electrode array located on the trailing edge surface of the slider body, the electrode array including at least a first electrode and at least a second electrode; and first and second bias circuits, wherein the first bias circuit is electrically coupled to the at least first electrode and the second bias circuit is electrically coupled to the at least second electrode.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: December 1, 2015
    Assignee: Seagate Technology LLC
    Inventors: Gary J. Kunkel, Ajaykumar Rajasekharan
  • Patent number: 9129660
    Abstract: Embodiments described herein generally relate to resistive shunt design in a read sensor for providing accurate measurements from an electronic lapping guide (ELG). More specifically, embodiments described herein relate to a transducer resistor shunt structure for low cost probing. A bleed resistor network for a read sensor may comprise one or more first resistors arranged in parallel with one another and a second resistor arranged in series with the one or more first resistors. The resistor arrangement may require a small physical area and reduce or prevent ELG measurement errors.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: September 8, 2015
    Assignee: HGST NETHERLANDS B.V.
    Inventors: John T. Contreras, David Patrick Druist, Edward Hin Pong Lee, David John Seagle, Darrick Taylor Smith
  • Patent number: 8908334
    Abstract: A magneto-resistive (MR) sensor protection circuit is disclosed, for the protection of an MR sensor. The MR sensor may have a safe operating voltage range, a normal operating voltage range within the safe operating voltage range, and two terminals coupled to a read channel circuit, including a positive terminal and a negative terminal. The MR sensor protection circuit may have positive and negative protection threshold voltage ranges. The MR sensor protection circuit may also have a plurality of N-channel field-effect transistors (NFETs) that are coupled to the positive terminal and to the negative terminal, and configured to, in response to a voltage between the two terminals being within either the positive or the negative protection threshold voltage range, limit the voltage between the terminals by shunting current between the positive terminal and the negative terminal.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ephrem G. Gebreselasie, Icko E. T. Iben, Alain Loiseau, Andreas D. Stricker
  • Publication number: 20140347766
    Abstract: Embodiments of the invention relate to electrostatic discharge (ESD) protection. One embodiment includes a first dissipative adhesive (DA) connected to at least a portion of multiple leads in a first plane of a flexible cable in a coverage area for providing ESD protection to at least one element of an electronic device. A common bus bar is connected to the leads in a second plane of the flexible cable. Conductivity of the common bus bar is greater than conductivity of the first DA and the first plane and the second plane are different planes of the flexible cable.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Inventors: Robert G. Biskeborn, Myron H. Gentrup, Icko E.T. Iben, Ho-Yiu Lam
  • Patent number: 8890248
    Abstract: An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: November 18, 2014
    Assignee: Texas Instruments Incorporation
    Inventors: Timothy Patrick Pauletti, Sameer Pendharkar, Wayne Tien-Feng Chen, Jonathan Brodsky, Robert Steinhoff
  • Patent number: 8885301
    Abstract: A crystal film with one or more nitrogen vacancy centers is placed in a magnetic field produced by a recording head and excitation illumination and a varying excitation field is applied. A confocal microscope or wide-field microscope optically detects a decrease in a spin dependent photoluminescence in response to the excitation illumination caused by electron spin resonance (ESR) of the at least one nitrogen vacancy center at varying excitation frequencies of the excitation field to measure Optically Detected Spin Resonance (ODMR). A characteristic of the recording head is determined using the ODMR.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: November 11, 2014
    Assignee: Infinitum Solutions, Inc.
    Inventor: Juergen Heidmann
  • Patent number: 8830616
    Abstract: A write head for a magnetic storage device includes a writing tip comprising a magnetic material, a write pulse generator configured to generate a write pulse signal comprising a varying voltage bias between the magnetic storage device and the writing tip. The write pulse signal comprising one or more write pulses effective to tunnel electrons from the writing tip to the magnetic storage device. The data stream generator configured to provide a data stream signal to the writing tip where the data stream signal is operative to vary spin polarity in the electrons from a first polarity to a second polarity.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: September 9, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Frank Sinclair, Alexander C. Kontos, Rajesh Dorai
  • Patent number: 8829901
    Abstract: A method to measure a magnetic field is provided. The method includes applying an alternating drive current to a drive strap overlaying a magnetoresistive sensor to shift an operating point of the magnetoresistive sensor to a low noise region. An alternating magnetic drive field is generated in the magnetoresistive sensor by the alternating drive current. When the magnetic field to be measured is superimposed on the alternating magnetic drive field in the magnetoresistive sensor, the method further comprises extracting a second harmonic component of an output of the magnetoresistive sensor. The magnetic field to be measured is proportional to a signed amplitude of the extracted second harmonic component.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: September 9, 2014
    Assignee: Honeywell International Inc.
    Inventor: Bharat B. Pant
  • Patent number: 8797693
    Abstract: A method, apparatus, and system are provided for preventing electrostatic discharge (ESD) in hard disk drives using spin-torque oscillator (STO) for microwave assisted magnetic recording (MAMR). A control circuit adjusts a disk electrical potential with an electrical potential of a spin-torque oscillator (STO) element. The control circuit maintains a potential difference of less than about 115 millivolts (mV) between the disk and the STO element.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: August 5, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Masaru Furukawa, Junguo Xu, Makoto Satou, Kenji Suzuki
  • Patent number: 8760791
    Abstract: A magnetic storage system includes a read and write device that (i) magnetically writes data on a platter, and (ii) reads, via a read element, the data written magnetically on the platter. The read element includes a first terminal and a second terminal. A transistor includes a gate. The transistor is closed responsive to the gate not receiving power. Responsive to the gate of the transistor receiving power, the transistor provides an open circuit between the first terminal and the second terminal. Responsive to the gate of the transistor not receiving power, the transistor shorts the first terminal to the second terminal. A first limiting circuit limits a first voltage of (i) the transistor and (ii) the first terminal. A second limiting circuit limits a second voltage of (i) the transistor and (ii) the second terminal.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: June 24, 2014
    Assignee: Marvell International Ltd.
    Inventor: Pantas Sutardja
  • Patent number: 8743510
    Abstract: A magnetoresistive transducer head assembly includes a reader element, a writer element and a high impedance shunt electrically connecting the reader element and the writer element. The high impedance shunt provides a high impedance conductive path for maintaining electrostatic charge equipotential between the reader element and the writer element.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Peter J. Golcher, Icko E. T. Iben, Ho-Yiu Lam, Jose Luis A. Salenga
  • Patent number: 8687369
    Abstract: An apparatus configured to create a resistive pathway for an electronic assembly is disclosed. In one embodiment, the pathway can be formed with a resistive film in conjunction with a conductive adhesive and a coverlay. In another embodiment, the resistive film, the conductive adhesive and the coverlay can be relatively transparent. In yet another embodiment, the resistive pathway can couple directly with traces on an electronic assembly saving space and easing assembly.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: April 1, 2014
    Assignee: Apple Inc.
    Inventors: David A. Stronks, Ahmad Al-Dahle, Wei H. Yao
  • Patent number: 8686508
    Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michel J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam, Robert Robison
  • Patent number: 8673462
    Abstract: A system, in one embodiment, includes an ESD adhesive operatively coupled to leads of an electronic device for providing ESD protection thereto, the ESD adhesive including a mixture of a polymeric thin film and electrically conductive fillers dispersed in the polymeric thin film, and has a structural characteristic of being formed through at least partial evaporation of a solvent therefrom and being substantially free of agglomerates of the electrically conductive fillers. In another embodiment, a method for providing ESD protection to an element of an electronic device includes preventing formation of agglomerates of electrically conductive fillers in an ESD adhesive that includes a polymeric thin film, the electrically conductive fillers dispersed therein, and a solvent by subjecting the ESD adhesive to high-energy mixing during formation thereof, applying the ESD adhesive across exposed leads, such as leads of a cable, PCB, or other substrate, and evaporating solvent from the ESD adhesive.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dylan J. Boday, Myron H. Gentrup, Icko E. T. Iben
  • Patent number: 8634168
    Abstract: A structure for preventing Electrostatic Discharge (ESD) damage to a magnetoresistive sensor during manufacture. The structure includes a switching element that can be switched off during testing of the sensor and then switched back on to provide ESD shunting to the sensor. The switch can be a thermally activated mechanical relay built onto the slider. The switch could also be a programmable resistor that includes a solid electrolyte sandwiched between first and second electrodes. One of the electrodes functions as an anode. When voltage is applied in a first direction an ion bridge forms across through the electrolyte across electrodes making the resistor conductive. When a voltage is applied in a second direction, the ion bridge recedes and the programmable resistor becomes essentially non-conductive.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: January 21, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Thomas Robert Albrecht, Robert E. Fontana, Jr., Bruce Alvin Gurney, Timothy Clark Reiley, Xiao Z. Wu
  • Patent number: 8605401
    Abstract: Systems and methods are disclosed for securing a programmable integrated circuit device against an over-voltage attack. Generally, programmable devices, such as FPGAs, contain volatile memory registers that may store sensitive information. To prevent tampering and/or reverse engineering of such a programmable device, an over-voltage detection circuit may be employed to disable the device and/or erase the sensitive information stored on the device when an over-voltage attack is suspected. In particular, once the over-voltage detection circuit detects that the voltage applied to the programmable device exceeds a trigger voltage, it may cause logic circuitry to erase the sensitive information stored on the device. Desirably, the over-voltage detection circuit includes components arranged in such a way as to render current consumption negligible when the voltage applied to the programmable device, e.g., by a battery, remains below the trigger voltage.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: December 10, 2013
    Assignee: Altera Corporation
    Inventors: Bruce B. Pedersen, Dirk A. Reese
  • Patent number: 8472146
    Abstract: A perpendicular magnetic read head having a balanced capacitive coupling with the substrate. The read head includes a magnetoresistive sensor with first and second magnetic, electrically conductive shields separated from a substrate by a layer of non-magnetic, electrically insulating material. A dummy magnetic shield is formed on the non-magnetic electrically insulating layer and is electrically connected with the second magnetic, electrically conductive shield. The dummy shield is formed to have a capacitive coupling with the substrate that matches the capacitive coupling of the first magnetic, electrically conductive shield with the substrate.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: June 25, 2013
    Assignee: HGST Netherlands B.V.
    Inventors: Diane L. Brown, David J. Seagle
  • Patent number: 8462457
    Abstract: A read head circuit includes a read element configured to read data stored magnetically on a platter and includes first and second terminals. A write element writes data on the platter. A normally-ON transistor includes first, second and control terminals. The first and second terminals of the transistor are connected to a respective one of the first and second terminals of the read element. The control terminal receives a control voltage referenced from a power terminal. The power terminal powers the read element or the write element. Responsive to the control terminal being powered by the power terminal, the normally-ON transistor provides an open circuit between the first terminal of the read element and the second terminal of the read element. Responsive to the control terminal not being powered by the power terminal, the normally-ON transistor shorts the first and second terminals of the read element.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: June 11, 2013
    Assignee: Marvell International Ltd.
    Inventor: Pantas Sutardja
  • Patent number: 8357993
    Abstract: An ultra-high voltage device has a high voltage path established from a high voltage N-well through a first metal layer to a second metal layer, and a contact plug electrically connected between the high voltage N-well and the first metal layer. The contact plug has a distributed structure on a horizontal layout to improve the uniformity of the ultra-high voltage device such that the current in the high voltage path will be more uniform distributed so as to avoid the localized heat concentration caused by non-uniform current distribution that would damage the ultra-high voltage device. Multiple fuse apparatus are preferably connected to the first metal layer individually. Each the fuse apparatus includes a poly fuse to be burnt down when an over-load current flows therethrough.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: January 22, 2013
    Assignee: Richtek Technology Corp.
    Inventor: Jian-Hsing Lee
  • Patent number: 8270124
    Abstract: A method for manufacturing a magnetic head with an electrostatic discharge resistor for preventing electrostatic discharge damage to magnetic head. The electrostatic discharge resistor is formed by a processes that saves manufacturing time and cost by forming resistor in the same deposition and patterning steps used to form the magnetoresistive sensor. However, the resistor includes only a portion of the layers used to form the magnetoresistive sensor, thereby ensuring that the resistor will have sufficient resistivity.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: September 18, 2012
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Satoru Araki, David John Seagle
  • Patent number: 8253203
    Abstract: An electrostatic discharge (ESD) protection circuit that includes a parallel connection of parasitic vertical and lateral bipolar junction transistors (BJTs) each with a floating base and a metal oxide semiconductor (MOS) field transistor with a floating body is disclosed. The three transistors may be connected in parallel between a bond (input or output) pad and a substantially fixed voltage level (e.g., a ground (or zero potential) or Vcc, depending on the transistor configuration) in a semiconductor electronic device so as to protect transistor gates or other circuit portions from damage from electrostatic voltages. The parasitic BJTs and the field transistor may be configured to remain cut off so long as an input voltage at the pad is between a negative V1 voltage (?V1) (V1>0) and a +V2 voltage (V2>Vcc), thereby allowing a greater input voltage swing without signal clamping.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: August 28, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Joohyun Jin
  • Publication number: 20120212854
    Abstract: A magnetoresistive transducer head assembly includes a reader element, a writer element and a high impedance shunt electrically connecting the reader element and the writer element. The high impedance shunt provides a high impedance conductive path for maintaining electrostatic charge equipotential between the reader element and the writer element.
    Type: Application
    Filed: May 3, 2012
    Publication date: August 23, 2012
    Applicant: International Business Machines Corporation
    Inventors: Peter J. Golcher, Icko E.T. Iben, Ho-Yiu Lam, Jose Luis A. Salenga
  • Patent number: 8199444
    Abstract: A magnetoresistive transducer head assembly includes a reader element, a writer element and a high impedance shunt electrically connecting the reader element and the writer element. The high impedance shunt provides a high impedance conductive path for maintaining electrostatic charge equipotential between the reader element and the writer element.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: June 12, 2012
    Assignee: International Business Machines Corporation
    Inventors: Peter J. Golcher, Icko E. T. Iben, Ho-Yiu Lam, Jose Luis A. Salenga
  • Patent number: 8169751
    Abstract: A structure for preventing Electrostatic Discharge (LSD) damage to a magnetoresistive sensor during manufacture. The structure includes a switching element that can be switched off during testing of the sensor and then switched back on to provide ESD shunting to the sensor. The switch can be a thermally activated mechanical relay built onto the slider. The switch could also be a programmable resistor that includes to solid electrolyte sandwiched between first and second electrodes. One of the electrodes functions as an anode. When voltage is applied in a first direction an ion bridge forms across through the electrolyte across electrodes making the resistor conductive. When a voltage is applied in a second direction, the ion bridge recedes and the programmable resistor becomes essentially non-conductive.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: May 1, 2012
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Thomas Robert Albrecht, Robert E. Fontana, Jr., Bruce Alvin Gurney, Timothy Clark Reiley, Xiao Z. Wu
  • Patent number: 8159790
    Abstract: A system and method for the prevention of electrostatic discharge (ESD) by a hard drive magnetic head is disclosed. The magnetic head is secured to a head-gimbal assembly (HGA) by anisotropic conductive paste (ACP) to provide an improved electrostatic discharge path.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: April 17, 2012
    Assignee: SAE Magnetics (H.K.) Ltd.
    Inventors: Bin Hua Tan, Quan Sheng Wu, Ze Liang Luo, Yu Fu
  • Patent number: 8149531
    Abstract: A read head circuit includes a read element configured to read data stored magnetically on a platter. The read element includes a first terminal and a second terminal. A normally-ON transistor includes a first terminal, a second terminal and a control terminal. The first terminal is directly connected to the first terminal of the read element. A second terminal is directly connected to the second terminal of the read element. Responsive to the control terminal being powered, the normally-ON transistor provides an open circuit between the first terminal of the read element and the second terminal of the read element. Responsive to the control terminal not being powered, the normally-ON transistor is configured to short the first terminal of the read element to the second terminal of the read element.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: April 3, 2012
    Assignee: Marvell International Ltd.
    Inventor: Pantas Sutardja
  • Patent number: 8130473
    Abstract: A multi-channel thin-film magnetic head includes a substrate, a plurality of MR read head elements, a plurality of first resistive elements, and a second resistive element. Each MR read head element includes a lower magnetic shield layer, an upper magnetic shield layer, and an MR layer arranged between the lower magnetic shield layer and the upper magnetic shield layer. Each first resistive element has a first resistance value. One ends of the first resistive elements are connected to the lower magnetic shield layers or the upper magnetic shield layers of the MR read head elements, respectively. The second resistive element has a second resistance value that is higher than the first resistance value. One end of the second resistive element is commonly connected to the other ends of the plurality of first resistive elements. The other end of the second resistive element is grounded.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: March 6, 2012
    Assignee: TDK Corporation
    Inventor: Nozomu Hachisuka
  • Patent number: 8115270
    Abstract: An electrostatic discharge protection device includes a first bipolar transistor having a collector terminal connected with a first power supply terminal, an emitter terminal connected with the input/output terminal, and a base terminal connected with a second power supply terminal, a second bipolar transistor having a collector terminal connected with the second power supply terminal, an emitter terminal connected with the input/output terminal, and a base terminal connected with the first power supply terminal, one of the first and second bipolar transistors ensuring a continuity between the collector terminal and emitter terminal under such conditions that a potential difference between the first or second power supply terminal and the input/output terminal is lower than a breakdown voltage at a PN junction between the emitter terminal and the base terminal of the other bipolar transistor.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: February 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Takayuki Nagai
  • Publication number: 20120033332
    Abstract: In one embodiment, a system includes a cable comprising a plurality of leads and an ESD dissipating adhesive coupled to the plurality of leads in a coverage area for providing ESD protection to an element of an electronic device. The ESD adhesive comprises a mixture of a polymeric thin film and electrically conductive fillers dispersed in the film, and the ESD adhesive has a resistivity from about 50 to 100 M?. In another embodiment, a method for providing ESD protection to an element of an electronic device includes applying an ESD adhesive across exposed leads of a cable and evaporating the solvent from the ESD adhesive. At least some of the leads are coupled to an element of an electronic device. The ESD adhesive comprises a polymeric thin film, electrically conductive fillers dispersed in the polymeric thin film, and a solvent for controlling a viscosity of the ESD adhesive.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 9, 2012
    Applicant: International Business Machines Corporation
    Inventors: William T. Bandy, IV, Dylan J. Boday, Icko E. T. Iben, Wayne A. McKinley
  • Patent number: 8107200
    Abstract: A slider mounted CPP GMR or TMR read head sensor is protected from electrostatic discharge (ESD) damage and from noise and cross-talk from an adjacent write head by means of a balanced resistive/capacitative shunt. The shunt includes highly resistive interconnections between upper and lower shields of the read head and a grounded slider substrate and a low resistance interconnection between the lower pole piece of the write head and the substrate. The capacitances between the pole piece and the upper shield, the upper shield and the lower shield and the lower shield and the substrate are made equal by either forming the shields and pole piece with equal surface areas and separating them with dielectrics of equal thicknesses, or by keeping the ratio of area to insulator thicknesses equal.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: January 31, 2012
    Assignees: Headway Technologies, Inc., SAE Magnetics (HK) Ltd.
    Inventors: Eric Cheuk Wing Leung, Anthony Wai Yuen Lai, Pak Kin Wong, David Hu, Moris Dovek, Rod Lee
  • Patent number: 8085510
    Abstract: A protective device for protecting an electronic device, e.g., MR head, from ESD/EOS damage includes a cable having leads coupled to the electronic device and a first port providing access to the leads. A second port with one-to-one electrical connection to each lead in the cable provides a second electrical access to the all leads. A shorting device is coupled to one of the ports thereby creating a short between both the leads of the extension and the leads of the cable. The other port is available for coupling to an external device, e.g., tester or end device while the short provides ESD/EOS protection.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventor: Icko E. (Tim) Iben
  • Patent number: 8020024
    Abstract: An exemplary method for preventing an electronic device from erroneously resetting due to electrostatic discharge (ESD) involves an electronic device that includes a reset control pin. The method includes providing a timer, and setting a reset condition of the reset control pin. If the reset condition is satisfied, the electronic device resets. The method includes appropriately setting the reset condition of the electronic device. The reset condition can virtually never be satisfied by an ESD. Thus, the electronic device is efficiently prevented from erroneously resetting due to ESD.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: September 13, 2011
    Assignee: Chimei Innolux Corporation
    Inventor: Ying-Tai Chen
  • Patent number: 8004782
    Abstract: A tester system includes a tester and a radioactive isotope source. The tester includes a spindle assembly, a disk mounted to the spindle assembly, and a head actuatable over the disk. The radioactive isotope source is positioned in an ionizing location proximate the tester, such that a minimum distance between the radioactive isotope source and an axis of rotation of the disk is less than a radius of the disk.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: August 23, 2011
    Assignee: Western Digital Technologies, Inc.
    Inventors: Michael Nojaba, Pradeep K. Thayamballi, James Tze-Hwa Tung, Julius A. Turangan
  • Patent number: 7982523
    Abstract: Electrostatic discharge clamp devices are described. In one embodiment, the semiconductor device includes a first transistor, the first transistor including a first source/drain and a second source/drain, the first source/drain coupled to a first potential node, the second source/drain coupled to a second potential node. The device further includes a OR logic block, a first input of the OR logic block coupled to the first potential node through a capacitor, the first input of the OR logic block being coupled to the second potential node through a resistor, and a second input of the OR logic block coupled to a substrate pickup node of the first transistor.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: July 19, 2011
    Assignee: Infineon Technologies AG
    Inventor: Cornelius Christian Russ
  • Patent number: 7939905
    Abstract: According to an embodiment of the present invention, an electrostatic breakdown protection method protects a semiconductor device from a surge current impressed between a first terminal and a second terminal, the semiconductor device including: a diode impressing a forward-bias current from the first terminal to the second terminal; and a bipolar transistor impressing a current in a direction from the second terminal to the first terminal under an ON state, a continuity between a collector terminal and an emitter terminal of the bipolar transistor being attained before a potential difference between the first terminal and the second terminal reaches such a level that the diode is broken down.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: May 10, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Takayuki Nagai
  • Patent number: 7888739
    Abstract: An electrostatic discharge circuit between a first pad and a second pad including an electrostatic discharge circuit element, including a bipolar transistor path and a resistor path, the electrostatic discharge circuit element alternately discharging an electrostatic current through the bipolar transistor path and the resistor path.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan-hee Jeon, Han-gu Kim, Sung-pil Jang
  • Patent number: 7864489
    Abstract: Provided is a thin-film magnetic head in which a noise due to the voltage potential difference between the read head element and the protective coat surface is suppressed. The thin-film magnetic head comprises: a read head element, one end surface of the read head element reaching an head end surface on the ABS side; a protective coat formed on the head end surface in such a way to cover at least the one end surface of the read head element; and at least one antistatic means for preventing the protective coat from being electrostatically charged, formed on/above the element formation surface, one end surface of the at least one antistatic means reaching the head end surface, the protective coat covering a portion, not the whole, of the one end surface of the at least one antistatic means on the head end surface.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: January 4, 2011
    Assignee: TDK Corporation
    Inventors: Kei Hirata, Takeo Kagami, Takumi Uesugi, Tetsuro Sasaki
  • Patent number: 7852591
    Abstract: A read head circuit comprises a read element including first and second terminals. A shunting device comprises a transistor including a first terminal that is connected to the first terminal of the read element, a second terminal that is connected to the second terminal of the read element, and a control terminal. The shunting device shorts the first and second terminals when the control terminal is not powered.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: December 14, 2010
    Assignee: Marvell International Ltd.
    Inventor: Pantas Sutardja
  • Patent number: 7827512
    Abstract: A plurality of internal circuits (11 to 14) are formed on a semiconductor chip 10, and receive different power supply voltages. An ESD protection circuit (15) is connected to the power supply lines (31 to 34) for the internal circuits (11 to 14). The area in which the protection circuit (15) is formed is closer to the center of the semiconductor chip (10) than the areas for the internal circuits (11 to 14). Surge voltages applied to the power supply pads reach the protection circuit before reaching the reaching the internal circuits.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: November 2, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Fujiyuki Minesaki
  • Patent number: 7773349
    Abstract: In a CPP MR device such as a tunnel magnetoresistive (TMR) device, shoulders that have a magnetic moment that is matched to the magnetic moments of the free layer extend between the free layer and the S2 shield to provide an electrical path from one shoulder, through the shield, to the other shoulder for dissipating edge charges. Thus, a CPP MR device may include a seed stack, a pinned stack on the seed stack, and a tunnel barrier on the pinned stack. A free stack may be on the tunnel barrier, and the free stack can include a free sublayer separated from a magnetic shield and a path for dissipating edge charges in the free stack through the magnetic shield.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: August 10, 2010
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Robert Stanley Beach, Wipul Pemsiri Jayasekara, Vladimir Nikitin
  • Patent number: 7773347
    Abstract: A thin-film magnetic head has a plurality of MR read head elements. Each MR read head element includes shield layers electrically insulated from the ground. An electrical resistor layer is electrically connected between the shield layer of one of the plurality of MR read head elements and the shield layer of the other one of the plurality of MR read head elements.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: August 10, 2010
    Assignee: TDK Corporation
    Inventors: Kazuhiko Maejima, Hiroshi Kamiyama, Tomonaga Nishikawa
  • Patent number: 7768268
    Abstract: Test methods and components are disclosed for testing the quality of the ground connection fabrication process for ESD shunt resistors in magnetic heads. A wafer is populated with one or more test components along with magnetic heads. The test components are fabricated with ESD shunt resistor ground connections created by the same or similar process used to fabricate the ESD shunt resistor ground connections in magnetic heads on the wafer. The resistance of the test component ground connections may then be measured in order to determine the quality of the ground connections formed by the fabrication process. The quality of the ground connection fabrication process may then be determined based on the measured resistance of the test components.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: August 3, 2010
    Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventors: Satoru Araki, Robert S. Beach, David J. Seagle
  • Patent number: 7715141
    Abstract: A magnetic data storage system according to one embodiment includes a head having a reader, the reader further comprising a shield, a sensor, and leads coupled to the sensor; a charge clamp circuit electrically coupling the shield to the leads; and a bias circuit for passing a bias current through the sensor via the leads; wherein the bias circuit maintains a potential of the shields at about a ground potential.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventor: Robert Glenn Biskeborn