Abstract: A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.

Abstract: Techniques for processing signal information from a high speed communication bus. The techniques includes determining spatial regions on an eye characterized by a start point, an end point, a middle point, a left point, and a right point. The start point is a beginning of an eye opening at a reference voltage. The end point is at an ending of eye opening at the reference voltage. The middle point is at a center point of eye opening at the reference voltage. The left point is a left sampling location characterized by a minimum setup time requirement, and the right point is a right sampling location characterized by a minimum hold time requirement. Determining the points is based on shifting a DQS position and a DQ position and running a plurality of memory built-in self test (BIST) engines and a plurality of results of BIST tests.

Abstract: A method for erasing a plurality of two-bit memory cells, each two-bit memory cell comprises a first bit and a second bit. A reference voltage is applied to a first bit line and a second bit line, the first bit line being associated with the first bits of each two-bit memory cell and the second bit line associated with the second bits of each two-bit memory cell. Then a control activation voltage is applied to a first bit line select and a second bit line select, each bit line associated with the first bits and the second bits of each memory cell, respectively. Then an operating voltage is applied to a plurality of word lines associated with each two-bit memory cell, wherein the operating voltage is between 14 and 20 volts.

Abstract: A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer.

Abstract: In a semiconductor storage device comprising a plurality of memory cells P formed in a matrix form in a semiconductor substrate, write and read for each of which is carried out through a word line and bit line, wherein each said memory cells includes a first and a second memory transistor MT1 and MT2 connected in series. In this configuration, the semiconductor storage device with high reliability which produces abnormality in operation can be provided.

Abstract: Switching distortion in a digitally controlled attenuator is effectively suppressed and soft-switching in passgate arrays, present at a certain point of a logic signal path, is implemented with a minimum number of additional components. The soft switching in passgate arrays is implemented by driving the control nodes of each passgate by an inverter, at least a current terminal of which is made switchable from the respective supply node to a node onto which an appropriate ramp signal toward the potential of the respective supply potential is produced by a suitable controlled ramp generator. The passgates for switching the current terminals of the inverters are controlled by the logic signal that preexisted the intervening switching on the respective signal line of the passgate, and by its inverse. The preexistent logic value is momentarily stored in a latch that is updated at the end of any new switching process.

Abstract: A DC to DC power converter having first and second input terminals and an output terminal for providing an output voltage at the output terminal which is at a potential halfway between a DC potential applied by a DC power supply across the first and second input terminal is disclosed. The converter comprises first and second switches connected at a switch junction in series across the first and second input terminals, first and second series-coupled diodes coupled at a diode junction across the first and second input terminals in reverse-bias relationship with respect to the DC potential applied across the first and second input terminals, a transformer comprising two windings inductively linked and having first and second ends and a center-tap, the ends coupled between the switch junction and the diode junction and the center-tap coupled to the output terminal and means for alternately switching the first and the second switches at an equal duty factor.

Abstract: A bubble memory chip includes a plurality of data loops, some of which may be defective, for storing magnetic bubbles representative of data therein. A serial-parallel input propagation path and a parallel-serial output propagation path are provided for propagating bubbles to and from the data loops. A plurality of spaced apart permalloy disk elements are provided, each adapted for having a single bubble circulated thereabout in the presence of an in-plane rotating magnetic drive field. A stream of bubbles representative of an error map indicating which of the data loops are defective is loaded onto and read from the disk elements to initialize the memory. A plurality of gates permit the bubbles of the error map to be transferred between an error map propagation path and the disk elements in parallel fashion upon pulsing of an adjacent control conductor. The potential for data scrambling in the error map is eliminated.

Abstract: A close-packed magnetic bubble propagation device includes a pattern having a plurality of propagation elements positioned in at least four adjacent rows. These elements are spaced to provide a period or spacing of bubbles in these rows of less than three bubble diameters. Upon application of a rotating in-plane field to the elements, bubbles in adjacent rows move in opposite directions. A preferred embodiment of this propagation device has at least two storage loops which contain at least four adjacent horizontal rows of propagation elements. A preferred device utilizing this pattern has at least two storage loops and an access path which passes through each of the loops. An electrical conductor is associated with the propagation elements in the access path so that the passing of a current through the conductor together with the application of an in-plane rotating field to the elements causes bubbles associated with the elements in the access path to move along the access path.

Abstract: There is disclosed an apparatus and method for constructing integrated buffered devices for use with magnetic bubble domain memories. A small storage loop acts as the buffer memory and is interfaced with the main storage loops through a new circuit component. The new circuit component performs the function of transferring a bubble from one track, holds the bubble for a prescribed number of cycles, and then transfers the bubble to another track. Thus, any arbitrarily located bubble within the storage loop can be transferred to any arbitrary location in the buffer loop.

Abstract: In a field access type bubble memory system using a major loop-minor loop organization, redundant loops are included in each memory chip so that defective minor loops may be disregarded and the memory retain its nominal capacity. Thus, the total number of loops is in excess of the nominal capacity. In one form of the invention the redundant loops are included with the minor loops. In another form of the invention, the redundant loops are independent of the minor loops. A stationary register or flaw chain having at least as many storage locations as the number of minor loops is located on the bubble memory chip with the major and minor loops. Each register location is assigned to contain information with respect to an assigned corresponding minor loop.

Abstract: A two-dimensional storage system having two dimensional access is described which offers advantages of speed and effective utilization of available storage area. The system is comprised of a plurality of bubble domain storage arrays, each of which has means therein for moving bubble domains in two dimensions. For instance, in each storage array bubbles can be moved either right-left or up-down. A functional area is provided between adjacent storage arrays to accommodate bubble movement to perform read, write, and clear functions and possibly logic functions. In one embodiment, the functional areas are comprised of sensors which simultaneously function as translation elements to map the information in one storage array into an adjacent array. Magnetic bubble domain sensors are provided for detecting bubble domains moved in one or two dimensions. For example, one sensor can be used to detect bubble domains moving right-left while another sensor is used to detect bubble domains moving up-down.

Abstract: In a field access type bubble memory system using a major loop minor loop organization, additional redundant minor loops are included in each memory device so that defective minor loops may be disregarded and the memory retain its nominal capacity. Thus, the total number of minor loops is in excess of the nominal capacity. A stationary register is formed integrally with the major loop by coupling bubble idlers directly to the major loop bubble propagation path. The stationary register has as many register positions as the total number of minor loops coupled to the major loop. An appropriate binary code identifies in the appropriate register location the corresponding minor loop which is defective, including nominally defective minor loops, if necessary, so that a number of minor loops equal to the nominal capacity of the memory are identified as good.

Abstract: A noncirculating register for bubble memory systems is comprised of a propagation track, or shift register, which allows the transmission of bubbles in a serial path, a plurality of bubble idlers formed in an array parallel and adjacent to the propagation track and coupled thereto and a single current conductor arranged in such a fashion that there is a loop formed in the vicinity of each idler location, said loop extending into the propagation track which contains the normal straight line path of the conductor. By properly current pulsing the conductor loop in proper relationship to the rotating in-plane magnetic field, bubbles may be transferred in, transferred out, replicated out or annihilated in the various idler locations with respect to the contents of the propagation track. Without a current pulse, the contents of the idler locations and the propagation track have no effect on one another.

Abstract: In a bubble memory system having storage loop architecture, means for buffering both read and write requests in order to improve performance including, in the embodiment disclosed, two sets of short or buffer loops, one for the write section and one for the read section, which are virtually asynchronous with respect to each other and to the main memory storage loops and in which data may be temporarily stored prior to transfer into the main storage loops or prior to transfer into an output track.

Abstract: In a field access type bubble memory system using a major loop-minor loop organization, additional redundant minor loops are included in each memory chip so that defective minor loops may be discarded and the memory retain its nominal capacity. Thus, the total number of minor loops is in excess of the nominal capacity. A stationary register is placed adjacent to and parallel to a major loop and has as many register positions as the total number of minor loops on the chip. An appropriate binary code identifies in the appropriate register location the corresponding minor loop which is defective, including nominally defective minor loops, if necessary, so that a number of minor loops equal to the nominal capacity of the memory are identified as good. Each time the memory is accessed, the contents of the register are accessed, nondestructively, and read into and merged with the contents of the major loop on an every other one basis.

Abstract: In a bubble memory system having storage loop architecture, means for decoupling the write-in means and the read-out means from the propagation cycle of the storage loops so that data may be transferred in and out of said storage loops independently of each other and of the propagation cycle thus decreasing the access time of a bubble memory.

Abstract: Disclosed are magnetic domain (bubble) memory arrays and correlator type memory arrays in uniaxially anisotropic crystals which utilize wavering loop conductor patterns at each bit location defining three contiguous magnetic domain retaining regions. On current reversal a bubble in the center loop of a wavering loop pattern will be equally attracted to either of the outside loops. Decision control is provided by a second array of two conductor lines interposed between the respective domain retaining regions. These control conductors establish an aiding or inhibiting magnetic field when current flows through them. In an alternate design a correlator function is obtained by using bubbles retained in previously disclosed bistable loops as memory elements and interrogating them by means of auxiliary bubbles driven by adjacent wavering loops.

Abstract: A field-access, magnetic bubble memory organized in a major-minor configuration includes an extra set of minor loops dedicated to fault correction. The loops of the extra set are coupled to a major path in a manner to move the information in the loops of the set controllably out of synchronism with respect to the information in the remaining loops. Thus, information in the loops of the extra set can be inserted into the data stream originating from the remaining loops at positions of missing data from faulty ones of those loops.