Abstract: A disclosed example to use an erase-suspend feature on a memory device includes a host interface to receive a first erase command to perform an erase operation; and a control circuit to: based on the erase-suspend feature being enabled at the memory device, suspend the erase operation based on determining that a length of time equal to an erase segment duration value has elapsed, the length of time elapsed being relative to a start of an erase segment, and the erase segment duration value specified in a configuration parameter for the erase-suspend feature; perform a second memory operation when the erase operation is suspended; and after the second memory operation is complete, resume the erase operation based on receiving a second erase command from the memory host controller.

Abstract: A memory controlling device configured to connect to a memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions including a first partition and a second partition is provided. A first controlling module accesses the memory module. A second controlling module determines whether there is a conflict for the first partition to which a read request targets when an incoming request is the read request, instructs the first controlling module to read target data of the read request from the memory module when a write to the second partition is in progress, and suspends the read request when a write to the first partition is in progress.

Abstract: An integrated circuit package for sensing fluid properties includes: a substrate made of semiconductor material; a fluid property measurement circuit formed on the substrate; and a sensor circuit coupled to the fluid property measurement circuit within a same integrated circuit package. The sensor circuit is configured to generate a field that interacts with the fluid. The fluid property measurement circuit is configured to determine a change in a property of the sensor circuit as results from the field interacting with the fluid and is further configured to determine a property of the fluid based on the change in the property of the sensor circuit.

Abstract: Systems and methods are provided for digital transport of paramagnetic particles. The systems and methods may include providing a magnetic garnet film having a plurality of magnetic domain walls, disposing a liquid solution on a surface of the magnetic garnet film, wherein the liquid solution includes a plurality of paramagnetic particles, and applying an external field to transport at least a portion of the paramagnetic particles from a first magnetic domain wall to a second magnetic domain wall of the plurality of magnetic domain walls.

Abstract: An adjustable voltage supply (310) may have a plurality of levels of adjustment, such as a coarse select circuit (471) and a fine select circuit (473), to generate an adjustable voltage (e.g. Vout 364 of FIGS. 3 and 4) with fine resolution across a wide voltage range. In one embodiment, the adjustable voltage may be used as an adjustable read voltage to measure the threshold voltages of bitcells in a memory array (300). From the distribution of these threshold voltages, it is possible to determine the marginality of the bitcells with regard to the voltage which is required to read the bitcells. In one embodiment, the adjustable voltage supply (310) may also be used to provide an adjustable voltage to one or more integrated circuit pwells and/or nwells in order to apply electrical stress. An adjustable voltage supply (310) may be used in any desired context, not just memories.

Abstract: A pulse generator circuit for non-volatile memories, is disclosed, including a circuit for determining the instant at which a pulse for incrementing a counter of the memory is generated and generating an increment pulse duration start signal; a circuit for determining the minimum amplitude of the increment pulse and generating an increment pulse duration end signal; a first logic circuit for enabling the generation of the increment pulse based upon the increment pulse duration start and end signals; and an increment pulse generation circuit for generating or suppressing the increment pulse of the counter of the memory, based upon the current condition of the memory.

Abstract: A least one one-time programmable nonvolatile (NV) memory element uses a field-effect transistor (FET) as a selectively programmed element. A short duration applied drain voltage exceeding the FET's drain-to-source breakdown voltage results in a drain source resistance which is substantially unaffected by the voltages typically applied at the gate terminal. Since the programmed resistance is less than 200 ohms and a high programming voltage is not required, the present invention compares favorably with antifuse nonvolatile memory techniques. The nonvolatile memory element is implemented without adding complexity to a very large scale integrated (VLSI) circuit process.

Abstract: A current access bubble memory system includes a method and device for propagating and switching isolated bubbles within a plurality of orthogonal propagation channels. The device includes two orthogonal arrays of parallel current conductors oriented at 45.degree. angles to the two orthogonal bubble translation axes. The conductors in each array are regularly spaced a distance S apart from center to center. The first array of conductors are connected in parallel to a first current source and the second array of conductors are connected in parallel to a second current source. The propagation channels are defined by confining means to have a width d where d is the bubble diameter. The centerline of the channels are spaced a distance of about .sqroot.2 S/8 from the center of adjacent conductor intersections. Bubble translation occurs through sequential activation of the two bipolar current sources.