Abstract: Implementations described herein relate to suspending memory erase operations to perform high priority memory commands. In some implementations, a memory device may detect, while an active stage of an erase operation is being performed by the memory device, a pending memory command with a higher priority than the erase operation. The memory device may selectively suspend the active stage of the erase operation, to allow the pending memory command to be executed, based on the active stage of the erase operation that is being performed and/or a value of a suspend determination timer associated with suspending the active stage of the erase operation.

Abstract: This document describes apparatuses and techniques for termination of a pulse amplitude modulation signal of a memory circuit. In various aspects, a memory circuit is implemented with a termination circuit that includes a power rail, a resistor, and a switch to couple the resistor between the power rail and a signal line of a memory interconnect. The power rail may be configured to provide power at a termination voltage that is nominally half of a voltage of another power rail from which a corresponding transmission circuit operates. This may be effective to enable termination of pulse amplitude modulation signals to the termination voltage instead of a higher voltage that corresponds to the power rail of the transmission circuit or a ground-referenced node. By so doing, use of the termination circuit may reduce power consumption and/or improve signal integrity of the memory circuit.

Abstract: A semiconductor storage device includes a connection transistor that connects a first wiring to a word line, a block decoder that supplies a signal to a gate of the connection transistor, and a voltage generation circuit including a first node from which a first voltage for generating the signal is supplied to the block decoder, a second node from which a second voltage is supplied to the first wiring, and a voltage difference generation circuit connected between the first node and the second node, wherein the voltage difference generation circuit includes diode-connected first and second transistors and a third transistor, each of the diode-connected first and second transistors having a current path connected between the first and second nodes, the third transistor having a first terminal connected to the first node, a gate connected to a gate of the second transistor, and a second terminal connected to the second node.

Abstract: A system includes: a high bandwidth memory (HBM) including a first sensing unit configured to generate one or more first environmental signals corresponding to a first transistor in a first memory cell, and a second sensing unit configured to generate one or more second environmental signals corresponding to a second transistor in a second memory cell; and a differentiated dynamic voltage and frequency scaling (DDVFS) device configured to perform the following (1) for a first set of the memory cells which includes the first memory cell, controlling temperature by adjusting one or more first transistor-temperature-affecting (TTA) parameters of the first set based on the one or more first environmental signals, and (2) for a second set of the memory cells which includes the second memory cell, controlling temperature by adjusting one or more second TTA parameters of the second set based on the one or more second environmental signals.

Abstract: Methods, systems, and devices for memory with fine grain architectures are described. An apparatus may include a memory device, a first organic substrate, and a second organic substrate. The first organic substrate may include a plurality of first conductive lines arranged with a first pitch that may power one or more components of the memory device. The second organic substrate may be coupled with the memory device and the first organic substrate. The second organic substrate may include a plurality of second conductive lines arranged with a second pitch smaller than the first pitch and may be configured to route signals between the memory device with a host device.

Abstract: A high bandwidth memory system includes a motherboard; and a semiconductor package coupled to the motherboard. The semiconductor package includes a package substrate mounted on the motherboard and including signal lines providing a plurality of channels; a first semiconductor device mounted on the package substrate and including a first physical layer (PHY) circuit; and a second semiconductor device mounted on the package substrate and including a second PHY circuit. The first semiconductor device and the second semiconductor device exchange a data signal with each other through the plurality of channels, the data signal is a multilevel signal having M levels, where M is a natural number greater than 2, and the first PHY circuit compensates for distortion of the channels and performs digital signal processing to compensate for a mismatch between the channels.

Abstract: Nitrogen vacancy (NV) centers in diamond combine exceptional sensitivity with nanoscale spatial resolution by optically detected magnetic resonance (ODMR). Infrared (IR)-absorption-based readout of the NV singlet state transition can increase ODMR contrast and collection efficiency. Here, a resonant diamond metallodielectric metasurface amplifies IR absorption by concentrating the optical field near the diamond surface. This plasmonic quantum sensing metasurface (PQSM) supports plasmonic surface lattice resonances and balances field localization and sensing volume to optimize spin readout sensitivity. Combined electromagnetic and rate-equation modeling suggests a near-spin-projection-noise-limited sensitivity below 1 nT Hz?1/2 per ?m2 of sensing area using numbers for contemporary NV diamond samples and fabrication techniques.

Abstract: A memory cell in capacitive logic, including a bistable system including a fixed element and a mobile element capable of taking one or the other of two stable positions with respect to the fixed element; a read device including a variable-capacitance capacitor including a first fixed electrode and a second mobile electrode rigidly fixed to the mobile element; and an electrically controllable write device for placing the mobile element in one or the other of its two stable positions.

Abstract: A memory controller includes a current information storage unit storing information about various current amounts of a memory system, a current management unit controlling an output time of an operation execution signal by calculating the information about the various current amounts, and a command controller outputting a command to operate a memory device in response to the operation execution signal.

Abstract: Methods of operating a memory include determining a target voltage level for an access line voltage, determining a target overdrive voltage level for gating the access line voltage to an access line coupled to a plurality of memory cells, generating a voltage level for the access line voltage in response to its target voltage level and generating a voltage level for gating the access line voltage to the access line in response to the target overdrive voltage level, and applying the access line voltage to the access line while applying the voltage level for gating the access line voltage to a control gate of a string driver connected to the access line. Apparatus include a voltage regulator having variable resistance paths between a voltage signal node and an output node, and between the voltage signal node and an input of a comparator of the voltage regulator.

Abstract: A semiconductor memory device includes a plurality of memory blocks. The semiconductor memory device also includes a block decoder configured to output a block select signal for selecting at least one memory block of the plurality of memory blocks to at least one block word line of a plurality of word lines, and a connecting circuit including a plurality of pass transistors configured to electrically connect global lines to local lines of a plurality of memory cells included in the plurality of memory blocks in response to the block select signal. The semiconductor device may also include a control logic configured to apply a voltage pulse to global word lines and a ground voltage to global select lines of the global lines, and the voltage pulse to at least the one block word line while the semiconductor memory device is in a ready state.

Abstract: An apparatus includes input circuitry that splits an input value into first bit-groups. First memory arrays are each populated with first random numbers, receive from the input circuitry a first bit-group, and retrieve and output a first random number from a first address indicated by the received first bit-group. Distribution circuitry splits each first random number output by the first memory arrays into second bit-groups, and distributes the second bit-groups. Second memory arrays are each populated with second random numbers, receive via the distribution circuitry a second bit-group from each first memory array, concatenate the received second bit-groups so as to form an address indicator, and retrieve and output a second random number from a second address indicated by the address indicator. Output circuitry combines the second random numbers output by the second memory arrays into an output random number that depends on the input value.

Abstract: An apparatus for signal processing, wherein a disc is placed on a turntable and is provided with a groove which can be followed by the pick-up element, and employing a time-code signal wherein during use of the disc the said time-code signal controls the digital audio source.

Abstract: Methods for programming memory cells. One such method for programming memory cells includes generating an encoded stream using a data stream and programming the memory cells using the encoded stream to represent the data stream. A particular bit position of the encoded stream has a first voltage level when the particular bit position of the data stream has a particular logical state, and the particular bit position of the encoded stream has either a second voltage level or a third voltage level when the particular bit position of the data stream has a logical state other than the particular logical state.

Abstract: In one embodiment, a non-volatile memory bitcell includes a program electrode, an erase electrode, a cantilever electrode connected to a bi-stable cantilever positioned between the program electrode and the erase electrode, and switching means connected to the program electrode arranged to apply a voltage potential onto the program electrode, or to detect or to prevent the flow of current from the cantilever to the program electrode. The switching means may comprise a switch having a first node, a second node, and a control node, wherein voltage is applied to the control node to activate the switch to provide a connection between the first node and the second node. The switching means may comprise a pass-gate. The switching means may comprise an NMOS transistor. The switching means may comprise a PMOS transistor. The switching means may comprise a MEMS switch.

Abstract: A memory mat (101) includes a main body portion (200) that includes a first capacitor (203A), a linear conductive film (204) that is formed between the main body portion (200) and a peripheral circuit (104), and a second capacitor (203B) that is formed to be in contact with the conductive film (204) at a bottom of the second capacitor (203B). The first capacitor (203A) is in contact with a contact layer (202) at a bottom of the first capacitor (203A).

Abstract: A vital-signs patch for a patient monitoring system that includes a housing containing a sensor that makes physiological measurements of a patient, a transmitter, a receiver, a memory, and a processor. The processor periodically takes a measurement from the sensor, converts the measurement to a data record, and stores the data record in the memory. Upon receipt of a signal from another device, the processor retrieves at least a portion of the data record, converts the retrieved portion of the data record to a vital-sign signal, and causes the transmitter to transmit the vital-sign signal to the other device.

Abstract: Methods for programming, memory devices, and methods for reading are disclosed. One such method for programming a memory device (e.g., an SLC memory device) includes encoding a two level data stream to a three level stream prior to programming the memory.

Abstract: In one aspect of the present invention, a memory apparatus comprises a plurality of resettable memory cells, a plurality of memory units, and a reset information propagation logic coupled to the resettable memory cells and the memory units. The reset information propagation logic designed to write reset information into a portion of the memory units in response to one of the resettable memory cells having a reset value when one of the memory units is written into.

Abstract: A memory device includes a plurality of memory cells, a token input interface, a token output interface and control circuitry. The control circuitry is configured to accept a storage command, to condition execution of at least a part of the storage command on a presence of a token pulse on the token input interface, to execute the storage command, including the conditioned part, in the memory cells upon reception of the token pulse on the token input interface, and to reproduce the token pulse on the token output interface upon completion of the execution.

Abstract: A memory power supply circuit is used for providing power to a first memory module received in a first memory slot and a second memory module received in a second memory slot, and comprises a logic circuit and a switching power supply. The logic circuit comprises a first input terminal electrically connected to the first memory slot, a second input terminal electrically connected to the second memory slot, and a first signal terminal. The switching power supply comprises a first power terminal, a second power terminal, and a second signal terminal electrically connected to the first signal terminal. When the first memory slot and the second memory slot receive the first memory slot and the second memory module, the switching power supply turns on the first power terminal and the second power terminal; otherwise, the switching power supply turns off the first power terminal or the second power terminal.

Abstract: A system for prioritizing a cache of print jobs associated with at least one print driver includes a workstation having a processing unit and at least one print driver having a processing unit, that interface via a network. The workstation implements a print job request for a document and determines whether a document key identifier associated with the document exists. If not, a key is created. If a printer-readable format for a document associated with the key identifier is stored in or is pre-existing in one of at least two caches, the print driver assigns a prioritization identifier to the format. The system retrieves the printer-readable format from the cache to produce a print job output. Since the cache stores the document in printer-readable format, overall printing time is reduced. The format may be moved from one cache to another depending upon priority. The corresponding method is also disclosed.

Abstract: A method and a system for coding and reading out information in a microscopic cluster formed with coupled functional islands includes: generating the cluster by forming a regular microscopic pattern for locating the functional islands; making use of a physical or chemical property of each individual island and making use of the coupling between the functional islands; assigning different information to different energy levels of the cluster; effecting a change of the physical or chemical property of at least one functional island in order to change the energy level of the cluster to the energy level equivalent to the information content to be coded; and reading out the information. These measures allow forming a cluster having distinct energy levels, each being assigned to a distinct information content.

Abstract: The memory cell comprises first and second inverter circuits, connected in a loop. First and second decoupling transistors, normally turned off outside the write phases, are respectively connected between an output of the second inverter circuit and first and second inputs of the first inverter circuit. The memory cell is thereby protected against transient disturbances due to ionizing particles. The gates of the decoupling transistors are preferably respectively connected to a supply voltage for the P-type decoupling transistors and grounded for the N-type decoupling transistors.

Abstract: Disclosed are a thermal code transmission circuit and a semiconductor memory device using the same. The thermal code transmission circuit includes a select signal generator which generates a select signal in response to a first enable signal, a level signal generator which receives the first enable signal to generate a level signal, an update signal generator which receives the level signal and a first update signal to generate a second update signal, a latch unit which receives a thermal code in response to the second update signal and outputs the thermal code as an output thermal code, and a thermal code output unit which selectively outputs the output thermal code in response to the select signal.

Abstract: A method and a system for coding and reading out information in a microscopic cluster formed with coupled functional islands includes: generating the cluster by forming a regular microscopic pattern for locating the functional islands; making use of a physical or chemical property of each individual island and making use of the coupling between the functional islands; assigning different information to different energy levels of the cluster; effecting a change of the physical or chemical property of at least one functional island in order to change the energy level of the cluster to the energy level equivalent to the information content to be coded; and reading out the information. These measures allow forming a cluster having distinct energy levels, each being assigned to a distinct information content.

Abstract: Disclosed are a thermal code transmission circuit and a semiconductor memory device using the same. The thermal code transmission circuit includes a select signal generator which generates a select signal in response to a first enable signal, a level signal generator which receives the first enable signal to generate a level signal, an update signal generator which receives the level signal and a first update signal to generate a second update signal, a latch unit which receives a thermal code in response to the second update signal and outputs the thermal code as an output thermal code, and a thermal code output unit which selectively outputs the output thermal code in response to the select signal.

Abstract: A memory card including a first memory responsible for the main memory of the memory card, a memory control unit adapted to control the operation of the first memory, a photoelectric voltage generating unit adapted to generate a voltage corresponding to light irradiated externally via photoelectric conversion, a display unit having a second memory adapted to store information set in advance and adapted to display the information set in advance, and a display control unit adapted to control the operation of the display unit. The method of displaying information includes generating a voltage corresponding to light irradiated externally via photoelectric conversion and displaying information set in advance via a display unit of the memory card using the voltage by photoelectric conversion.

Abstract: A circuit for inline testing of memory devices which provides information on the variation of the threshold voltage. The circuit includes an array of ring oscillators with a series of inverters, which already exist in the memory device. A control logic systematically steps through all of the ring oscillators by enabling each inverter and toggling the input. The mean frequency and its distribution is measured and recorded in an output circuit. The threshold voltage variation in the memory device is deduced from the ring oscillators. The circuit additionally includes two inverters place external of the memory device. Each ring oscillator is coupled to an inverter. The inverter preconditions the elements of the ring oscillator to prevent a resistive divider between the two transistors.

Abstract: When a command is input to a semiconductor memory device, a sub-threshold current is reduced to a predetermined value corresponding to the command. After the reduction of the sub-threshold current is completed, the semiconductor memory device starts to operate corresponding to the command.

Abstract: Two memory areas on a wafer are coupled through pass transistors to double the memory capacity of each area and can be sawed to yield two memory chips each with single memory area. A pair of pass transistors are used to couple each dedicated functional pad in both memory areas, when the pass transistors are turned on. The connection between the pass transistor pair can be sawed through to yield single capacity memory dice. The memory capacity can be further increased by coupling more memory areas together with pass transistors.

Abstract: A protection circuit to discharge plasma-induced charges in a semiconductor device or integrated circuit includes a PMOS transistor and a diode. The PMOS transistor includes a substrate, a drain, a source, and a gate, the source being coupled to receive the plasma-induced charges. The diode has a positive terminal coupled to the substrate of the PMOS transistor and a negative terminal coupled the gate of the PMOS transistor.

Abstract: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.

Abstract: A fail repair circuit in semiconductor memory devices is disclosed. The fail repair circuit can be applied to semiconductor memory devices for receiving a row address and a column address at a time without receiving them divisionally, and semiconductor memory devices operating as a single read mode and a single write mode with no burst or a page mode without address multiplexing.

Abstract: An apparatus is described having a plurality of storage cells coupled between a first bit line and a second bit line. The apparatus also has a first transistor that pre-charges the first bit line and provides a first supply of current for one or more leakage currents drawn from the first bit line by any of the plurality of storage cells. The apparatus also has a second transistor that pre-charges the second bit line and provides a second supply of current for one or more leakage currents drawn from the second bit line by any of the plurality of storage cells.

Abstract: A CAN microcontroller that supports a plurality of message objects, and that includes a processor core that runs CAN applications, a plurality of message buffers associated with respective ones of the message objects, a CAN/CAL module that processes incoming messages that include a plurality of frames, each frame having a maximum number n of data bytes, and a plurality of message object registers associated with each of the message objects, including at least one buffer size register that contains a message buffer size value that specifies the size of the message buffer associated with that message object, and at least one buffer location register that contains an address pointer that points to an address of the storage location in the message buffer associated with that message object where the next data byte of the current incoming message is to be stored.

Abstract: A NAND flash memory device includes a first and second memory blocks. A shared row selection circuit is provided between the first and second memory blocks, selectively or simultaneously selecting the first and second memory blocks, and transferring wordline voltages to a selected memory block by means in a multi-boosting manner.

Abstract: A CAN microcontroller that supports a plurality of message objects, including a processor core that runs CAN applications, a CAN/CAL module that processes incoming messages, and a data memory space. The data memory space includes a plurality of message buffers associated with respective ones of the message objects, and a dedicated RAM memory space that contains a plurality of memory-mapped registers associated with each of the message objects. The plurality of memory-mapped registers associated with each message object correspond to respective command/control fields for facilitating configuration and setup of that message object. Each of the memory-mapped registers is mapped to a respective storage location within the dedicated RAM memory space. In one embodiment, the dedicated RAM memory space encompasses a plurality of separate RAM modules, each RAM module being dedicated to a respective one of the command/control fields.

Abstract: A low power, nonvolatile microelectromechanical memory cell stores data. This memory cell uses a pair of cantilevers, to store a bit of information. The on and off state of this mechanical latch is switched by using, for example, electrostatic forces applied sequentially on the two cantilevers. The cantilevers are partially overlapping. Changing the relative position of the cantilevers determines whether they are electrically conducting or not. One state represents a logical “1”. The other state represents a logical “0”. After a bit of data is written, the cantilevers are locked by mechanical forces inherent in the cantilevers and will not change state unless a sequential electrical writing signal is applied. The sequential nature of the required writing signal makes inadvertent or noise related data corruption highly unlikely. This MEMS memory cell can be implemented, for example, using a three-polysilicon-layer surface micro-machining process.

Abstract: Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments (310, 320, 330, 350 and 360) provide an elongated compact form factor that provides easy and firm grasping for insertion and removal. The digital media devices of the family have respective body portions (312, 322, 332, 342, 352 and 362) preferably of a rigid or semi-rigid material. Preferably, the digital media devices of the family use serial memory requiring few power and signal lines, so that few electrical contacts are required.

Abstract: A method and apparatus for repair of a multi-chip module such as a memory module is provided, where at least one redundant or auxiliary chip attach location is provided on the substrate of the multi-chip module. The auxiliary chip attach location preferably provides contacts for attachment of more than one type of replacement semiconductor chip. Accordingly, when one or more chips on the multi-chip module are found to be completely or partially defective, at least one replacement chip can be selected and attached to the auxiliary location to provide additional memory to bring the module back to its design capacity.

Abstract: Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments (310, 320, 330, 350 and 360) provide an elongated compact form factor that provides easy and firm grasping for insertion and removal. The digital media devices of the family have respective body portions (312, 322, 332, 342, 352 and 362) preferably of a rigid or semi-rigid material. Preferably, the digital media devices of the family use serial memory requiring few power and signal lines, so that few electrical contacts are required.

Abstract: Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments (310, 320, 330, 350 and 360) provide an elongated compact form factor that provides easy and firm grasping for insertion and removal. The digital media devices of the family have respective body portions (312, 322, 332, 342, 352 and 362) preferably of a rigid or semi-rigid material. Preferably, the digital media devices of the family use serial memory requiring few power and signal lines, so that few electrical contacts are required.

Abstract: A memory device includes a multiplicity of memory cells disposed on a substrate for at least intermittent stable storage of at least two different information states. A writing device is associated with the memory cells for selectively putting one of the multiplicity of memory cells into a predetermined information state by external action. A reading device is associated with the memory cells for external detection of a current or chronologically preceding information state of a selected memory cell. The memory cells have a miniaturized mechanical element.

Abstract: A device for optically storing and retrieving information incorporating a cadmium fluoride crystal. Using focused ionizing radiation, patterns can be formed in the crystal by the creation of color centers and/or intrinsic luminescence quenched areas. The stored information can then be retrieved by irradiating the crystal with visible light, ultraviolet light, ionizing radiation or combinations thereof. The device and the storage technique allows the storage of various different levels of information, the different levels being retrievable by using different irradiating media and magnifications of the retrieved information. The device and technique also allows the information to be stored for a predetermined period of time.

Abstract: An intensity controlling circuit device can correct variation in intensity of light beams, due to tolerance occurred in each of a plurality of LED-array chips, emitted by LEDs provided in each of the LED-array chips. The intensity controlling circuit device is connected to at least one LED-array chip comprising a plurality of LEDs and slave transistors corresponding to each of the LEDs. The intensity controlling circuit device comprises an intensity controlling circuit connected to the respective LED-array chip. The intensity controlling circuit comprises a first transistor provided between a power source and a constant current generating unit so as to supply a current to the LED-array chip, and an intensity adjusting unit having a second transistor connected to the first transistor in parallel and a controlling unit for controlling the on/off state of the second transistor.

Abstract: A recording medium comprises an electroconductive oxide film held between a substrate and an insulating oxide film. A recording method locally applies a voltage onto the medium to form a portion different in electric resistance or oxygen content in the electroconductive oxide film. A record-readout method comprises the steps of applying a voltage to the electroconductive oxide film having information recorded thereon and detecting the intensity of current flowing through a recorded portion to read out the recorded information.

Abstract: A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions is disclosed. A printed circuit board having a multiplicity of DRAM memory elements mounted thereto is arranged in a data path having a width of 144 bits. The SIMM of the present invention further includes on-board drivers to buffer and drive signals in close proximity to the memory elements. In addition, electrically conductive traces are routed on the circuit board in such a manner to reduce loading and trace capacitance to minimize signal skew to the distributed memory elements. The SIMM further includes a high pin density dual readout connector structure receiving electrical traces from both sides of the circuit board for enhanced functionality. The SIMM is installed in complementary sockets one SIMM at a time to provide memory expansion in full width increments.

Abstract: A double-side optical disc formed by a pair of optical disc halves bonded together, and a process for producing the double-side optical disc. An adhesive is applied to the disc halves, which are then bonded together at an angle relative to each other in which the direction of the adhesive flow on one disc half will intersect the direction of the adhesive flow on the other disc half. In this manner, satisfactory flatness of the optical disc may be achieved without being affected by surface irregularities of the adhesive layer.

Abstract: An input source is digitalized via a rotated wedge (or wedges) which is operatively sandwiched between a rigidly secured input wire (or wires) and a rigidly secured output wire (or wires).