Abstract: A memory device is provided including circuitry for correcting an over-erased memory cell in the memory device. The memory device may include a substrate. A control gate and a floating gate may be formed over the substrate. The memory device may include a source region and a drain region. A first resistive element may be coupled between the source region and the control gate.

Abstract: Redundancy in storage arrays is used to extend the life of disk drives and conserve power. In an exemplary storage array, a group of storage devices includes y storage devices. Data and redundant information is distributed across the y devices to provide m levels of redundancy. “Spun down devices” are provided by spinning down a set of one or more of up to m of the y storage devices. Meanwhile, data transfers to and from the group of storage devices continue to be serviced. After a predetermined time, the currently spun down disks can be spun up, and new spun down devices are provided by spinning down another set of one or more of m of the y storage devices. An array may include several groups of storage devices, each having its own value for y and m.

Abstract: A self aligned method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench. An electrically conductive floating gate is formed over and insulated from a portion of the channel region, with a horizontally oriented edge extending therefrom. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion disposed adjacent to and insulated from the floating gate edge.

Abstract: A least one one-time programmable nonvolatile (NV) memory element uses a field-effect transistor (FET) as a selectively programmed element. A short duration applied drain voltage exceeding the FET's drain-to-source breakdown voltage results in a drain source resistance which is substantially unaffected by the voltages typically applied at the gate terminal. Since the programmed resistance is less than 200 ohms and a high programming voltage is not required, the present invention compares favorably with antifuse nonvolatile memory techniques. The nonvolatile memory element is implemented without adding complexity to a very large scale integrated (VLSI) circuit process.

Abstract: According to one embodiment of the present invention, a magnetic bubble memory module comprising a flexible printed circuits substrate (FPC3), on which a magnetic bubble memory chip (CHI) is mounted and electrically connected, with interconnecting patterns (9a) electrically connecting the chip (CHI) with external connecting leads, terminals or pins as well as bias coil winding (BIC2) for applying bias field to the chip (CHI), thereby reducing the number of components as well as fabricating steps because of the formation of the bias coil (BIC2) with the printed circuits substrate (FPC3).

Abstract: According to one embodiment of the present invention, a magnetic bubble memory module comprising a flexible printed circuits substrate (FPC3), on which a magnetic bubble memory chip (CHI) is mounted and electrically connected, with interconnecting patterns(9a) electrically connecting the chip (CHI) with external connecting leads, terminals or pins as well as bias coil winding (BIC2) for applying bias field to the chip (CHI), thereby reducing the number of components as well as fabricating steps because of the formation of the bias coil (BIC2) with the printed circuits substrate (FPC3).

Abstract: A magnetic bubble memory device comprises a magnetic bubble memory chip, a unit for generating a bias field, a magnetic shield, and a unit for compensating the bias field, wherein the thermodependency of the bias field is compensated to approximate that of the operation characteristics of the memory chip over a wide temperature range, thereby providing a wide region in which operation is ensured.

Abstract: A layer in a magnetic storage medium provides a biasing magnetic field for writing data. The layer exhibits a net magnetization with an orientation in a first direction when the layer is at a temperature below its compensation temperature and a net magnetization with an orientation in a second direction different from the first direction when heated as by a laser to a temperature above its compensation temperature, but below its Curie point temperature.

Abstract: A system for optimizing the performance of a bubble memory includes a temperature sensor, the output of which is amplified and converted to a digital number by a low power A/D converter to address a memory that stores correction data for various temperatures represented by the temperature sensor output. The correction data output by the memory is converted to an analog signal that is used to control the current flowing through a bias coil of the bubble memory. The bubble memory is used as a non-volatile back-up memory for a CMOS-RAM. A relatively small capacitor bank is charged to a high voltage during normal operation of the CMOS-RAM by a voltage booster circuit. In the event of a power interruption, low power control circuitry actuates a voltage down converter circuit that produces a regulated output voltage to temporarily power the control circuitry while the CMOS-RAM is being transferred to the bubble memory.

Abstract: The specification describes a magnetic bubble device which incorporates a Z coil for providing a test magnetic field in addition to the usually provided bias field. In order to reduce package size the Z coil comprises at least one printed coil 17 formed on a substrate 15. The substrate 15 may be a flexible substrate such as polyimide film which is provided as a flap on a chip connection substrate formed from the same film, the flap folding over to lie parallel with the chip connection substrate.The invention enables a Z coil to be provided within a package without unduly increasing package height and provides an additional advantage that the substrate which supports the Z coil may be used to protect the magnetic bubble device chip.

Abstract: A magnetic bubble device in which ions are implanted, under different conditions, in at least two kinds of regions of a magnetic thin film serving as a medium for propagation of a magnetic bubble. In this manner, the operating margins of magnetic bubble stable operation regions of respective functional parts of the device are made nearly equal, thereby providing for improved operating margin of the device as a whole.

Abstract: A domain drag effect stripline pattern of conductive magnetic bubble material deposited upon a substrate is located in a magnetic bias field preferably normal to the plane of the stripline. Magnetic bubbles can be propagated through the stripline in response to passage of D.C. current pulses through the stripline. The width and cross-sectional area of the stripline is preferably substantially constant except at a switching area where it may be different, and preferably wider. There a coil is juxtaposed with the stripline to apply a magnetic field upon the switching area with the magnetic field varying above and below a critical value to switch the propagation of magnetic bubbles along the stripline on and off as a function of the current through the coil. Alternatively, the external magnetic bias field can be modulated to turn the stripline switch on and off.

Abstract: An adjustable magnetic bias field structure for magnetic bubble devices. A pair of parallel facing magnetically permeable plates are adjustably separated by a number of threaded magnetically hard cylindrical rods or slugs slotted at one end. Threaded plastic rings fastened around holes provided in the pair of permeable plates engage the threads of the slotted rods to provide the adjustment feature. A magnetic bubble device is placed between the two permeable plates.

Abstract: A bias field control arrangement for correcting the bias field in accordance with stability range variations in magnetic domain thin film layers. A thin film layer is provided auxiliary to the layers, which auxiliary layer responds to external environmental conditions such as temperature in a manner substantially identical to that of the magnetic domain layers. A pair of register-detectors are defined on the layer in the form of permalloy domain propagating elements, the dimensions of the elements of one being optimized to propagate domains of a diameter larger than that of a domain of a diameter which is optimum in view of the stability range of the layers and the dimensions of the elements of the other being optimized to propagate domains of a diameter smaller than that of the optimum diameter domain. For normal operation, the domains will be propagated along both channels with equal facility and an output comparison section at the output of the detectors produces no control signal.

Abstract: A magnetic bubble domain package which insures a coplanar relationship between the signal leads and the active surface of the magnetic bubble domain chip and also insures the precise location of the magnetic bubble domain chip within the most uniform part of the rotating magnetic field. The package utilizes a thin film of insulating material and chip means secured to the film to produce the coplanar relationship between the active surface of the chip and the signal leads. The package also includes a plastic coil carrier member which supports the inner drive coil and which may be prewound in a separate manufacturing operation. The coil carrier member is attached to the insulating material/chip means assembly in such a way as to locate the chip precisely in the center of the inner coil wound thereon.