Embedded Conductor Patents (Class 365/59)
  • Patent number: 7483286
    Abstract: A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A number of high permeability metal lines are formed on the first layer of insulating material. The number of high permeability metal lines includes composite hexaferrite films. A number of transmission lines is formed on the first layer of insulating material and between and parallel with the number of high permeability metal lines. A second layer of insulating material is formed on the transmission lines and the high permeability metal lines. The structure for transmission line operation includes a second layer of electrically conductive material on the second layer of insulating material.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: January 27, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Salman Akram
  • Patent number: 7391637
    Abstract: A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A number of high permeability metal lines are formed on the first layer of insulating material. The number of high permeability metal lines includes composite hexaferrite films. A number of transmission lines is formed on the first layer of insulating material and between and parallel with the number of high permeability metal lines. A second layer of insulating material is formed on the transmission lines and the high permeability metal lines. The structure for transmission line operation includes a second layer of electrically conductive material on the second layer of insulating material.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: June 24, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Salman Akram
  • Patent number: 7035128
    Abstract: In a DRAM memory cell including an access Tr and a cell capacitor, a depletion type MOSFET is used for each of the access Tr and the cell capacitor. Thus, an operation margin can be increased and the number of necessary power supplied can be reduced, compared to a known DRAM.
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: April 25, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuji Yamasaki, Masanobu Hirose
  • Publication number: 20040136219
    Abstract: In a DRAM memory cell including an access Tr and a cell capacitor, a depletion type MOSFET is used for each of the access Tr and the cell capacitor. Thus, an operation margin can be increased and the number of necessary power supplied can be reduced, compared to a known DRAM.
    Type: Application
    Filed: December 15, 2003
    Publication date: July 15, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yuji Yamasaki, Masanobu Hirose
  • Patent number: 6704220
    Abstract: A resistive memory device (40) and method of manufacturing thereof including magnetic memory cells (14) having a second magnetic layer (20) including at least a first and second material (24/26). The Curie temperature of the second material (26) is lower than the Curie temperature of the first material (24). A plurality of non-continuous second conductive lines (22) are disposed over the magnetic memory cells (14). A current (28) may be run through the second conductive lines (22) to increase the temperature of the second material (26) to a temperature greater than the second material (26) Curie temperature, causing the second material (26) to lose its ferromagnetic properties, providing increased write selectivity to the memory array (40).
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: March 9, 2004
    Assignee: Infineon Technologies AG
    Inventor: Rainer Leuschner
  • Patent number: 6643160
    Abstract: A data bus architecture for integrated circuit embedded dynamic random access memory having a large aspect ratio serves to reduce power requirements in the data path through the use of multiple metal layers to reduce capacitance on the data busses. The memory is divided into multiple sections with data bussing in those sections routed in one metal, or conductive, layer. A different metal layer is used to route global data across these sections to a data register located on one edge of the memory. These global data lines are double data rate and single-ended which increases the physical spacing of these lines thereby reducing capacitance and power requirements. Each of the global data lines are routed to only one of the memory sections. This results in the average length of these lines being less than the length of the entire memory, which reduces the capacitance of the lines.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: November 4, 2003
    Assignees: United Memories, Inc., Sony Corporation
    Inventor: Kim Carver Hardee
  • Patent number: 6477073
    Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, which are organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays; row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: November 5, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Layne G. Bunker, Larry D. Kinsman
  • Patent number: 5973951
    Abstract: A single in-line memory module (SIMM) for memory expansion in a computer system. The SIMM includes a plurality of memory chips surface-mounted on a printed circuit board. The printed circuit board includes a dual read-out connector edge adapted for insertion within a socket of the computer system. One or more driver chips may further be mounted on the printed circuit board and connected to distribute control signals to the memory chips. A full-width data path may further be connected between the dual read-out connector edge and the plurality of memory chips.
    Type: Grant
    Filed: June 19, 1997
    Date of Patent: October 26, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Andreas Bechtolsheim, Edward Frank, James Testa, Shawn Storm
  • Patent number: 5465229
    Abstract: A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions is disclosed. A printed circuit board having a multiplicity of DRAM memory elements mounted thereto is arranged in a data path having a width of 144 bits. The SIMM of the present invention further includes on-board drivers to buffer and drive signals in close proximity to the memory elements. In addition, electrically conductive traces are routed on the circuit board in such a manner to reduce loading and trace capacitance to minimize signal skew to the distributed memory elements. The SIMM further includes a high pin density dual readout connector structure receiving electrical traces from both sides of the circuit board for enhanced functionality. The SIMM is installed in complementary sockets one SIMM, at a time to provide memory expansion in full width increments.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: November 7, 1995
    Assignee: Sun Microsystems, Inc.
    Inventors: Andreas Bechtolsheim, Edward Frank, James Testa, Shawn Storm
  • Patent number: 4187981
    Abstract: A coded, magnetic module has a plurality of Wiegand effect exhibiting wires deployed parallel to one another and extending substantially across the module. These wires are supported in a laminated arrangement between two thin plastic support plies. Coding is impressed on the module by punching out an intermediate portion of each wire including the adjacent zone of the support plies. This produces a relatively physically stable coded module for subsequent use as part of a coded magnetic pulse generator.
    Type: Grant
    Filed: November 30, 1978
    Date of Patent: February 12, 1980
    Assignee: The Echlin Manufacturing Company
    Inventors: Michael J. Sinko, Milton Velinsky