Plural Shift Register Memory Devices Patents (Class 365/78)
  • Patent number: 10255362
    Abstract: A method of accessing computer networks and data sources simultaneously is disclose. The method includes the steps of (a) selecting at least one of a target source to be accessed; and (b) running target parsing tool of said at least one of a target source if parsing is required. Also, there is disclosed a user interface for accessing multiple target sources simultaneously. The user interface includes a text entry field, a scroll-down menu for selecting one or more target sources, and an infobar for displaying information.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: April 9, 2019
    Inventors: Benjamin Rodefer, Nathan Perkins
  • Patent number: 9645820
    Abstract: An apparatus and method are described for performing a bit reversal and permutation on mask values. For example, a processor is described to execute an instruction to perform the operations of: reading a plurality of mask bits stored in a source mask register, the mask bits associated with vector data elements of a vector register; and performing a bit reversal operation to copy each mask bit from a source mask register to a destination mask register, wherein the bit reversal operation causes bits from the source mask register to be reversed within the destination mask register resulting in a symmetric, mirror image of the original bit arrangement.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Robert Valentine
  • Patent number: 9330004
    Abstract: The present invention provides a data processing method based on a cache node group for data caching, where each cache node in the group includes a local replacement-allowable data storage space for storing data accessed by a local client and a collaborative replacement-allowable data storage space for storing data content accessed by a non-local client. By using the data processing method to process data content stored in the local replacement-allowable data storage space and the collaborative replacement-allowable data storage space of the cache node, the clients can obtain data more accurately and directly during access to the cache node, thereby meeting different requirements for local optimization of the cache node.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: May 3, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Youshui Long
  • Patent number: 9146876
    Abstract: A caching method and a caching system using dual disks, adapted to an electronic apparatus having a first storage unit and a second storage unit, are provided, in which an access speed of the second storage unit is higher than that of the first storage unit. In the method, a data access to the first storage unit is monitored, a data category of the data in an access address of the data access is identified and whether the data category belongs to a cache category is determined. If the data category belongs to the cache category, an access count of the data in the access address being accessed is accumulated and whether the accumulated access count is over a threshold is determined. If the access count is over the threshold, the data in the access address is cached to the second storage unit.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: September 29, 2015
    Assignee: Acer Incorporated
    Inventors: Po-Wei Wu, Hsin-Yu Chen, Hsung-Pin Chang, Ta-Wei Chang
  • Patent number: 8902680
    Abstract: Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: December 2, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Tadashi Yamamoto
  • Patent number: 8681526
    Abstract: A size and retry programmable multi-synchronous FIFO. In one embodiment, a multi-synchronous FIFO memory generally comprises a selectable number of addressable memory locations for storing information; read control means synchronized by a read clock for controlling pop transactions configured to read from one or more of the selected number of addressable memory locations; write control means synchronized by a write clock asynchronous to the read clock for controlling push transactions to write to one or more of the selected number of addressable memory locations; and selectable transaction retry control means configured to cause read control means to repeat selected pop transactions and/or cause write control means to repeat selected push transactions.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: March 25, 2014
    Assignee: Cradle IP, LLC
    Inventors: Moshe B. Simon, Erik P. Machnicki, Mark Longley
  • Patent number: 8300621
    Abstract: The present invention relates to a method for timing acquisition and carrier frequency offset estimation of an OFDM communication system and an apparatus using the same. For this purpose the present invention provides a method for calculating at least one auto-correlation and calculating an observation value by performing a sliding sum on the at least one auto-correlation, and calculating a peak point of an absolute value of the observation as frame timing. In addition, the present invention provides a method for generating a third OFDM symbol that is generated by delaying a second OFDM symbol, calculating an observation value through the second and third OFDM symbols, and calculating a phase difference from a result of multiplication of the observation value and a conjugate complex value of the observation value such that a carrier frequency offset can be estimated.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: October 30, 2012
    Assignees: Samsung Electronics Co., Ltd, Electronics and Telecommunications Research Institute, KT Corporation, SK Telecom Co., Ltd, Hanaro Telecom, Inc.
    Inventors: Hyoung-Soo Lim, Dong-Seung Kwon
  • Patent number: 8238115
    Abstract: A computer motherboard includes a printed circuit board which includes a central processing unit (CPU) socket and a group of memory slots. The group of memory slots includes an in-line type memory slot and a surface mounted device (SMD) type memory slot. The in-line type memory slot includes a number of plated through holes. The SMD type memory slot is set between the in-line type memory slot and the CPU socket. The through holes of the in-line type memory slot are connected to the CPU socket through traces, pads of the SMD type memory slot are connected to corresponding through holes of the in-line type memory slot having the same pin definition.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: August 7, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Yung-Chieh Chen, Cheng-Hsien Lee, Shou-Kuo Hsu, Shen-Chun Li, Hsien-Chuan Liang, Shin-Ting Yen
  • Patent number: 8218377
    Abstract: A fail-safe level shifter switching with high speed and operational for a wide range of voltage supply includes a cascode module, and one or more speed enhancer modules. The cascode module receives one or more input logic signal for generating a plurality of output signals with a reduced switching time. The speed enhancer modules are coupled to the cascode module for facilitating faster charging and discharging of nodes of the cascode module and improving the robustness and operating voltage range of cascode module.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: July 10, 2012
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Amit Tandon, Promod Kumar, Abhishek Lal
  • Patent number: 8115874
    Abstract: Memory storage requirements for digital signal processing operations, for example, motion-compensated video scan rate conversion, that produce intermediate output data, which is then used as an input to the operation, are reduced by reordering operations and organizing memory allocations in a special manner to allow intermediate output at a particular execution time, to substantially share the same memory space as the intermediate output of a previous execution time. Such a reduction in the amount of memory required for processing operations advantageously reduces cost and power consumption.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: February 14, 2012
    Assignee: Trident Microsystems (Far East) Ltd.
    Inventors: Shaori Guo, Selliah Rathnam, Gwo Giun Lee
  • Publication number: 20110267868
    Abstract: According to one embodiment, a shift register memory device includes a shift register, a program/read element, and a rotating force application unit. The shift register includes a plurality of rotors arranged along one direction and provided with a uniaxial anisotropy. Each of the plurality of rotors has a characteristic direction rotatable around a rotational axis extending in the one direction. The program/read element is configured to program data to the shift register by causing the characteristic direction of one of the rotors to match one selected from two directions conforming to the uniaxial anisotropy and configured to read the data by detecting the characteristic direction. The rotating force application unit is configured to apply a rotating force to the shift register to urge the characteristic direction to rotate. The plurality of rotors are organized into a plurality of pairs of every two mutually adjacent rotors.
    Type: Application
    Filed: March 18, 2011
    Publication date: November 3, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi
  • Publication number: 20100290263
    Abstract: A circuit for controlling the read cycle includes plurality of shift stages configured to sequentially shift read signals; and an activating unit configured to activate a read cycle signal which represents a read cycle, by performing logical operation for output signals of the plurality of the shift stages, wherein the plurality of the shift stages are configured to sequentially shift the read signals for a period corresponding to burst setting information.
    Type: Application
    Filed: June 30, 2009
    Publication date: November 18, 2010
    Inventors: Je-Yoon Kim, Jong-Chern Lee
  • Patent number: 7782690
    Abstract: A semiconductor device includes plural switching transistors configured to perform trimming for characteristic adjustment of the semiconductor device, and a nonvolatile memory connected to the plural switching transistors and configured to store data for determining ON and OFF of the plural switching transistors. When the semiconductor device is in operation, ON and OFF of the switching transistors are determined by the data.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: August 24, 2010
    Assignee: Ricoh Company, Ltd.
    Inventor: Hiroaki Nakanishi
  • Patent number: 7747020
    Abstract: Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the invention, the hash algorithm is pipelined within the processor architecture.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: June 29, 2010
    Assignee: Intel Corporation
    Inventor: Wajdi K. Feghali
  • Patent number: 7667994
    Abstract: A method for use with a magnetic racetrack device includes placing domain walls having a first structure and domain walls having a second, different structure along the racetrack at stable positions corresponding to different regions within the device. The domain walls having the first structure and the domain walls having the second structure occupy alternating positions along the racetrack. A current pulse is applied to the racetrack, so that each of the domain walls moves to an adjacent region. This results in a transformation of the domain walls having the first structure into domain walls having the second structure, and vice versa. The first structure may be a vortex structure and the second structure may be a transverse structure.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Rai Moriya, Stuart Parkin, Luc Thomas
  • Patent number: 7566941
    Abstract: A magnetoresistive memory cell includes a tunnel barrier region between first and second electrode devices. The first electrode device includes a natural antiferromagnet region. A diffusion barrier region is formed in the first electrode device and serves as a chemical and/or physical transformation region of a surface region or interface region between the tunnel barrier region and the natural antiferromagnet region.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: July 28, 2009
    Assignee: Infineon Technologies AG
    Inventor: Manfred Ruehrig
  • Publication number: 20090168485
    Abstract: A pipe latch device includes an output controller for outputting first and second output control signal groups based on a DLL clock signal and a driving signal; an input controller for generating an input control signal group; and a pipe latch unit for latching data on a data line when a corresponding input control signal is activated, and outputting latched data when a corresponding output control signal is activated, wherein the output controller includes a plurality of shifters, each for delaying an input data signal by half clock and one clock to output a first and second output signals in synchronization with the DLL clock signal and the driving signal; and a plurality of output control signal drivers for outputting the first and second output control signal groups based on the first and second output signals.
    Type: Application
    Filed: March 5, 2009
    Publication date: July 2, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kyoung-Nam KIM, Ho-Youb Cho
  • Patent number: 7545663
    Abstract: Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a memory cell is formed, and an interface chip in which a peripheral circuit is formed for the memory cell. The plurality of core chips through have latch circuit units through for temporarily storing data to be outputted by the memory cell, and latch circuit units through for temporarily storing data to be inputted to the memory cell, respectively, and these latch circuit units through and latch circuit units through are connected in a cascade to the interface chip. Since the plurality of latch circuit units connected in a cascade can thereby perform a pipeline operation, it becomes possible to achieve high-speed data transfer.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: June 9, 2009
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroaki Ikeda, Mamoru Sasaki, Atsushi Iwata
  • Publication number: 20080239784
    Abstract: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.
    Type: Application
    Filed: June 10, 2008
    Publication date: October 2, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael C. Gaidis, Lawrence A. Clevenger, Timothy J. Dalton, John K. DeBrosse, Louis L.C. Hsu, Carl Radens, Keith Kwong Hon Wong, Chih-Chao Yang
  • Patent number: 7345701
    Abstract: A line buffer and a method of providing data to a 3×3 line interpolation processor using the line buffer in an image processing system, such as a digital camera, includes a readable and writable single memory, a buffer register having a prior data area storing first line image data, which has been stored in a memory, in a unit of 2m bits, and having a present data area storing second image data, which is inputted from an image sensor in a unit of m bits, in a unit of the 2m bits, and a memory controller providing the memory with a chip enable signal, a write enable signal, and an address indicating locations of the first and second line image data stored in the buffer register, reading and writing the first and second line image data from and on the memory, and outputting the first and second line image data and a third line image data, which is inputted from the image sensor.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: March 18, 2008
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang-Hyun Park, Jong-Sik Jeong, Yeon-Cheol Lee, Kang-ju Kim, Hyung-Man Park, Boo-Dong Kwak
  • Patent number: 7317780
    Abstract: A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the first transistor, an output and a first clock signal, and a pull-down module coupling to the output, output signals of pre-stage and post-stage shift register, a second and a third voltage level. When the second transistor turns on and the first clock signal is at high voltage level, the output is at a first voltage level. When the signal of post-stage shift register is at first voltage level, the output is at the third voltage level.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: January 8, 2008
    Assignee: AU Optronics Corp.
    Inventors: Wei-Cheng Lin, Chun-Ching Wei, Yang-En Wu, Cheng-Liang Ma
  • Publication number: 20070297250
    Abstract: In a data processing apparatus and method using a first-in first-out (FIFO), the data processing apparatus includes a first sampling circuit, a delay circuit, and a FIFO device. The first sampling circuit samples a logic state of input data in response to a first edge of a first clock signal and holds a result of the sampling. The delay circuit receives and delays the first clock signal by a predetermined delay time and outputs a second clock signal. The FIFO device processes the result of the sampling output from the first sampling circuit using a FIFO method in response to a first edge of the second clock signal output from the delay circuit.
    Type: Application
    Filed: June 12, 2007
    Publication date: December 27, 2007
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Kwan-Yeob Chae
  • Patent number: 7310260
    Abstract: The use of a bus clock is eliminated in communication between a cpu, or mpu, and a register block. The communication between the cpu/mpu and the register block is made combinatorial, such that the cpu/mpu does not require any acknowledge or wait signal from the register block to know when to proceed with a requested write operation. The register block has both a write request input and a read request input, each of which is separately actuated to initiate a write operation or read operation, respectively. The cpu/mpu initiates a write operation by actuating the write request input while maintaining the read request input negated. The register block responds to actuation of its write request input by getting ready for initiate the requested write operation, and waiting for a signal letting it know if the requested operation is a valid write operation. If the requested write operation is deemed valid, then the register block executes the requested write operation only upon the negation of the write request.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: December 18, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Phil Van Dyke, Barinder Singh Rai
  • Patent number: 7256484
    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: August 14, 2007
    Assignee: Staktek Group L.P.
    Inventors: Russell Rapport, James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, Jr., Jeff Buchle
  • Patent number: 7177421
    Abstract: Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. Authentication engines in accordance with the present invention apply a variety of techniques that may include, in various applications, collapsing two multi-round authentication algorithm (e.g., SHA1 or MD5 or variants) processing rounds into one; reducing operational overhead by scheduling the additions required by a multi-round authentication algorithm in such a matter as to reduce the overall critical timing path (“hiding the ads”); and, for a multi-loop (e.g., HMAC) variant of a multi-round authentication algorithm, pipelining the inner and outer loops.
    Type: Grant
    Filed: April 4, 2001
    Date of Patent: February 13, 2007
    Assignee: Broadcom Corporation
    Inventors: Mark Buer, Patrick Y. Law, Zheng Qi
  • Patent number: 7174014
    Abstract: The present invention provides permutation instructions usable in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. PPERM and PPERM3R instructions are defined to perform permutations by a sequence of instructions with each sequence specifying the position in the source for each bit in the destination. In the PPERM instruction bits in the destination register that change are updated and bits in the destination register that do not change are set to zero. In the PPERM3R instruction bits in the destination register that change are updated and bits in the destination register that do not change are copied from intermediate result of previous PPERM3R instructions. Both PPERM and PPERM3R instructions can individually do permutation with bit repetition. Both PPERM and PPERM3R instructions can individually do permutation of bits stored in more than one register. In an alternate embodiment, a GRP instruction is defined to perform permutations.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: February 6, 2007
    Assignee: Teleputers, LLC
    Inventors: Ruby B. Lee, Zhijie Shi
  • Patent number: 7154984
    Abstract: A FIFO-register (10) according to the invention comprises a sequence of register cells (10.1, . . . ,10.m), which register cells have a data section (40) and a status section (30). Data (Din) provided at an input (20) is shifted via the data sections (40) in the register cells to an output (50). The status section (30) of each cell indicates whether the data section (40) of that cell contains valid data. The status section of a cell comprises a control unit (37) coupled to a status input (32), to a status output (33) and to a clock input (31), and generates an output clock signal (Cli), which controls charge controlling elements (35, 36) coupled to the status input and the status output and controls the data section (40). The status output (33) of a status section (30) and the status input (32?) of its successor (30?) share a common capacitive node (33).
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: December 26, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Roelof Herman Willem Salters, Paul Wielage
  • Patent number: 7120041
    Abstract: The present invention relates to a memory device having the capability of controlling a characteristic parameter including a register controller including a nonvolatile memory unit for storing data and a parameter controller for outputting a signal corresponding to a predetermined input signal. The parameter controller controls one or more characteristic parameters of the memory unit, including input voltage sensitivity, output signal delay and output signal voltage, according to a signal outputted from the register controller.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: October 10, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee Bok Kang
  • Patent number: 7092301
    Abstract: The present invention provides a controller that can write an operation program for a control circuit to a memory and a method for writing data, while suppressing an increase in circuit area and an increase in manufacturing cost. An ATA register is connected to a host computer. A flash ROM access register is connected to the ATA register. When a special command code 80h is sent to the ATA register from the host computer, data (a command and microcomputer control software) sent from the host computer is sent via the ATA register. A decoder decodes the data sent to the flash ROM access register and generates a format, an address, and data for writing the microcomputer control software to the flash ROM.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: August 15, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Takayuki Suzuki
  • Patent number: 7092272
    Abstract: A first-in-first-out (FIFO) microelectromechanical memory apparatus (also termed a mechanical memory) is disclosed. The mechanical memory utilizes a plurality of memory cells, with each memory cell having a beam which can be bowed in either of two directions of curvature to indicate two different logic states for that memory cell. The memory cells can be arranged around a wheel which operates as a clocking actuator to serially shift data from one memory cell to the next. The mechanical memory can be formed using conventional surface micromachining, and can be formed as either a nonvolatile memory or as a volatile memory.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: August 15, 2006
    Assignee: Sandia Corporation
    Inventors: Jeffrey C. Gilkey, Michelle A. Duesterhaus, Frank J. Peter, Rosemarie A. Renn, Michael S. Baker
  • Patent number: 7057946
    Abstract: Circuits have a certain function. A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored data to respective adjacent registers in sequence. The plurality of first and second registers are connected in one-to-one correspondence to a plurality of input terminals or to a plurality of output terminals. A first scan input terminal is formed at one end of the plurality of first series-connected registers, and a first scan output terminal is formed at the other end. A second scan input terminal is formed at one end of the plurality of second series-connected registers, and a second scan output terminal is formed at the other end. An operation control circuit controls operations of the circuits and the plurality of first and second registers.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: June 6, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryo Fukuda
  • Patent number: 7038965
    Abstract: The present invention discloses a pointer generator which generates pointer values for a stack (LIFO memory). The pointer generator includes a selection input terminal and a bi-direction linear feedback shift register. The selection input terminal transmits a selection signal to the bi-direction linear feedback shift register in response to a command to read/write the stack. The fundamental structure of the bi-direction linear feedback shift register is a linear feedback shift register. After receiving the selection signal from the selection input terminal, the bi-direction linear feedback shift register performs calculation of a specific primitive characteristic polynomial, and then creates a number sequence. When the selection signal changes, the bi-direction linear feedback shift register creates another number sequence by performing calculation of another specific primitive characteristic polynomial. The two number sequences are exactly opposite to each other in order.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: May 2, 2006
    Assignee: Benq Corporation
    Inventor: Ying-Heng Shih
  • Patent number: 6987686
    Abstract: For increasing the performance of a register file that is constructed to include dual-Vt bitlines or single-Vt bitlines. A boost of the drive signal for one of the transistors of a bitline circuit, preferably for the high voltage threshold read-selection transistor of a local bitline (LBL) circuit. The drive signal amplitude is made greater than the normal supply voltage by some increment delta V.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: January 17, 2006
    Assignee: International Business Machines Corporation
    Inventors: Suhwan Kim, Stephen V Kosonocky
  • Patent number: 6948030
    Abstract: A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: September 20, 2005
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jay Kishora Gupta, Amitabha Banerjee, Somnath Paul
  • Patent number: 6930903
    Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: August 16, 2005
    Assignee: Netlist, Inc.
    Inventors: Jayesh R. Bhakta, Robert S. Pauley, Jr.
  • Patent number: 6930900
    Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: August 16, 2005
    Assignee: Netlist, Inc.
    Inventors: Jayesh R. Bhakta, Robert S. Pauley, Jr.
  • Patent number: 6879526
    Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: April 12, 2005
    Assignee: Ring Technology Enterprises LLC
    Inventors: William Thomas Lynch, David James Herbison
  • Patent number: 6873534
    Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: March 29, 2005
    Assignee: Netlist, Inc.
    Inventors: Jayesh R. Bhakta, Robert S. Pauley, Jr.
  • Patent number: 6859844
    Abstract: A computer system comprises a plurality of modules and a shift register having a plurality of slots connected in series, wherein each of the plurality of slots is coupled to one of the plurality of modules. In one embodiment, an output of a last slot of the plurality of slots is coupled to an input of an initial slot of the plurality of slots to form a ring. Each slot of the shift register corresponds to a time slot on the ring, and each of the time slots is assigned to one of the modules. At least two of the modules are configured to independently generate frames for transmission on the ring. In another embodiment, at least one of the modules comprises a bridge module coupled to communicate with other bridge modules separate from the plurality of modules.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: February 22, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Bodo K. Parady
  • Publication number: 20040246758
    Abstract: A shift register includes at least one stage circuit that has at least three voltage control switches, a storage element, and a first clock signal, a second clock signal and a third clock signal to control various switches. Input signals are stored in the capacitor and sequentially transferred to the next stage. During transferring to the next stage, pixel switches of one row on the panel display are activated to receive information delivered from the data end for displaying on the pixels. The clock signals have the characteristics that the first clock signal, second clock signal and third clock signal are not at the same certain potential concurrently to prevent the switches of each stage (the second and third switches) from forming a DC path and burning out.
    Type: Application
    Filed: June 4, 2003
    Publication date: December 9, 2004
    Inventors: Rui-Guo Hong, Chih-Chung Chien, Yen-Hua Chen, Shin-Tai Lo
  • Patent number: 6816430
    Abstract: The data storage device includes several registers that can be addressed by address words, and connected to p output ports through connections that can be configured in response to address words of p registers selected to read the contents of these registers on the p ports respectively. All register address words contain a specific bit with a predetermined rank identical for all address words and remaining bits. The registers are connected in pairs on each output port, each pair of registers containing two registers with address words that only differ in the value of the said specific bit.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: November 9, 2004
    Assignee: STMicroelectronics SA
    Inventor: Hélène Esch
  • Patent number: 6804743
    Abstract: A command buffer for use in packetized DRAM includes a two stage shift register for shifting for sequentially storing two of four 10-bit command words in each packet. After the first two words of each packet have been stored, they are transferred to a first storage register and output from the first storage register. After the final two words of each packet have been shifted into the shift register, they are transferred to a second storage register and output from the second storage register. The first two command words are output from the first storage register before the last two command words are applied to the command buffer. As a result, the DRAM can start processing the first two command words of the command packet before the entire command packet has been received.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: October 12, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 6785389
    Abstract: A bitstream generator including a plurality of linear feed shift registers (LFSRs) operative to generate a bit stream and including: at least a first LFSR operative, when assigned as a generator during a first time period including at least one clock cycle, to provide an output bit in each clock cycle within the first time period, and at least a second LFSR operative, when assigned as an assignor during the first time period, to provide in each clock cycle an output bit for determining assignments of at least some of the plurality of LFSRs for a second time period following the first time period, the assignments including assignment as a generator, and assignment as an assignor, and a first combiner operative to combine output bits from all of the at least a first LFSR being assigned as generators thereby to produce during each clock cycle a single output bit which is provided to the bit stream. Related apparatus and methods are also provided.
    Type: Grant
    Filed: October 18, 2000
    Date of Patent: August 31, 2004
    Assignee: NDS Limited
    Inventors: Yaron Sella, Aviad Kipnis
  • Patent number: 6751113
    Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: June 15, 2004
    Assignee: Netlist, Inc.
    Inventors: Jayesh R. Bhakta, Robert S. Pauley, Jr.
  • Patent number: 6711494
    Abstract: A data formatter includes a shift register and a pointer manager. The shift register receives data from a providing RAM and shifts that data in response to reading data from the providing RAM and writing data to a receiving FIFO. A pointer manager maintains a pointer that points to a first valid byte in a sub-block of data into the correct bytes lanes of the FIFO by moving the pointer as data is shifted into and out of the shift register.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: March 23, 2004
    Assignee: Emulex Corporation
    Inventors: Eric Peel, Bradley Roach, Qing Xue
  • Patent number: 6639850
    Abstract: A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored data to respective adjacent registers in sequence. The plurality of first and second registers are connected in one-to-one correspondence to a plurality of input terminals or to a plurality of output terminals. A first scan input terminal is formed at one end of the plurality of first series-connected registers, and a first scan output terminal is formed at the other end. A second scan input terminal is formed at one end of the plurality of second series-connected registers, and a second scan output terminal is formed at the other end. An operation control circuit controls operations of the circuits and the plurality of first and second registers.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: October 28, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryo Fukuda
  • Patent number: 6628539
    Abstract: A multi-entry register file cell includes multiple memory elements. A value stored in each of the multiple memory elements may be individually read from the register file cell in response to asserting a single word line.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: September 30, 2003
    Assignee: Intel Corporation
    Inventors: Sudarshan Kumar, Gaurav G. Mehta, Sadhana Madhyastha, Jiann-Cherng Lan
  • Patent number: 6622204
    Abstract: An apparatus comprising one or more memory blocks in a programmable logic device. The memory blocks may be configured as content-addressable memory having arbitrarily adjustable tag and data widths.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: September 16, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: Christopher W. Jones, Steven J. E. Wilton
  • Patent number: 6577524
    Abstract: An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload portions for storage of payload data and a portion for storage of administrative data. Based on the contacts of the administrative data, certain payload portions may be enabled or disabled.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: June 10, 2003
    Assignee: Intel Corporation
    Inventors: David M. Brooks, Vivek Tiwari
  • Patent number: 6525973
    Abstract: A one-shot system for loading a bitline shift register with a typical test pattern is described. Each bitline latch within the bitline shift register is augmented with a one-shot circuit that may pull-up or pull-down the value stored in the bitline latch. The choice of a particular memory test pattern dictates the control of the one-shot circuit.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: February 25, 2003
    Assignee: Xilinx, Inc.
    Inventors: Farshid Shokouhi, Michael G. Ahrens