Abstract: A memory device includes a magnetic track layer extending on a substrate, the magnetic track layer having a folded structure that is two-dimensionally villi-shaped, a plurality of reading units including a plurality of fixed layers and a tunnel barrier layer between the magnetic track layer and each of the plurality of fixed layers, and a plurality of bit lines extending on different ones of the plurality of reading units, the plurality of reading units being between the magnetic track layer and corresponding ones of the plurality of bit lines.

Abstract: A NAND interface having a reduced pin count configuration, in which all command and address functions and operations of the NAND are provided serially on a single serial command and address pin, and data is transmitted over data pins in response to commands and addresses received on the serial command and address pin.

Abstract: A high-density semiconductor device includes a first input/output line connected among a plurality of banks on a core area storing data, so that it transmits data, a second input/output line connected to a data pad capable of performing data input/output operations at a Peri-area, so that it transmits data, a first repeater connected between the first input/output line and the second input/output line, for transmitting data of the first input/output line to the second input/output line in response to a read enable signal enabled by a read command, and a second repeater connected between the first input/output line and the second input/output line, for transmitting data of the second input/output line to the first input/output line in response to a write enable signal enabled by a write command.

Abstract: A magnetic shift register includes at least a magnetic memory track of which several walls separate the memory track into multiple magnetic domains to serve as magnetic binary memory cells. The magnetic memory track includes multiple data regions. Each data region has multiple of the magnetic binary memory cells for storing bit data at a quiescent state and registering at least one of the bit data shifted from the adjacent data region at a shifting state. Wherein, the bit data of the magnetic binary memory cells is shifted between the adjacent two data region under an operation current.

Abstract: A semiconductor device having a register and an information generation circuit can reduce data to be transferred, and consequently save electric power. The register stores first information. The information generation circuit generates, in response to a signal acquired from the an exterior of the device, second information indicating which bits of the first information is to be inverted.

Abstract: Disclosed is a FIFO peek access device that utilizes a peek signal to access data stored in a FIFO without losing or erasing data. The peek signal is applied to read address logic and prevents the incrementing of the pointers in the peek address logic, so that after a read enable signal is asserted, the same data block can be accessed again on the next read enable signal.

Abstract: Embodiments of the invention relate generally to a coupling device, to a processor arrangement, to a data processing arrangement, and to methods for transmitting data. In an embodiment of the invention, a coupling device for coupling a memory, which has a serial data output, with a processor, which has a parallel data input, is provided. The coupling device may include a serial data interface configured to receive data, a parallel data interface configured to transmit data, and a cache memory coupled to the serial data interface and to the parallel data interface, wherein the cache memory is configured to receive and store data, which have been received in a serial data format via the serial data interface, and to transmit data stored in the cache memory to the parallel data interface.

Abstract: A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein the plurality of memories are controlled by the switch. By suppressing reflection and loads on the bus, a higher data transmission speed can be obtained.

Abstract: A magnetic shift register uses the inherent, natural properties of domain walls in magnetic materials to store data. The shift register uses spin electronics without changing the physical nature of its constituent materials. The shift register comprises a fine track or strip of magnetic materials. Information is stored as domain walls in the track. An electric current is applied to the track to move the magnetic moments along the track past a reading or writing device. In a magnetic material with domain walls, a current passed across the domain wall moves the domain wall in the direction of the current flow. As the current passes through a domain, it becomes “spin polarized”. When this spin polarized current passes through the next domain and across a domain wall, it develops a circle of spin torque. This spin torque moves the domain wall.

Abstract: A magnetic shift register uses the inherent, natural properties of domain walls in magnetic materials to store data. The shift register uses spin electronics without changing the physical nature of its constituent materials. The shift register comprises a fine track or strip of magnetic materials. Information is stored as domain walls in the track. An electric current is applied to the track to move the magnetic moments along the track past a reading or writing device. In a magnetic material with domain walls, a current passed across the domain wall moves the domain wall in the direction of the current flow. As the current passes through a domain, it becomes “spin polarized”. When this spin polarized current passes through the next domain and across a domain wall, it develops a circle of spin torque. This spin torque moves the domain wall.

Abstract: A ferromagnetic pinned layer (1) kept at a fixed magnetic orientation by a pinning layer (4) is separated from a ferromagnetic free layer (3) by a Mott insulator coupling layer (2). A controllable voltage source (5) is connected between the pinned layer (1) and the free layer (3). A sublayer of the coupling layer (2) whose width (d) increases with the voltage is converted to an electrically conducting and magnetically coupling metallic state. The magnetic exchange field acting on the free layer (3) which is controlled by the applied voltage via the width (d) of the electrically conducting sublayer of the coupling layer (2) can be used to switch the free layer (3) between states of parallel and antiparallel orientations with respect to the magnetic orientation of the pinned layer (1). This is used in memory cells and in a write head.

Abstract: The present invention discloses an interface circuit suitable for a high-speed semiconductor device.

Abstract: An optical device and a method for manufacturing the optical device. An optical device having a molded-package structure includes: a lead frame having a ferrule-mounting portion; a ferrule mounted on the ferrule-mounting portion; and a molding resin that encapsulates the lead frame and the ferrule, molding, except that an end of the ferrule protrudes through and outside of the surface of the molding resin. The first groove parallel to a longitudinal axis of the ferrule is located on the ferrule-mounting portion and the ferrule is placed on the first groove. Thus, the ferrule is hardly ever detached from a ferrule-mounting portion, an optical fiber is hardly ever damaged, and an optical coupling is hardly ever obstructed.

Abstract: The semiconductor integrated circuit comprises a parallel-serial converter for converting parallel data read from memory cells into serial data and a switch control circuit for receiving a control signal and controlling the parallel-serial converter. The parallel-serial converter has a plurality of switches connected in a predetermined order. The switch control circuit controls the order of connecting the switches in accordance with the control signal so that parallel data are converted into serial data in a predetermined bit order. This minimizes delay elements formed on the transmission paths of parallel data. Specifically, for example, it eliminates the need for a conversion circuit for changing the bit order of parallel data. This results in faster data read operations from memory cells. Each of the switches in the parallel-serial converter operates in synchronization with a clock signal supplied from the exterior.

Abstract: A mechanism to effectively retrieve residual data received from a serial data source is provided. As the shift register receives serial data from the serial data source, the activities and content of the shift register is monitored. Status bits are set to reflect the activities and content. These status bits are used to determine whether the shift register contains residual data and whether such residual data should be ignored the serial data received from the serial data source is output to a destination.

Abstract: Disclosed is a bubble memory system that includes a plurality of bubble memory chips. Each of the chips have a number of minor loops, but only a predetermined portion of the loops are utilized to store information therein. The remaining loops may be defective and are not used. Data words that are to be stored in the bubble memory chips are passed through a first FIFO circuit which scrambles the bits in the words prior to their storage in the bubble memory chips. Due to this scrambling operation, no bits are stored in the defective loops. Data bits that are received from the bubble memory chips are passed thorugh a second FIFO circuit. There, all of the bits of each word are then realigned and presented at the FIFO output in parallel.