Abstract: A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.

Abstract: A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.

Abstract: Mechanisms for controlling a commercial transaction is presented. An article of manufacture has a time cell that is read by an electronic apparatus. In response to a determination of a state of the time cell by the electronic apparatus, usage of the article of manufacture in a commercial transaction is enabled or denied based on the determined state of the time cell. The expiration period of a time cell controls the time period during which the commercial transaction is enabled or is denied to be performed; an unexpired time cell may both enable or deny performance of a commercial transaction, and an expired time cell may also both enable or deny performance of a commercial transaction. The time cell may be used to restrict the usage period of a coupon, a promotional offer, a pre-paid service, or some other commercial transaction that involves an article of manufacture.

Abstract: An apparatus for estimating data relating to a time difference between two events includes a delay line having a plurality of stages. Each stage has a delay difference between a first delay in a first part and a second delay in a second part. This delay difference is measured by a phase arbiter in each stage, which outputs an indication signal indicating whether the first event of two events in the first part precedes or succeeds a second event of the two events in the second part. A summation device is provided for summing over the indication signals of the plurality of stages to obtain a sum value. The sum value indicates a time difference estimate.

Abstract: Methods and arrangements to model an asynchronous interface are disclosed. Embodiments include transformations, code, state machines or other logic to generate a skew pattern for a semi-static or time-constrained, asynchronous interface and employ the skew pattern in data transfers during a time interval in which the asynchronous interface. Embodiments may than alter the skew pattern in at the expiration of the time interval. In many embodiments, changes to the skew pattern may be substantially non-deterministic. In other embodiments, chances to the skew pattern may follow a heuristic or other dynamic or pre-determined pattern.

Abstract: A delay test system includes an electronic circuit, such as a normal circuit which has a portion to be tested and a plurality of flip-flop circuits. In this event, each of flip-flop circuits is serially connected to each other to perform a delay test for said normal circuit. Further, a first clock input terminal is connected to the flip-flips and a normal circuit to input a normal mode clock signal. Moreover, a second clock input terminal is connected to the flip-flop circuits and the normal circuit to input a test clock signal. With such a structure, an input and output operation of data signals is carried out in synchronism with edge timings determined by both the normal mode clock signal in the normal mode on the condition that the test clock signal is not supplied to the second clock input terminal. On the other hand, the first and second clock input terminals are separately driven by the normal mode clock signal and the test clock signal in the test mode.

Abstract: A temperature compensated clock and method of clocking systems are provided. The clock preferably has an oscillator for generating an oscillating waveform signal at a preselected frequency and a frequency divider responsive to the oscillator for dividing the frequency of the oscillating waveform signal. A temperature monitoring circuit is positioned responsive to a voltage input signal independent of temperature and a voltage input signal proportional to temperature for monitoring temperature variations. A temperature compensating circuit, preferably including a programmable scaling circuit, is responsive to the frequency divider and the temperature monitoring circuit for scaling the divided frequency of the generated waveform and thereby advantageously produces a temperature compensated output timing signal.

Abstract: A trace coloring system enhances signal information that is provided to a user of a signal measurement device, for example, a digitizing oscilloscope or spectrum analyzer, having a color display for displaying graphical depictions of electrical signals. Trace coloring logic (hardware, software, or a combination thereof) colors a trace with different colors, each indicating a corresponding range of signal values. As an example, in the context of an oscilloscope, the trace may be colored with various colors to visually indicate which areas of the trace correspond to particular logic levels. A first color may be allocated to a logic low ("0"), a second color to a logic high ("1"), a third color to an indeterminate range that is between logic low and high, and a fourth color to an extreme value that is outside a desired or acceptable predefined logic range. In the preferred embodiment, the trace coloring logic is implemented in software that is executed by a processor.

Abstract: A clock doubler circuit with duty cycle control includes an exclusive-OR, a toggle flip-flop, a plurality of control bit flip-flops, a primary delay element, a plurality of secondary delay elements, and a multiplexer. The toggle flip-flop has a clock input connected to an output of the exclusive-OR, and an inverted data output connected back to a data input of the toggle flip-flop and connected forward to an input of the primary delay element. An output of the primary delay element is connected to an input of the multiplexer and to individual inputs of the plurality of secondary delay elements which in turn, have outputs connected to other inputs of the multiplexer. A plurality of control bits generated, for example, by a computer program running on a host processor, are respectively provided to data inputs of the plurality of control bit flip-flops which in turn, have data outputs connected to select inputs of the multiplexer.

Abstract: A programmable timing unit having a number of event markers circuits that receive a master clock signal and generate an output when a predetermined time occurs. Optionally, the event marker circuit can add an interpolated delay time to provide greater resolution than the master clock circuit. The output is programmably coupled to any of a number of function circuits. Each function circuit has a trigger input for receiving the event signal and output for providing the delayed output function.

Abstract: A Vernier delay line interpolator provides a precision level smaller than a clock period by delaying a periodic pulse signal in a delay line which has equally time-spaced taps and a total delay that is a harmonic H greater than 1 of the pulse period. The taps of the delay line are latched and decoded to derive the fraction of the pulse period that has passed. When the interpolator is combined with a coarse counter, misalignment between their outputs is prevented by having the coarse counter count both edges of the periodic pulse signal so as to provide redundant bits between the counter and the interpolator. If the redundant bits are not equal, the counter output is corrected before it is combined with the output of the interpolator.

Abstract: A time measurement circuit (100) measures a time interval between two events. The time measurement circuit (100) includes two digital phase counters (10' and 10"), a period counter (210), and a digital calculator (310). The first digital phase counter (10') converts a time interval from a leading edge of a start signal to a leading edge of clock signal following the start signal into a first binary number. The second digital phase counter (10") converts a time interval from a leading edge of a stop signal to a leading edge of clock signal following the stop signal into a second binary number. The period counter (210) converts a time interval between the two leading edges of the clock signal into a third binary number. The digital calculator (310) combines the three binary numbers to generate a number representing the time interval between the start signal and the stop signal.

Abstract: A delay time measurement apparatus of delay circuit is configured to minimize the influence of periodic noises for accurately measuring the delay time.

Abstract: A programmable timing unit having a number of event markers circuits that receive a master clock signal and generate an output when a predetermined time occurs. Optionally, the event marker circuit can add an interpolated delay time to provide greater resolution than the master clock circuit. The output is programmably coupled to any of a number of function circuits. Each function circuit has a trigger input for receiving the event signal and output for providing the delayed output function.

Abstract: A digital data propagation delay margin monitoring circuit that includes (a) a digital data propagation unit having a send flip-flop, a combinatorial delay, and a receive flip-flop; and (b) a margin detection circuit having a test flip-flop that receives the same input as the receive flip-flop and is configured to have a set up time margin or a hold time margin that is less than the set up margin or hold time margin of the receive flip-flop by a predetermined amount, depending upon which margin is being monitored. The outputs of the receive flip-flop and the test flip-flop are compared by a comparison circuit which provides an indication of when the outputs of the receive flip-flop and the test flip-flop are different, which indicates that the monitored margin of the receive flip-flop has been reduced to a predetermined margin or less.

Abstract: A circuit for verifying the accuracy a tester, for enhancing its calibration and for providing tracking between testers. The circuit includes a delay element, first and second multiplexers connected to the input and output of the delay element, respectively, and a feedback path linking outputs of the second multiplexer to inputs of the first multiplexer to provide an oscillation. The delay between an input of the first multiplexer to an output of the second multiplexer is measured and this delay is compared to the frequency domain measurement of the same to provide an indication of the accuracy of the tester.

Abstract: An apparatus for measuring intervals of time, which requires only a simple counter circuit (15) and delay circuit (17), through which electrical pulses travel. The counter circuit (15) counts pulses during the time interval. During each count of the counter circuit (15), the delay circuit (17) tracks the position of the pulse. The output of the two circuits are a counter word and a vernier word, such that the counter word may be multiplied by the period of each pulse, and the product added to the vernier word, to obtain the time interval measurement. The apparatus may also be used for frequency measurement.

Abstract: An adaptive time period measurement technique which provides full speed for every measurement period with increased resolution afforded from repeated measurements. The time measure is produced by adaptively filtering a number of prior time measures. Each measurement includes a count and a fractional part from a controlled variable delay interposed in the measurement system. This variable delay is controlled over a number of measurements to cover the entire range of one clock cycle, preferably in accordance with a reversed binary progression algorithm. The adaptive filtering is preferably a self-modifying, classic low pass filter with a roll off which depends on the rate of change and direction of change of the measurerd time period. Thus the present invention provides all the resolution feasible based upon the rate of change of the measured quantity.

Abstract: A digital time base with differential period delay uses the difference in period between a master oscillator and a voltage controlled oscillator phase-locked to the master oscillator to achieve small time delay increments. The oscillators are used to drive respective delay generator trigger channels that have programmable counters and state machines. A first programmable counter is a clock counter to generate a lock signal to initiate a delay sequence, the lock signals from the respective channels being input to a phase detector to generate an error signal to keep the VCO phase-locked with the master oscillator. A second programmable counter is a delay counter that is controlled by a delay state machine to generate a delay signal. The delay signal is input to respective trigger state machines to generate the desired trigger signals, the duration of the trigger signals being a function of a third programmable counter.

Abstract: An automatic period and frequency measurement feature for an analog oscilloscope uses a single sweep signal and a delay trigger to detect edges. The sweep rate for the sweep signal is set to the highest rate that provides at least one cycle of the input signal on a display. By varying a programmable level that is compared with the sweep signal, a first event after the start of the sweep is searched for. Once a first event is located, then a second event is searched for in the same manner, reducing the sweep rate if necessary to provide the second event on the display. From the programmable levels corresponding to the first and second events a period and frequency are computed and displayed.

Abstract: A time interval counter permits the time interval between a first signal and one of a series of timing signals to be measured to less than .+-.2 nanoseconds without using microwaves and high power-consuming devices. The time interval counter uses a first passive delay time operated from the first signal, which occurs at an unknown interval from the timing signals, to produce a plurality of binary outputs spaced from each other by known equal time intervals that are substantially less than the interval between the timing signals, and a second passive delay line operated by the timing signal, which occurs after the first signal, to produce a plurality of sequential outputs spaced from each other by a plurality of known sub-time intervals that are substantially less than the time interval between the plurality of binary outputs of the first delay line.

Abstract: Time measurement apparatus comprising a delay line having a plurality of taps, each tap having an associated latch. An inverting AND gate has its output connected to an initial tap of the delay line, an input signal having two conditions connected to one of its inputs, and has its other input connected to a later tap of the delay line.The arrangement causes oscillation of the delay line in the presence of the first condition of the input signal. A counter counts the oscillations of the delay line, and the latches are caused to operate simultaneously on the second condition of the input signal.The value stored in the counter and the pattern stored in the latches is used to derive the duration of the first condition.

Abstract: The fabrication of a printed circuit board (26) usually includes the step of testing the board with a testing machine (24) to verify operability. The testing machine accomplishes such testing by transmitting test signals to the board via a transmission line (36) and then analyzing each response signals returned from the board in response to the test signals. To reduce the incidence of error, the testing machine (24) is compensated for the propagation delay of the line (12) which is measured by launching a first string of pulses into one end of the line whose opposite end is left open. A second string of pulses is sinultaneously launched into a programmable delay line (16) which delays each second pulse by an adjustable interval. After the generation of each first and second pulse, a check is made whether the first pulse has been reflected back to the first end of the transmission line at the same time the second pulse reaches the output of the delay line.

Abstract: The fabrication of a printed circuit board (26) usually includes the step of testing the board with a testing machine (24) to verify operability. The testing machine accomplishes such testing by transmitting test signals to the board via a transmission line (36) and then analyzing each response signals returned from the board in response to the test signals. To reduce the incidence of error, the testing machine (24) is compensated for the propagation delay of the line (12) which is measured by launching a first string of pulses into one end of the line whose opposite end is left open. A second string of pulses is simultaneously launched into a programmable delay line (16) which delays each second pulse by an adjustable interval. After the generation of each first and second pulse, a check is made whether the first pulse has been reflected back to the first end of the transmission line at the same time the second pulse reaches the output of the delay line.

Abstract: A digital time base with analog interpolation provides a variable reference voltage to assure that the period of an analog ramp between a zero value and a maximum value is equal to the time interval between range clock pulses. A time base error is determined by establishing a zero reference level on a test pulse rising edge corresponding to the zero value of the analog ramp, and then establishing a maximum level on the test pulse corresponding to the maximum value of the analog ramp initiated one clock pulse prior to the test pulse. The difference between the two levels on the test pulse represents the time base error. A microprocessor provides a corrected reference voltage as the maximum value so that the maximum delay of the analog ramp equals the time interval between clock pulses.

Abstract: Apparatus for indicating the timing relationship between a reference point of a repetitive input signal, e.g. the horizontal sync point of a video signal, and a signal element that repeats at a higher frequency than the input signal, e.g. an element of the color burst, comprises a phase-locked oscillator for generating a continuous wave signal that is in phase with the signal element. The continuous wave signal is used to generate a train of pulses having a repetition frequency that is equal to the repetition frequency of the signal element and is selectively variable in phase relative to the continuous wave signal, and this train of pulses is used to modulate a display of the repetitive input signal in a dimension other than one that is used in a normal waveform display, e.g. intensity.