Abstract: A method of programming a ring oscillator for use as a temperature sensor comprises selecting an initial number of delay elements for use in a ring oscillator. The method further comprise starting a system clock counter and counting pulses of the ring oscillator until the system clock counter reaches a programmed value. The method also comprises determining whether a number of counted ring oscillator pulses is between lower and upper count thresholds and changing the number of delay elements for the ring oscillator as a result of the number of counted ring oscillator pulses being less than the lower count threshold or greater than the upper count threshold.

Abstract: A method and apparatus for externally aided self adjusting real time clock have been disclosed. A circuit having a pulse train output is coupled to an adjusting circuit, a real-time clock is coupled to the adjusting circuit, and a proportional integral derivative time processor is coupled to the adjusting circuit, and where the adjusting circuit affects the pulse train output.

Abstract: An electronic apparatus includes a first frequency division portion that frequency-divides a clock signal by a first frequency division ratio, a second frequency division portion that frequency-divides the first clock signal which has been frequency-divided by the first frequency division portion by a second frequency division ratio, and a regulation frequency division portion that performs logical regulation of the clock signal using a second clock signal which has been frequency-divided by the second frequency division portion.

Abstract: In a frequency corrector, a counter divides a clock signal CK to be input into a fraction of a natural number larger than one to generate a signal having a clock frequency. The counter corrects the number of clock pulses of the signal having the clock frequency in response to a correction signal to output a first frequency-divided signal. A frequency divider circuit divides the first divided signal to output a unit time signal having another frequency and another frequency-divided signal Db composed of plural frequencies. A correction timing generator decodes the both divided signals to detect a correction timing for the first divided signal, and generates plural correction timing signals different in timing from each other. A correction signal generator generates the correction signal in response to the correction timing signals and correction values to provide the correction signal to the counter.

Abstract: A high definition video transmitter and receiver are disclosed. The transmitter provides high definition video to a one-point receiver or to multipoint receivers. The transmission network is asynchronous and the receiver re-synchronizes the video. The transmission can be wired or wireless.

Abstract: Provided is an electronic clock which makes no erroneous determination of rotation detection and suppresses unnecessary current consumption even when being provided with the second hand having a large moment of inertia. The electronic clock uses a first detection mode determination circuit 112 and a second detection mode determination circuit 113 to perform the rotation detection. The electronic clock includes a determination selecting circuit 113c as changing means for changing the determination period of the second detection mode in accordance with the determination period of the first detection mode. Even when the current waveform is disturbed, erroneous determinations are prevented in a way that the determination terminal of the second detection mode is shortened if the first detection mode terminates earlier.

Abstract: In a frequency corrector, a counter divides a clock signal CK to be input into a fraction of a natural number larger than one to generate a signal having a clock frequency. The counter corrects the number of clock pulses of the signal having the clock frequency in response to a correction signal to output a first frequency-divided signal. A frequency divider circuit divides the first divided signal to output a unit time signal having another frequency and another frequency-divided signal Db composed of plural frequencies. A correction timing generator decodes the both divided signals to detect a correction timing for the first divided signal, and generates plural correction timing signals different in timing from each other. A correction signal generator generates the correction signal in response to the correction timing signals and correction values to provide the correction signal to the counter.

Abstract: The clock signal output device has a crystal oscillator for generating a reference clock signal and generating and outputting an output clock signal having a prescribed frequency on the basis of the reference clock signal. The device also has an atomic oscillator for generating a clock signal having higher precision than a crystal oscillator, an intermittent time management unit for intermittently driving the atomic oscillator, and a correction unit for receiving correction data for correcting the offset amount of the output clock signal on the basis of a clock signal each time the atomic oscillator is driven, and correcting the output clock signal on the basis of the correction data.

Abstract: An integrated circuit for analogue electronic watch applications, comprising an oscillator circuit for generating clock signals, stepper motor driver circuit for generating motor driving signals, a plurality of trimming capacitors for fine-tuning the output frequency of the oscillator circuit and a corresponding plurality of electronic switches for selectively connecting/disconnecting said trimming capacitors to said oscillator circuit and switching circuitry for switching-in and/or -out the electronic switch, wherein said stepper motor driver circuit being connected to said oscillator circuit and comprising means for converting said clock signals into said motor driving signals, said switching circuitry comprises means to control the switching-in and/or switching-out of said electronic switches whereby oscillator frequency is fine-tuned, said plurality of electronic switches being selectively controllable and operable by switching control signals applied at said frequency trimming port.

Abstract: Accuracy adjustment apparatus for a timepiece has an accuracy adjustment data input control section including a case-mounted switch such as a crown of the timepiece. A crown state detection signal is used to determine the state of the crown. When an accuracy adjustment data input mode is indicated based on the position of the crown, an indicator of the timepiece is driven to provide a visual indication of accuracy adjustment data selectable by operation of the crown. When the proper accuracy adjustment data has been selected, the data is stored to a memory.

Abstract: A method for adjusting the rate of a horological module, said horological module including a printed circuit (1) on which are mounted in particular a quartz (10) and an integrated circuit (20) including an oscillator (21) driven by the quartz (10), a frequency divider circuit (22) with several stages (22.1 to 22.15), an adjustment circuit (23) allowing the introduction of a correction factor of the division ratio of said frequency divider circuit (22), and a memory circuit (24) containing data (N) representing said correction factor. The adjustment method according to the present invention uses a laser device to allow said data (N) representing the correction factor to be coded by the selective destruction of fuses (F1, F2; F.1 to F.6; F.1* to F.6*) forming memory elements of said memory circuit (24).

Abstract: A control circuit adapted to be switched to a standby mode during periods without control requirement and to be repeatedly reset during the standby mode of operation for a short wake-up period each to a full mode of operation. The control circuit comprises a standby oscillator that is operative also in the standby mode and that is adjusted during wake-up periods.

Abstract: A regulating circuit for a quartz crystal oscillator-based timepiece is capable of compensating for large deviations in oscillation frequency of the quartz crystal oscillator. A frequency divider sequentially divides the reference clock by one-half. A regulation data setting circuit sets logical regulation data used to compensate for deviations in the oscillation frequency of the oscillator from a desired value. A regulation circuit adjusts the frequency dividing ratio of the frequency dividing circuit based on the logical regulation data in accordance with a predetermined cycle and controls in such a manner that the frequency of a divided output signal of the frequency divider has a predetermined frequency. When the frequency of the divided output signal cannot coincide with the predetermined frequency using the set logical regulation data, the range of adjustment is shifted using data set in a switch during production of the timepiece.

Abstract: A temperature compensation system includes a first oscillator to generate a number of pulses which vary from a desired frequency as a function of temperature of the first oscillator. The system also includes a second oscillator to generate digital pulses at a corrective frequency which is greater than the desired frequency. A sensor provides an temperature signal for the first oscillator. A digital memory has a digital error table addressable by a signal corresponding to the temperature signal to provide a number of pulse errors corresponding to temperature error for each of the number of pulses. Each pulse error is a function of the corrective frequency and a temperature versus frequency characteristic of the first oscillator. An accumulator receives each pulse error to generate a cumulative error corresponding to one of the number of pulses. A variable delay device counts a quantity of corrective pulses from second oscillator to provide a delayed output pulse in accordance with the desired frequency.

Abstract: A digital trimming circuit is used to produce a stable time reference signal. This type of reference time signal can be used in equipment, such as watches, which have motors and acoustic outputs that interfere with producing the time reference signal. A basic oscillation frequency, which is produced by an oscillator circuit, is frequency divided to form the generic time reference signal. The digital trimming circuit generates a control signal to shorten the period of the time reference signal by predetermined amounts based on correction data. The control signal is in the form of pulses which can be dispersively applied to create substantially equal intervals between pulses during one time period of the time reference time signal. While maintaining the necessary digital trimming amount in one digital trimming time period, an expansion/reduction amount of the time reference signal is suppressed at one digital trimming time instant.

Abstract: A digital trimming circuit is used to produce a stable time reference signal. This type of reference time signal can be used in equipment, such as watches, which have motors and acoustic outputs that interfere with producing the time reference signal. A basic oscillation frequency, which is produced by an oscillator circuit, is frequency divided to form the generic time reference signal. The digital trimming circuit generates a control signal to shorten the period of the time reference signal by predetermined amounts based on correction data. The control signal is in the form of pulses which can be dispersively applied to create substantially equal intervals between pulses during one time period of the time reference time signal. While maintaining the necessary digital trimming amount in one digital trimming time period, an expansion/reduction amount of the time reference signal is suppressed at one digital trimming time instant.

Abstract: To produce a time-base signal for timekeeping, an oscillator circuit generates an oscillator clock signal, which is counted cyclically with a programmable cycle length to establish a time-base cycle. The time-base signal is set and reset once in each time-base cycle. The oscillator clock signal is also counted with a fixed cycle length to establish an adjustment cycle, which is longer than the time-base cycle. In each adjustment cycle, the length of one or more time-base cycles is altered by a total amount determined by adjustment data stored in a non-volatile memory, then the time-base cycle length is restored to its nominal value. The average frequency of the time-base signal can be adjusted by writing appropriate adjustment data in the non-volatile memory.

Abstract: The hand held decimal timer circuit comprises: a power supply having a positive voltage output and a ground or common output; a counter circuit coupled to the power supply; a frequency divider circuit coupled to the counter circuit and to the power supply; a clock circuit including an oscillator coupled to the frequency divider circuit; a display circuit coupled to the counter circuit; a switch circuit coupled to the counter circuit; and, the frequency divider circuit including: (a) a first input for receiving a clock signal from the clock circuit, (b) a second input and a third input for receiving, respectively, a positive voltage reference and a ground voltage reference from the power supply, (c) a 12 bit binary counter which counts the clock cycles from the clock circuit and outputs, on a plurality of output pins, a number of clock cycles in binary form, (d) a pair of NAND gates each having at least three inputs and an output, the inputs being coupled to at least some of the plurality of output pins for re

Abstract: An adjustable vibrations counter (20) and an elapsed time counter and switch (18) that select and adjust one second durations, the adjustment depending on whether the timekeeping rate of a watch or clock is fast or slow. The adjustable vibrations counter provides for an increase or decrease in the number of crystal (12) vibrations that are counted during each adjusted one second duration. The elapsed time counter and switch provides for the number of seconds that are selected for adjustment during each hour or day.A slide switch (22) or other means for changing the number of crystal vibrations that are counted during an adjusted one second duration, thus providing the timekeeping rate regulation. A display (28) of the amount of timekeeping rate adjustment that has been entered into a watch or clock.

Abstract: Apparatus for digitally trimming the output frequency of a real-time clock is disclosed. The output frequency of a divider chain is adjusted by the contents of a trim constant register. The amount of correction and direction (slow or fast) to be effected is determined by the trim constant register. During "slow" real-time clock operation, the divider chain "shortens" the next second produced by the real-time clock. During "fast" real-time clock operation, the production of the next second is blocked and then a portion of the "blocked" signal is "added back" to effectively "lengthen" the next second produced by the real-time clock.

Abstract: A method of adjusting the pulse rate of a local clock (1) by generating a first pulse train at a first predetermined rate, dividing the pulse train by a divisor (3) to produce a second pulse train. The value of the divisor (3) is selected (4,5,6) so that the rate of the second pulse train is adjusted within a predetermined range.

Abstract: An integrated circuit for an electronic timepiece includes at least one semiconductor nonvolatile memory device. Reference data can be checked across a pair of output terminals prior to being stored in at least one EPROM to check the accuracy and acceptability of the reference data for driving a motor of the timepiece. The reference data once written into the EPROM serves as control data. Both the reference data and control data are used for controlling at least one function of the timepiece. The control data also can be checked across the output terminals to determine its accuracy and acceptability for driving the motor. Testing of the reference data and control data can be performed on a faster than real time basis.

Abstract: This programming arrangement for a non-volatile memory incorporated in the inner circuit of a timepiece for adjusting the frequency of the time base thereof includes a support provided with a connector to be plugged in in place of the energy cell. The rate of division of the frequency divider is adjusted by the introduction into the memory of a number k representative of the frequency difference between the time base frequency and a standard frequency. To effect this the arrangement comprises an electronic circuit external to the timepiece and which is coupled thereto by the connector. The electronic circuit introduces the number k into certain predetermined stages of the divider. When such number k is thus introduced the state of such stages is blocked by the inner circuit of the timepiece such state then being transferred into the non-volatile memory.

Abstract: In a temperature gradient adjustor for a temperature-compensated electronic watch, the temperature gradient adjusting range can be widened without any drop in the temperature gradient adjusting resolution of a temperature sensitive oscillator by adding a roughly temperature gradient adjusting variable frequency divider for variably dividing the frequency of the output of a temperature sensitive oscillator and by operating the temperature gradient adjustor at a value which is prepared by adding a constant numerical value to temperature gradient adjusting numerical information.A constant voltage supplying to a temperature sensitive oscillator can be finely adjusted from external side so as to optimize a linearity of frequency versus temperature characteristic.

Abstract: An electronic timepiece has an oscillator for generating a high frequency time standard signal which is frequency-divided by a multi-stage divider circuit. A memory stores time adjustment information for use in adjusting the time in the event the oscillator time standard signal is higher than a predetermined frequency. The memory is connected to a preset circuit for presetting the divider circuit in accordance with the content of the memory. The divider circuit comprises 16 dividing stages and when no time adjustment is needed, the divider output is taken from the 15th stage in the conventional manner whereas when time adjustment is being carried out, the divider output is taken from the 16th stage. A selecting circuit applies either the output form the 15th or 16th stage to a display device depending on whether or not time adjustment information is stored in the memory.

Abstract: A logic regulation circuit for regulating the frequency dividing ratio of a variable frequency divider of an electronic timepiece comprises a first switch group having a plurality of ON and OFF switching states representative of different frequency rates and a second switch group having a plurality of ON and OFF switching states representative of frequency rate adjustment values. A first set of memory circuits is connected to the first switch group for memorizing the ON-OFF information thereof, and a second set of memory circuits is connected to the second switch group for memorizing the ON-OFF information thereof.

Abstract: An electronic timepiece is provided with a temperature compensation system which combines precise control of the timebase oscillator circuit frequency over a narrow temperature range with control of the frequency divider circuit operation to provide relatively large step changes in compensation, thereby providing accurate temperature compensation over a very wide temperature range. Data for control of this compensation is produced by computing the square of a data value which varies proportionally with temperature, with the resultant data being adjusted to provided compensation control which exactly matches the temperature characteristic of the timebase oscillator circuit.

Abstract: A linearizer circuit comprises a frequency mixer which mixes a first frequency varying in accordance with a change in a parameter and a second frequency from a reference oscillator which has no dependence upon any parameter at a given proportion, and a derivation circuit for producing an output pulse corresponding to the average period of an output from the mixer, thus providing a linearized output for the parameter. The linearizer circuit may be assembled into a watch as means to detect the environmental temperature of the watch. By detecting temperature information with this means, a temperature compensation of a clock signal may be achieved in accordance with a temperature offset from a reference temperature.

Abstract: In a circuit arrangement for adjusting a pulse frequency of a quartz-controlled clock or watch there are present a pulse generator, a multi-stage frequency divider arranged behind said pulse generator and in front of a counter, as well as adjustable means for adding clock pulses in front of at least one predeterminable frequency divider stage during a counting cycle, and adjustable means for subtracting a clock pulse between a frequency divider stage of higher frequency and a frequency divider stage of lower frequency in a counting cycle. The higher-frequency frequency divider stages are developed as fixed, pre-settable counters, and between the pre-settable counter and the next following frequency divider stage the adjustable means for subtracting a clock pulse are arranged. In this way the current consumption of the circuit arrangement can be kept small since its elements oscillate only with a relatively low frequency.

Abstract: The timepiece includes a low frequency oscillator serving as time base and rranged to feed a first chain of frequency dividers having an adjustable division rate in order to display the time and a high frequency oscillator feeding a second chain of frequency dividers. During an imprecise period established by the first chain (3) reference pulses from the second chain (7) are counted thereby to establish a binary value (HF-DF) representing the amount of imprecision of the first chain in respect of the reference. This value is transferred into a memory in order to correct directly or indirectly the division rate of the first divider chain. There is thus obtained an oscillator having the stability of a high frequency oscillator but with energy consumption only slightly exceeding that of a low frequency oscillator.

Abstract: An electronic timepiece having a quartz crystal oscillator circuit as a timebase signal source is provided with a temperature compensation system to compensate timebase signal frequency deviations with temperature, all components of the system being incorporated in the timepiece IC chip. The system is based on a temperature-sensitive voltage stabilizer circuit whose output voltage is current-converted to control the frequency of a temperature-insensitive oscillator circuit. Date generated on the basis of the latter oscillator frequency is applied to compensate the timebase signal frequency, by a capacitor switching technique.

Abstract: An electronic timer with a case having two windows and a manually adjustable control on the exterior. The output of an oscillator within the case is applied to a first frequency divider dividing the frequency by a factor manually selected by a switch indicating the factor in one window. The output of the first divider is applied to a second divider dividing by a factor selected manually by a second switch viewable through the other window and indicating timing in seconds, minutes, hours or days.

Abstract: In an electronic timepiece having a primary frequency divider circuit coupled to receive a standard frequency signal and comprising a group of P-channel FETs and a group of N-channel FETs, a bias circuit supplies a bias input to the P-channel FET group and a separate bias input to the N-channel FET group. By providing these bias inputs through current mirror coupling from a standard current source, the response of the primary frequency divider circuit to low amplitudes of the standard frequency signal can be made substantially independent of timepiece battery voltage variations, over a wide range of battery voltages.

Abstract: An electronic timepiece comprising a rate correction circuit for modifying the number of time base pulses received by the frequency divider during a predetermined period of time by a predetermined number of correction pulses. The rate correction circuit is arranged to divide said period of time into a given number of sub-periods and to distribute correction pulses substantially and equally over these sub-periods.

Abstract: A method and apparatus for correcting errors in an electronic digital timepiece that includes an oscillator which has a 2.sup.n frequency output, an n-stage frequency divider for reducing the oscillator output frequency to a time keeping frequency, and means for displaying the count of the time keeping frequency. The error E in the time of the timepiece for an arbitrary period of time T is determined. A computer computes a new adjustment value N+(2.sup.n-m +N)E/T where N is the preceding adjustment value and m is a nonnegative integer less than n. Then the 2.sup.n-m divisor of the first n-m stages of the n-stage frequency divider is adjusted in an amount equal to the new adjustment value. In first and second embodiments of the invention the timepiece is synchronized with a time standard at the beginning of the period of time T.

Abstract: An electronic watch comprising a stepping motor for driving a mechanism for displaying the time information, a quartz oscillator, a frequency divider with an adjustable division factor, a circuit for adjusting the division factor, a memory containing data relating to the magnitude of said adjustment and a logic circuit which, in response to an interrogation signal, produces a measuring signal which is supplied to the coil of the stepping motor and which comprises pulses whose distribution is representative of the division factor and the frequency of the oscillator and whose duration is sufficiently short so as not to cause the motor to turn and sufficiently long to cause a magnetic stray field of the coil of the motor which can be detected by an external apparatus for measuring the rate of the watch.

Abstract: A time correction circuit for an electronic timepiece comprising an oscillator circuit inputting a high frequency standard signal to a divider network, the divider network dividing down the standard signal in a plurality of stages. Correction data is periodically applied to a plurality of divider stages to advance or retard the timing rate when a selected stage achieves a preferred logic state. Occurrence of a logic state in a subsequent divider stage enables the circuits for the next periodic application of the correcting data. Coarse and fine adjustments can be made.

Abstract: A plurality of mechanical switches in an electronic timepiece having a timepiece circuit which performs frequency division and which has a plurality of terminals for controlling frequency division within the timepiece circuit according to external connections made to the plurality of terminals. The plurality of mechanical switches includes at least one rotary switch. The plurality of mechanical switches is connected to the timepiece circuit terminals for making a number of different external connections to the terminals which exceeds the sum of the different possible switch settings of the respective individual switches of the plurality of mechanical switches.

Abstract: An electronic timepiece comprising a fundamental frequency oscillator, a plurality of frequency divider stages, a timekeeping mechanism and display, includes circuitry for resetting and setting selective stages of the divider and thereby adding or subtracting timing pulses which are delivered to the timekeeping mechanism. A non-volatile memory stores data which terminates whether a divider stage is to be set or reset. Additionally, a plurality of circuit elements are selectively inserted to modify the circuit of the oscillator and to provide frequency adjustment. External contacts are provided for the inputting of data to memory and for measuring timing rate against an external standard.

Abstract: An electronic timepiece is equipped with a frequency division ratio adjustment circuit controlled by switch means, for producing a running rate correction signal that is aperiodically added in frequency to the output of a standard frequency oscillator, to correct the running rate of the timepiece, and is provided with externally controlled gate means for inhibiting this aperiodic frequency addition, so that the actual frequency of the standard frequency oscillator may be measured by means such as an external monitoring device which detects a display drive or modulation signal frequency through electrostatic or electromagnetic coupling to the timepiece display.

Abstract: An electronic timepiece adapted to perform time correction in response to a train of time correction pulses transmitted from another electronic timepiece. The electronic timepiece comprises a detecting means to detect the train of time correction pulses; a writing-in signal generator circuit to generate writing-in signals in synchronism with a synchronizing signal contained in the train of time correction pulses, and a writing-in gate circuit means to perform writing-in of the train of time correction pulses into a timekeeping circuit of the timepiece as new current time data in response to the writing-in signals.

Abstract: There is provided an electronic timepiece basic circuit comprising a pulse generating circuit for generating 1 Hz pulses, a first terminal group having a plurality of terminals including a terminal connected to the output terminal of the pulse generating circuit, a second terminal group having terminals to be connected to the terminals of the first terminal group, respectively, 10 scale counters coupled with the second terminal group, 6 scale counters connected to the 10 scale counters, a display unit, and a decoder which is coupled with the 10 scale counters and the 6 scale counters and decodes the contents of the 10 and 6 scale counters and delivers the decoded contents to the display unit. The first and second terminal groups are properly coupled to each other. The combination of the 10 scale counters and the 6 scale counters is properly modified so as to form a 12, 24, or 60 scale counter, as necessary.

Abstract: A system for correcting the accuracy of a reference signal in an electronic timepiece comprises an electronic timepiece including a reference signal frequency correction means for increasing or decreasing the reference signal frequency in a digital fashion with the use of a low frequency signal, and a quartz tester arrangement for measuring the accuracy of the reference signal frequency. The quartz tester arrangement indicates the displacement of the reference signal frequency from the standard signal frequency with the use of five lamps, each of which is selected to be enabled in accordance with the detected value of the displacement. The reference signal frequency correction means in the electronic timepiece includes five manually operable switches corresponding to said five lamps and functions to increase or decrease the reference signal frequency in a digital fashion in response to the closing of the switches corresponding to the enabled lamps.

Abstract: An electronic timepiece includes frequency-dividing circuit means for generating a first signal of at least 1 Hz from a signal of a predetermined frequency. This first signal is counted by a time counter. The frequency-dividing circuit and the time counter are reset in response to the closing of a first input switch. Circuitry is provided for releasing the frequency-dividing circuit from its reset condition to generate a second signal of at least 1 Hz as a quick advance signal for time setting in response to the closing of a second input switch.

Abstract: A frequency dividing circuit for dividing an input signal provided from a signal source at a selected dividing ratio includes first and second cascade-connected frequency dividers with signal controlling gates connected between the signal source and the first frequency divider, between the first and second frequency dividers, and between the signal source and the gates connected between the first and second frequency dividers. The signal controlling gates may be selectively controlled by a control switch to define a first signal path that includes both the first and second frequency dividers to effectively divide the input signal by both frequency dividers or a second signal path that includes only the second frequency divider to effectively divide the input signal by the second frequency divider only. The circuit includes input amplifiers which may be connected to various signal sources including signal sources that employ crystal oscillators, RC oscillators, and other types of oscillating circuits.