Abstract: A bi-directional signal coupler is incorporated into a transmission/reception communication system and is used for the transmission and reception of signals over a single transmission medium. The bi-directional signal coupler includes a primary nulling device for removing a signal to be transmitted through the bi-directional signal coupler from a signal to be received into the bi-directional signal coupler. The primary removing device provides an output signal representative of the signal to be received plus the signal to be transmitted wherein a level of the signal to be transmitted is removed to a first extent relative to a level of the signal to be received. At least one additional secondary device is provided for removing the signal to be transmitted from the signal to be received in a successive manner.

Abstract: A frequency estimator for estimating the frequency of a digital input signal (x(k)) includes a phase detection device (2) for determining the phase (&phgr;(k)) of the input signal (x(k)), a differentiator (3) for generating the phase difference (&phgr;diff1(k)) between adjacent samples of the phase (&phgr;(k), &phgr;(k-1)) and a filter (4) for averaging the phase difference (&phgr;diff(k)) and having a trapezoidal pulse response (hM(k)). The trapezoidal pulse response (hM(k)) is generated by superimposing a first triangular pulse response with a second triangular pulse response which is offset in time with respect to the first triangular pulse response.

Abstract: A Complementary Metal Oxide Semiconductor (CMOS) current mode differential link with precompensation is provided. The Complementary Metal Oxide Semiconductor (CMOS) bi-directional current mode differential link with precompensation includes a CMOS driver receiving a data input and having an output coupled to a transmission line. A CMOS replica driver receives the data input and provides a replica driver output substantially equal to the CMOS driver output. A CMOS receiver is coupled to both the transmission line and replica driver output. The CMOS receiver subtracts the replica driver output from a signal at the transmission line. The CMOS driver and the CMOS replica driver include a plurality of parallel current sources. Each of the current sources is arranged to send positive or negative current through a load responsive to an applied control signal. The use of the plurality of parallel current sources allows the CMOS driver to effectively implement precompensation.

Abstract: A measuring device for the interface of a transmission link with full-duplex transmission in two-wire common band operation includes a device for simulating the interface that allows the signal in the near-to-far direction on the transmission link to be separated from the return signal. To precisely perform jitter measurements on the interface of the transmission link during ongoing transmission using a conventional jitter measuring instrument, the measuring device has a differentiator followed by a comparator connected between a subtractor and the jitter measuring instrument.

Abstract: The present invention pertains to a system for transmitting data. The system comprises a network on which free topology transmission of data occurs. The system comprises a first node. The system comprises a second node. The system comprises a shared free topology modem connected to the network and the first and second nodes for transmitting signals from the first and second nodes. The present invention pertains to a method for transmitting data. The method comprises the steps of transmitting data from a first node on a balanced line two-wire differential network to a free topology modem. Next there is the step of transmitting the data from the first node to the free topology network on which free topology transmission of data occurs with the free topology modem. Then there is the step of transmitting data from a second node on the balanced line two-wire differential network to the free topology transceiver.

Abstract: The transmission of data via a differential bus by means of balanced signals is not only reliable, but also offers the advantage that in the event of various single faults, i.e. faults concerning only one of the two lines or faults where the two lines of the differential bus are short-circuited, data transmission is still possible, be it with a reduced reliability. To this end, both lines are connected to a number of comparators which have different threshold values so that the nature of a fault occurring can be determined and, in dependence thereon, the comparator output can be determined wherefrom the recovered data signal must be derived.

Abstract: A measuring device for the interface of a transmission path with full-duplex transmission in the common carrier duplex process. A highly integrated interface unit is connected to the interface via a hybrid set and a transmitter on one side. A line termination or a network termination is connected as the test object on the other side. In order to perform measurements on the test object with such a measuring device relatively easily and accurately, a device simulating the arrangement of a hybrid set, a transmitter and a line or network termination is provided and with its connected to the highly integrated interface unit via a high-resistance differential amplifier, and its output connected to an input of a subtractor. Another input of the subtractor is connected to the interface via an additional differential amplifier. The output of the subtractor is connected to a measurement system.

Abstract: A repeater for use in a control network includes isolating transformers at its root input/output and at a plurality of branch input/outputs. There is a line receiver and a line driver circuit associated with each of the isolating transformers. To determine the direction of transmission of signals through the repeater, there is a common mode voltage detector which detects a common mode voltage imposed on the wiring to the root side of the root transformer. A corresponding common mode voltage is imposed by the repeater on the branch side of each of the branch transformers. The repeater also includes a logic circuit for testing the validity of signals received from the branches and ensuring that only valid signals are passed to the root transformer.

Abstract: An analogue audio signal input to a transmission unit 1 is band limited into a frequency band lower than that of a main signal pass with a low-pass filter 21 and then converted into a digital value with a sampling clock lower than the main signal pass by an analogue/digital converter 22. All bits of the converted digital signal are inverted by an inverter 23. The digital signal input to a reception unit 3 via a transmission channel 100 is inverted by inverter 42 and is digital/analogue converted by digital/analogue converter 43 with the sampling clock lower than the main signal pass. The resultant signal is band limited into the low frequency band through a low-pass filter 44 and then output to a level comparator 45. A low-pass filter 46 band limits the signal for the main signal pass into the low frequency bang. The level comparator 45 compares the output level of the low-pass filter 44 with that of the low-pass filter 46.

Abstract: A transmitter/receiver interface (12) for use with a bi-directional transmission path (18) couples a transmitter (14) and a receiver (16) to the bi-directional transmission path (18). The transmitter/receiver interface (12) separates transmitted signals (20) and received signals (22) and routes them from the transmitter (14) and to the receiver (16) with negligible interference. The transmitter/receiver interface (12) incorporates coupling elements (44 and 50) that couple the transmitter to the transmission path and incorporates networks that couple the receiver to the transmission path. Impedances of the networks are derived based on the coupling elements and the transfer characteristics of the transmission path to provide consistent attenuation of the transmit signal over a large frequency range.

Abstract: A system for converting between parallel data and serial data is described. In the system (10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

Abstract: A full-duplex, differential, bi-directional communications link for simultaneously transmitting differential data between electronic devices is provided. Each transceiver coupled to the communications channel comprises a CMOS (Complementary Metal-Oxide Semiconductor) differential driver and receiver. The differential driver provides constant CMOS voltage sources for providing stable data signal transmission at reduced voltage levels. Voltage sources providing a data signal voltage different from the desired data signal voltage can be placed into a high impedance mode to allow the desired data signal voltage to be transmitted on the common line. The differential receiver includes self-biasing feedback circuitry to provide biasing voltages to the circuit while avoiding manufacturing difficulties associated with providing precise bias voltages. The complementary amplifier structure of the receiver provides an increased common mode noise tolerance.

Abstract: Circuitry 200 is provided for transmitting data between a first endpoint and a second endpoint and includes an information line 201 and a dummy line 205. Information transmission circuitry 202, 203, 204 is disposed at the first endpoint for transmitting information on information line 201, transmission circuitry 202, 203, 204 pulling information line 201 to a low voltage during transmission of information of a first logic state and charging information line 201 to a higher voltage during transmission of information of a second logic state. Charging circuitry 206, 207, 208 is disposed at the first endpoint for charging dummy line 205 to a reference voltage during transmission of information on information line 201, charging circuitry 206, 207, 208 charging dummy line 205 at a rate different from a rate at which transmission circuitry 202, 203, 204 charges information line 201 during transmission of information of the second logic state.

Abstract: A bidirectional, long-distance open collector link is constructed between a pair of spaced-apart open collector ports, with each of the ports being coupled to one input of a comparator. The other input of the comparator is responsive to a reference voltage and the comparator of the opposite port via an extended conductor. A first diode poled to pass current from the respective port is coupled between inputs of each comparator, and a second diode is coupled in the extended conductor to pass current to the opposite port. As such, when a first port goes LOW, a first comparator operatively associated with that port provides a LOW to the input of the second comparator, causing it to provide a HIGH output and also pulls the second port LOW. The HIGH from the second comparator is used to clamp the first comparator LOW as long as the port asserts a LOW.