Abstract: In a data communication circuit, data is multiplexed onto a communication link through multiple multiplexer stages and demultiplexed from the communication link through multiple demultiplexer stages in order that a clock signal applied to each multiplexing circuit need only be precisely distributed to a limited, high frequency portion of the circuit. Each circuit is clocked by a multiplying delayed locked loop bit clock generator. Where the number of parallel bits in the signal between the two stages is greater than two, the higher frequency stage coupled to the communication link is clocked by an N-phase overlapping clock. In the case of a multiplexer, the intermediate frequency signal is enabled in the higher frequency data multiplexer by concurrence of two clock phases.

Abstract: Transport packet multiplexing system and methodology that provides accurate bandwidth control, allowing bandwidth requirements to vary per multiplexed data stream while guaranteeing bandwidth availability. Accurate timing control is provided by implementing a real-time scheduling mechanism for adjusting the timing information based upon timing information obtained at the time of multiplexing to accurately represent environmental changes.

Abstract: In addition to a main monitor/control module, sub-monitor/control modules are provided, which monitor the operating conditions of transmission sections in real time through a CPU bus. The main monitor/control module collects monitor data from each sub-monitor/control module at a given timing through a LAN and processes the monitor data collected.

Abstract: A method and apparatus are provided to remove dataless TDM frames when transporting private line traffic over an ATM network. A number of TDM frames comprising a TDM private line circuit are received, and it is determined if a TDM frame contains data. The determination may be based on, for example, the detection of one or more frame delimiters, such as by comparing information in the TDM frame with a pre-determined frame delimiter pattern. Information from the TDM frame is placed into an ATM cell only when the TDM frame contains data. An indication that a TDM frame has not been placed into an ATM cell is conveyed in the AAL2 headers.

Abstract: Interleaving of data symbols comprises permuting rows and columns of a matrix of Nr rows and Nc columns, in which data symbols to be interleaved are represented row by row, in accordance with:

Abstract: A method and system are provided for operating a transmission system having connected nodes. Channels are assigned for carrying traffic along the connections according to a multiple protection classes. Traffic may then be propagated over the connections in accordance with the assigned protection classes.

Abstract: In digital video compression, the output bit-streams from respective encoding means, each of which has a quantization parameter being varied between coarser and finer values in accordance with the nature of the material being encoded, are multiplexed. The allocation of bit rate amongst the respective encoding means is effected by using a measure of the relative quantization levels of the respective encoding means to select the encoding means from which data is to be read.

Abstract: A system and method for voice transmission over high level network protocols. On the Internet and the World Wide Web, such high level protocols are HTTP/TCP. The restrictions imposed by firewalls and proxy servers are avoided by using HTTP level connections to transmit voice data. In addition, packet delivery guarantees are obtained by using TCP instead of UDP. Variable compression based on silence detection takes advantage of the natural silences and pauses in human speech, thus reducing the delays in transmission caused by using HTTP/TCP. The silence detection includes the ability to bookend the voice data sent with small portions of silence to insure that the voice sounds natural. Finally, the voice data is transmitted to each client computer independently from a common circular list of voice data, thus insuring that all clients will stay current with the most recent voice data. The combination of these features enables simple, seamless, and interactive Internet conferencing.

Abstract: A synthesizer for generating a desired chirp signal has M parallel channels, where M is an integer greater than 1, each channel including a chirp waveform synthesizer generating at an output a portion of a digital representation of the desired chirp signal; and a multiplexer for multiplexing the M outputs to create a digital representation of the desired chirp signal. Preferably, each channel receives input information that is a function of information representing the desired chirp signal.

Abstract: A multiplexing control system has a common process input/output unit for distributing process signals from sensors for measuring the same state variable of a process to digital controllers. One process input/output unit for inputting/outputting a process signal between the multiplexing control system and plant is provided for each process signal. The process input/output unit for the process signal of high importance is triplexed. A process controller having an operating function is provided to each of the triplexed process input/output units. A process input/output unit for the process signal of intermediate importance is diplexed. A process input/output unit for the process signal of low importance is monoplexed. The process signals of the diplexed process input/output units and the monoplexed process input/output unit are controlled by a controller having a master right among the process controllers.

Abstract: A protocol independent multiplexer is described that allows for multiple different protocols that operate at different bit rates to be combined and output in a format that may have yet another bit rate. The multiplexer includes a series of inputting devices that are each coupled to a respective buffering device, a mapping device coupled to each of the buffering devices, and an outputting device coupled to the mapping device. Each of the inputting devices receive an input optical signal and forwards recovered data information to the corresponding buffering device. The buffering devices store the data information and output to the mapping device, the outputting being controlled by the mapping device to ensure that the buffering devices remain approximately half full. The mapping device formats the data information into individual data units and outputs the data units to the outputting device which subsequently multiplexes the data units.

Abstract: Method and systems for improving utilization of high-speed time division multiplexed communications links at a signal transfer point are disclosed. A multi-port link interface module terminates two or more high-speed TDM links and generates internal data. Data received on one high-speed communications link is combined with the internal data used to fill outbound timeslots in an outgoing high-speed link. The data may include signaling data, bearer data, or signaling and bearer data.

Abstract: The present invention involves hierarchical storage controllers which enable a scalable storage system. The scalable storage system is capable of causing a very large amount of discrete disk units to appear as a single drive. The scalable storage system is organized into a hierarchical structure by providing a series of disk arrays in parallel with a controller via Fiber Channel connections to form a “virtual disk.” The next level in the hierarchical structure is created by connecting a number of virtual disks and a higher level controller in parallel via higher bandwidth connections. This next assemblage of devices is configured to appear as a single drive. Also, the scalable storage system disposes increasingly sized RAM caches to increase system performance. Moreover, wave division multiplexing (WDM) may be utilized to communicate with a file server via a highest level controller.

Abstract: In a communication network for transferring signals, e.g. according to the SONET or SDH standards, interconnecting node devices are provided consisting of parallel processing modules (9-T, 9-R). A plurality of processing modules with first and second interfaces rearrange/insert/extract tributary signals and configurable multiplexing/de-multiplexing components enable each processing module to access any portion of an arbitrarily preselected tributary signal. In a SONET/SDH system, signals between SONET/SDH frames are rearranged on incoming (20) and outgoing (26) main lines=Digital Cross-Connect, or tributary signals are transferred between frames and local lines (16-i-T, 16-i-R)=Add/Drop Function.

Abstract: A method and associated detecting circuitss for detecting and correcting a connection polarity of a network transmission line include two network clients and a network transmission line. One network client utilizes a detecting circuit to count and compare the number of signal pulses at the receiving and transmitting ports to determine if the connection polarity is correct or inverted. The detecting circuit can switch the connection polarity if required to correct it.

Abstract: A multiplexer cell (1) for converting an input signal (D0, D1) with a data input rate (fD) into an output signal (E) with a data output rate (fE), which in particular is twice the size of the data input rate, is proposed.

Abstract: A novel and improved method and apparatus for generating a reduced peak amplitude high data rate channel comprised of a set of lower rate channels is described. The set of lower rate channels are phase rotated before being summed and transmitted. The amount of phase rotation is dependent on the number of channels used to form the higher rate channel. In an embodiment where two lower rate channels are used, the in-phase and quadrature-phase components of the two channels are complex multiplied before upconversion with an in-phase and quadrature-phase sinusoids. For a high rate channel comprised of more than two lower rate channels, the in-phase and quadrature-phase component of each channel is upconverted with a set of sinusoids that are phase offset from one another.

Abstract: A multiplexing method for multimedia communication is provided, which is compatible with the H.223 protocol by changing a header of a multiplex protocol data unit (MUX-PDU). The multiplexing method includes the steps of encoding media data, and multiplexing the media data encoded in the step (a) in units of a predetermined frame, and inserting a second flag having a predetermined length with an auto-correlation into the frame after a first flag representing the opening and closing of the frame. Therefore, the probability of detecting the MUX-PDU by a receiver is increased by adding a flag having a high auto-correlation to the H.223 MUX-PDU frame, thereby increasing error-resiliency.

Abstract: A data transmission apparatus and a camera system for multiplexing serial data into horizontal blanking portions of video data for transmission between a CHU (1) and a CCU (2). On the transmitting side, resampled data is obtained by sampling the serial data using a clock signal of a frequency higher than that of the transmission rate of the serial data. A predetermined number of resampled data items are selected as multiplexing data from the resampled data obtained in each of the horizontal periods of the video data. The multiplexing data is multiplexed into the horizontal blanking portions of the video data for transmission. On the transmitting side, the multiplexing data is separated from the received video data. The separated multiplexing data is decoded so as to extract successively definite data constituting the initial serial data.

Abstract: Apparatus and methods for multiplexing data received from a plurality of sources to a communication channel. Each of the sources is assigned to one of at least two scheduling layers based in part upon one or more bit rate characteristics of the sources.

Abstract: In an integrated circuit, a data traffic router includes a number of multiplexors and a controller, coupled to each other, and to subsystems of the IC. The subsystems selectively output to each other. The data traffic router selectively configures itself to provide paths for the outputs to reach their destinations, to facilitate concurrent communications between selected combinations of the subsystems.

Abstract: An apparatus and a method of fast rotation. A pipeline comprising a plurality of multiplexes a plurality of shifters to perform last rotation of data selected by the multiplexes, and a plurality of adders/subtracters is provided. A plurality sets of data is input to be filtered and selected by the multiplexes. Fast rotation is performed to the data selected by the multiplexes. A final computation is performed a set of resultant data is output through the adder/subtractors.

Abstract: An on-chip RAM FIFO (first-in-first-out) buffer for storing SPE overhead bytes wherein each entry of the RAM FIFO stores (1) a byte of the SPE overhead; (2) an indication of which byte of the SPE overhead is currently stored in that entry; and (3) an indication of which STS signal that byte was taken from.

Abstract: This invention relates to digital subscriber line arrangements. The invention divides the functionality of an xDSL-DSLAM device into two separate parts: a subunit and upper unit. The subunit contains xDSL line cards for copper pair lines to downstream and a multiplexer for multiplexing the transmission channels of the pair lines to an upstream transmission line. The upper unit contains a CPU, which handles, for example, management and security tasks, a router for routing messages between the channels of a backbone (trunk) network and subscriber lines, and an internal bus for connecting the equipment of the upper unit.

Abstract: A system and method for providing digital subscriber line service that uses a cross-connect switch to switch in new connections and switch out obsolete connections.

Abstract: A signal decoding method comprises the steps of: receiving multiplexed signals in which coded signals of plural pieces of information to be recorded or transmitted have been multiplexed; obtaining priority information of respective information from the multiplexed signals; and decoding coded signals of respective information included in the multiplexed signals in the order in accordance with the obtained priority information.

Abstract: A glitchless delay line using a Gray code multiplexer is provided. The glitchless delay line combines a multi-tap delay circuit with the Gray code multiplexer. Specifically, the multi-tap delay circuit provides a plurality-of sequentially ordered delayed output signals on a plurality of sequentially ordered output terminals. The Gray code multiplexer has a plurality of input terminals coupled to the sequentially ordered delayed output terminals. The Gray code multiplexer is controlled by driving a Gray code value onto the control terminals of the Gray code multiplexer to select a specific delayed output terminal of the multi-tap delay circuit. The delay provided by the delay line is increased by incrementing the Gray code value on the control terminals of the Gray code multiplexer and decreased by decrementing the Gray code value on the control terminals. Race conditions on the control lines are eliminated when incrementing or decrementing the Gray code value by one.

Abstract: To simplify the structure of the demodulator and reduce the hardware scale in a code division multiple accessing communication apparatus. A plurality of base band received signals are multiplexed in a time division manner, so that one matched filter executes path searching or a time division multiplexing processing is executed for demodulation in a despreader. Or path searching and demodulation for a plurality of codes are executed with time division multiplexing of outputs from a plurality of code generators.

Abstract: A judgment as to whether an action to transfer digital data of a content through a network has been initiated by a party on a transmission or reception side is performed. If the action has been initiated by the party on the transmission side, a judgment as to whether a sign appended as a prefix to the digital data of the content is positive or negative is performed. If the sign is positive, the party on the transmission side settles accounting for the digital data of the content. If the sign is negative, the reception side is requested to settle accounting for the digital data of the content. If the action has been initiated by the party on the reception side, a judgment as to whether the sign appended as a prefix to the digital data of the content is positive or negative. If the sign is positive, the party on the reception side is requested to settle accounting for the digital data of the content.

Abstract: A packet multiplexing apparatus includes at least one high transmission rate data memory for accumulating high transmission rate data, and at least one low transmission rate data memory for accumulating low transmission rate data. A control section determines whether an accumulation quantity of the high transmission rate data reaches a first predetermined value, and issues a transmission instruction when it is determined that the accumulation quantity of the high transmission rate data reaches the first predetermined value. A multiplexing unit multiplexes the high transmission rate data from the high transmission rate data memory and the low transmission rate data from the low transmission rate data memory in response to the transmission instruction to form a packet.

Abstract: An integrated circuit structure and method is capable of automatically tuning the duty cycle of a generated clock signal to any desired value. Tuning of the duty cycle depends upon the precise layout specifications of multiple delay elements of one or more multiplexing circuits of the integrated circuit device. Connecting one or more multiplexing circuits in a serial fashion allows a base frequency to be multiplied in order to produce a generated clock frequency of a desired frequency. Control of select lines to the multiplexing circuits allows the delay path through the one or more multiplexing circuits to be adjusted, thereby automatically adjusting the duty cycle of the generated clock signal.

Abstract: A multiplexing system is provided for controlling and monitoring all the electrical functions of a vehicle. The system includes a switch control unit which receives inputs from various sources and converts the inputs into digital signals which are decoded in a microprocessor. The decoded signals are then sent to a power distribution unit, which sends out, shuts off, increases or decreases the power to different parts of the vehicle as needed.

Abstract: In the preferred embodiment, the outputs of a plurality of analog signal generators are connected to a single wire (the analog bus). Each analog signal generator is addressable by a unique code provided to its respective address input terminals. A host controller selectively addresses only one of the analog signal generators such that an output of only one of the analog signal generators is applied to the analog bus at a time. In this manner, a single wire may be used to transmit a plurality of analog signals to a receiver. In one embodiment, the receiver is a MUX having an output connected to an ADC.

Abstract: A variable resistor/bar graph driver multiplexer uses a resistor network for obtaining a variable resistance and a constant current source. The resistor network contains a plurality of switches such that each switch corresponds with a particular resistor when depressed, thereby providing one of a plurality of output voltages. The output voltage is received by a receiver containing a bar graph driver circuit and a plurality of PNP drivers and relay coils corresponding to the switches at the transmitter. The relay coils will turn on depending on the switch pushed at the transmitter. This multiplexer circuit allows a large amount of switch position information and multiple to be transmitted over only two signal lines rather than the large number of lines used in conventional multiplexers. The multiplexer circuit can also be implemented using analog-to-digital converters and digital-to-analog converters at the receiver.

Abstract: The present invention provides a media-independent interface (MII) on a highly integrated network component by implementing the MII interface with a lower pin count, while reducing the timing budget. In another embodiment, the present invention functions to interface MII compatible devices while reducing pin count and the timing budget.

Abstract: A method of controlling multiplexers and cross-connects on a telecommunications network to interconnect DS0 and/or wideband circuits is developed for a test range where a large number of circuits, perhaps several hundred. have to be reassigned every fifteen minutes. However, the method is sufficiently general to work for a variety of telecommunications networks. The method of the invention controls the OC-3 multiplexers and the cross-connects to connect a DS0 or DS1 from any feeder site on the range to a DS0 or DS1 at any other feeder site. In addition to the interconnection of DS0 and DS1 signals, the method includes the control needed to set up conference circuits, where many full duplex circuits (such as two-way voice circuits) are connected together; other one-to-many connections, and simplex circuits where a connection is one-way.

Abstract: A process for distributing an aggregate rate and total transmitting power of a data stream over a plurality of channels in which the sub-rate (R.sub.i), capable of being transmitted over one channel, is calculated for each selected channel in accordance with the equation ##EQU1## R.sub.i being the sub-rate in the i-th channel, N.sub.i the average noise power first determined in the i-th channel, and D' being the number of actually used channels out of the channel group.

Abstract: In a multimedia information processing system, a relay station comprises: transmission decoding section for reproducing a fixed packets stream from received transmission signal from a transmitter; signal change processing means for executing changing process for the fixed packets stream; and transmission coding section for producing a transmission signal corresponding to a characteristic of a transmission line from the fixed packets stream. The construction for exchanging signals between different transmission means is simplified. Thus, it is achieved to exchange contents of media between different transmission means by a simple construction.

Abstract: System for establishing a TDM information protocol over a communications path includes a transmit section and a receive section. In general, the transmit element receives a succession of data elements from each of a plurality of independent channels and combines the data elements to form a single TDM sequence of data elements. The receive element receives a TDM sequence of data elements and separates the sequence into its constituent components to form a plurality of channels, each forming a succession of data elements. In one form of the invention, data elements transmitted via the TDM communications path are limited to a single time slot in the TDM protocol.

Abstract: Two T1 signals are mapped onto a subscriber bus (26) in a subscriber loop equipment (10) for transport between a bank control unit (20) and channel units (22), for example. The data channels and the signaling and control channels of the first T1 signal are mapped onto a first data stream, and the data channels and the signaling and control channels of the second T1 signal are mapped onto a second data stream. The data streams are bit-interleaved for transport on the subscriber bus (26).

Abstract: A tone generating circuit comprises a counter circuit having a clock input for receiving a clock signal and a plurality of outputs which generate sequential binary values in response to transitioning of the clock signal; a multiplexer having several inputs, a number of select lines connected to the counter circuit outputs, and at least one output; and a resistor divider network connected to the multiplexer inputs. The multiplexer select lines select one of the multiplexer inputs in accordance with the binary value received from the counter circuit. The multiplexer inputs are connected to different taps on the resistor divider network. The counter selects multiplexer inputs on the falling edge of the clock signal, while the output signal level transitions before the rising edge of the clock signal.

Abstract: A digital signal transmission system operates in a mode for transmitting multiplexed signals as a serial digital signal and in a mode for transmitting only a predetermined signal. A transmitter of the system includes a first control circuit which, in a particular signal transmission mode, places only a particular signal processing circuit block for transmitting a particular signal in an operative state and places in an inoperative state a multiplexer circuit block for multiplexing the predetermined signal with at least one other signal. In a multiplexed transmission mode, the first control circuit places in an operative state only the multiplexer circuit block and places in an inoperative state the particular signal processing circuit block.

Abstract: A multiplexer, preferably on an integrated circuit chip, receives a plurality of buses each having a plurality of lines responsive to binary indications and passes the binary indications in the lines of a particular one of the buses. The multiplexer includes a plurality of circuit blocks each responsive to the binary indications in the lines of an individual one of the buses. Each block has a plurality of recursive circuits each having first and second stages. The second stages of the recursive circuits in an individual one of the circuit blocks receive an individual one of a plurality of control indications at a first side of the block to activate the first stages in such recursive circuits. The first stage in each recursive circuit in each individual circuit block receives at a second side of the block the binary indications in an individual line in an individual one of the buses to obtain a signal from such first stage in accordance with such binary indication upon the activation of such first stage.

Abstract: A hierarchial bus structure having at least three dimensions provides improved interconnect flexibility between nodes located on one or more levels of the structure. Nodes are defined on at least first and second "horizontal" (or "H") rings, the rings being coupled by at least one "vertical" (or "V") ring. Each node is identified in terms of its (H,V) coordinates in the hierarchial interconnect structure, and an M-dimensional structure will provide an M-way multiplex unit at each node. For an M=3, e.g., three-dimensional structure, each multiplex unit has three-inputs, a Localout, a Vin, and an Hin input, and couples one of these inputs to an output port in response to a Local select arbitration signal. The output signal is coupled to Hout and Vout, and to Localin. Nodes on the same horizontal level will drive their Hin signal to Vout and Hout, whereas all other nodes receive the Vin signal.

Abstract: A demand assign multiplexer has a multiplexing portion multiplexing a signal which can be transmitted in a statistical multiplexing. Also, the multiplexer has an output element for outputting a channel assignment demand depending upon a signal from a system which requires guarantee of transparent data transfer which guarantees content of transfer in a normal state of a transmission path. A control portion controls to perform demand assign process with channel assignment depending upon the output of the statistical multiplexing processing portion; and the signals which require guaranteed transparent data transfers.

Abstract: A postage meter mailing machine includes a multiplex serial data communication system for providing communication between the postage meter mailing machine and a plurality of internal and external devices. Each device can generate and receive serial messages at a respective device communication port. The mailing machine includes a controller, a UART controller module responsive to control signals from the controller, a message buffer in bus communication with the UART controller and a communication multiplexer. The communication multiplexer provides single channel communication with the UART controller module and selectively with one of a number of external communication ports. The communication multiplexer is responsive to control signals from the controller for establishing a communication path between the UART controller module and the selected one of communication ports over the single channel communication and sequentially alternating the communication path between each of the communication ports.

Abstract: A facility is provided in a telecommunications network which causes Digital Speech Interpolation (DSI) apparatus to transmit noise signals toward a destination if the level of the noise signals at least equals a predetermined threshold value, in which the predetermined threshold value is selected, in accord with an aspect of the invention, as a function of a type of telephone service subscribed to by the telephone station set involved in the associated telephone call.