Multiplexing Combined With Demultiplexing Patents (Class 370/535)
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Patent number: 12210870Abstract: An application processor receives first and safety state information from first and second microcontrollers, and respective first and second sets of bytes forming a first identifier of the first microcontroller and a second identifier of the second microcontroller. The processor concatenates a safety message including the first and second safety state information, the safety message including the first set of bytes and the second set of bytes. The processor transmits the safety message to a second application processor of a safety controller, which separates, the first set of bytes and the second set of bytes, compares at least one of the first set of bytes and the second set of bytes to a data structure of known microcontroller identifiers, and verifies the safety state information based on identifying a match.Type: GrantFiled: May 27, 2021Date of Patent: January 28, 2025Assignee: Fort Robotics, Inc.Inventor: Kerfegar Khurshed Katrak
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Patent number: 12166545Abstract: A transmission method simultaneously transmitting a first modulated signal and a second modulated signal at a common frequency performs precoding on both signals using a fixed precoding matrix and regularly changes the phase of at least one of the signals, thereby improving received data signal quality for a reception device.Type: GrantFiled: September 22, 2023Date of Patent: December 10, 2024Assignee: SUN PATENT TRUSTInventors: Yutaka Murakami, Tomohiro Kimura, Mikihiro Ouchi
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Patent number: 12147265Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, a computing system includes transmitters sending data signals to receivers that support using a prefix to provide clock recovery and alignment of the input bit stream that arrives at the receivers. Based on when a decoder of a receiver receives the prefixes, the decoder determines which clock cycles to skip writing data into a buffer of data processing circuitry. Therefore, the decoder prevents overflow of this buffer when the rate of insertion is greater than the rate of removal for this buffer. In contrast, the transmitter continues to send data during each clock cycle, and accordingly, avoids reducing the effective bandwidth on transmission lines in the presence of clock domain differences between transmitter and receiver.Type: GrantFiled: November 21, 2022Date of Patent: November 19, 2024Assignee: ATI Technologies ULCInventors: Yanfeng Wang, Shaofeng An
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Patent number: 11956008Abstract: One example may include transmitting data between a client device and a server over a first channel, sending test data on a second channel to identify a transmission rate of the second channel, comparing the transmission rate to a transmission rate threshold, and determining whether to perform bonding of the first channel with the second channel based on the transmission rate of the second channel being greater or less than the transmission rate threshold.Type: GrantFiled: February 14, 2023Date of Patent: April 9, 2024Assignee: CONNECTIFY, INC.Inventors: Kevin Cunningham, Harry Volek, Brian Prodoehl, Alexander Gizis
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Patent number: 11954584Abstract: A neural core, a neural processing device including same and a method for lauding data of a neural processing device are provided. The neural core comprises a processing unit configured to perform operations, an L0 memory configured to store input data and an LSU configured to perform a load task and a store task of data between the processing unit and the L0 memory, wherein the LSU comprises a local memory load unit configured to transmit the input data in the L0 memory to the processing unit, and the local memory load unit comprises a target decision module configured to identify and retrieve the input data in the L0 memory, a transformation logic configured to transform the input data and thereby generate transformed data and an output FIFO configured to receive the transformed data and transmit the transformed data to the processing unit in the received order.Type: GrantFiled: May 23, 2023Date of Patent: April 9, 2024Assignee: Rebellions Inc.Inventors: Jinseok Kim, Kyeongryeol Bong, Jinwook Oh, Yoonho Boo
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Patent number: 11902721Abstract: A communication device is configured to receive data at a first data rate and to transmit the data at a second data rate that is greater than the first data rate. The communication device includes a plurality of communication pipelines and a multiplexer. Each communication pipeline is configured to receive a respective input data stream including first data blocks having a first format compatible for transmission at the first data rate, convert the first data blocks into second data blocks having a second format compatible for transmission at the second data rate, and provide an indication when one of the input data streams that is expected to be received is not received. The multiplexer is configured to receive the second data blocks from the communication pipelines and to generate an output data stream for transmission at the second data rate when one of the input data streams is not received.Type: GrantFiled: March 2, 2022Date of Patent: February 13, 2024Assignee: MARVELL ASIA PTE LTDInventors: Whay Sing Lee, Arash Farhoodfar, Volodymyr Shvydun, Michael Duckering
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Patent number: 11871078Abstract: To reduce a processing load at a reception side in a case where a plurality kinds of audio data items are transmitted. A container in a predetermined format having a predetermined number of audio streams including coded data items of a plurality of groups is transmitted. For example, the coded data items of the plurality of groups include either or both of channel coded data items and object coded data items. Attribute information indicating respective attributes of the coded data items of the plurality of groups is inserted into a layer of the container and/or a layer of an audio stream. For example, stream correspondence relation information indicating which audio stream includes each of the coded data items of the plurality of groups is further inserted.Type: GrantFiled: November 9, 2020Date of Patent: January 9, 2024Assignee: SONY CORPORATIONInventor: Ikuo Tsukagoshi
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Patent number: 11854636Abstract: A data sampling circuit includes a frequency dividing circuit, a sampling circuit and a selection circuit. The frequency dividing circuit is configured to receive a first data sampling signal, and perform frequency dividing processing on the first data sampling signal to obtain multiple second data sampling signals associated with respective phases; the sampling circuit is configured to receive the multiple second data sampling signals and a first data signal, and sample the first data signal according to the multiple second data sampling signals to obtain multiple second data signals associated with respective phases; and the selection circuit is configured to receive preamble information and mode register set (MRS) information, and select among the multiple second data sampling signals and the plurality of second data signals according to the preamble information and the MRS information to obtain a target data sampling signal and a target data signal respectively.Type: GrantFiled: April 29, 2022Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Zhiqiang Zhang
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Patent number: 11809345Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.Type: GrantFiled: February 22, 2022Date of Patent: November 7, 2023Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, John Eric Linstadt, Catherine Chen
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Patent number: 11805042Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.Type: GrantFiled: September 20, 2022Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: Yoni Landau, Janardhan Satyanarayana, Assaf Benhamou, Mark Bordogna
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Patent number: 11804858Abstract: A system, method, and device is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network that includes a plurality of layers of multiplexers. Many transformations are possible with such a network which may include separate control of each multiplexer.Type: GrantFiled: July 19, 2021Date of Patent: October 31, 2023Assignee: Texas Instruments IncorporatedInventors: Dheera Balasubramanian, Joseph Zbiciak, Duc Quang Bui, Timothy David Anderson
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Patent number: 11762059Abstract: The invention relates to a method for simplifying a sampled signal digital filter, the method including at least one step for: in order to obtain a first intermediate filter, gathering channels including discrete nonstationary operations relating to the same signal, the first channels including the nonstationary operations relating to a first signal and the second channels including the nonstationary operations relating to a second signal, in order to obtain a second intermediate filter, on each of the first channels and second channels, commutative stationary operations with the nonstationary operations, in order to eliminate the redundant nonstationary operations, and building the filter corresponding to the last obtained intermediate filter.Type: GrantFiled: October 13, 2020Date of Patent: September 19, 2023Assignee: THALESInventor: Jean-Michel Hode
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Patent number: 11751284Abstract: Apparatus, methods, and computer-readable media for cooperative relay in sidelink networks are disclosed herein. An example method for wireless communication at a first user equipment (UE) includes receiving, from a second UE, a groupcast signal comprising a resource allocation assigned to a plurality of sidelink UEs including the first UE. The example method also includes communicating, with a remote apparatus on a first resource included in the resource allocation, a first relay signal comprising at least a portion of the groupcast signal, in which the first relay signal corresponds to at least a portion of a second relay signal communicated with the remote apparatus on a second resource included in the resource allocation by at least one other sidelink UE of the plurality of sidelink UEs.Type: GrantFiled: June 25, 2021Date of Patent: September 5, 2023Assignee: QUALCOMM IncorporatedInventors: Yi Huang, Seyedkianoush Hosseini, Wei Yang, Tugcan Aktas, Hwan Joon Kwon, Krishna Kiran Mukkavilli, Tingfang Ji
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Patent number: 11722958Abstract: A Wi-Fi chip is configured to operate in a power saving Wi-Fi mode in which the Wi-Fi chip repeatedly checks, at a first time interval, periodic DTIM beacons transmitted at a second time interval by a wireless access point of a Wi-Fi network, wherein the first time interval is longer than the second time interval. Upon receiving a standby message, the Wi-Fi chip, during a predefined time duration, operates in a standby mode in which the Wi-Fi chip checks at a third time interval periodic DTIM beacons transmitted by the wireless access point, wherein the third time interval is shorter than the first time interval.Type: GrantFiled: May 5, 2021Date of Patent: August 8, 2023Assignee: Google LLCInventors: Howard M. Harte, Haidong Wang, Feng Wang
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Patent number: 11722341Abstract: Methods and systems are described for asynchronously measuring an equalized information signal to obtain amplitude information, modifying frequency dependent parameters of a continuous-time linear equalization (CTLE) component of the signal path, determining a correlation between CTLE parameters and signal amplitude, and adjusting, responsive to the correlation, a continuous-time linear equalization (CTLE) code of a CTLE to adjust equalization of the equalized information signal.Type: GrantFiled: June 28, 2022Date of Patent: August 8, 2023Assignee: KANDOU LABS SAInventor: Ali Hormati
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Patent number: 11700002Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.Type: GrantFiled: December 20, 2021Date of Patent: July 11, 2023Assignee: Intel CorporationInventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
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Patent number: 11611791Abstract: A method to transfer a video stream from a host device comprising a controller configured for bulk transfers to a descrambling device, comprises: forming a chain out transfer comprising a chain out header linked with multiple chain out descriptors, the first chain out descriptor pointing to an out description packet containing at least one producer ID, the second and subsequent chain out descriptor pointing to chunks from the video stream, the last chain out descriptor being configured to generate an interrupt; forming a chain in transfer comprising a chain in header linked with a plurality of chain in descriptors, each chain in descriptor pointing to a descrambled chunk; requesting the controller to process the chain; receiving the description packet by the descrambling device and using key data associated with the chunks to descramble them; receiving by the controller the descrambled chunks and triggering an interrupt on the last chunk.Type: GrantFiled: January 15, 2021Date of Patent: March 21, 2023Assignee: NAGRAVISION S.A.Inventor: Fabien Gremaud
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Patent number: 11606167Abstract: A method includes: sending, by a first device, a first bit stream to a second device, where the first bit stream is sent over N logical lanes of a physical layer of the first device; sending, by the first device, a first trigger marker group to the second device, where the first trigger marker group is used to indicate that the sending of the first bit stream ends; and sending, by the first device, a second bit stream to the second device in response to the sending of the first trigger marker group, where the second bit stream is sent over P logical lanes of the physical layer of the first device, and both N and P are positive integers.Type: GrantFiled: December 3, 2021Date of Patent: March 14, 2023Assignee: Huawei Technologies Co., Ltd.Inventors: Desheng Sun, Yongzhi Liu, Li Ding, Zhigang Zhu
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Patent number: 11570514Abstract: An electronic device includes a display, a communication interface, a memory storing one or more instructions, and a processor. The processor, by executing the one or more instructions, is configured to, receive a user input for processing a second content while displaying a first content image on the display by processing a first content, identify whether a resource is available for processing the first content and the second content in the electronic device, based on the resource for processing the first content and the second content being unavailable in the electronic device, identify a peer device which has available resource to process the second content, transmit a request for processing the second content to the peer device, receive, through streaming, result second content which results from processing the second content by the peer device, from the peer device, and display, in addition to the first content image, a second content image corresponding to the result second content, on the display.Type: GrantFiled: December 23, 2020Date of Patent: January 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jongin Lee, Kilsoo Choi, Sehyun Kim, Kwansik Yang, Jaesoon Lee, Dahee Jeong
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Patent number: 11558289Abstract: The disclosed systems and methods provide hyperscalar packet processing. A method includes receiving a plurality of network packets from a plurality of data paths. The method also includes arbitrating, based at least in part on an arbitration policy, the plurality of network packets to a plurality of packet processing blocks comprising one or more full processing blocks and one or more limited processing blocks. The method also includes processing, in parallel, the plurality of network packets via the plurality of packet processing blocks, wherein each of the one or more full processing blocks processes a first quantity of network packets during a clock cycle, and wherein each of the one or more limited processing blocks processes a second quantity of network packets during the clock cycle that is greater than the first quantity of network packets. The method also includes sending the processed network packets through data buses.Type: GrantFiled: October 22, 2021Date of Patent: January 17, 2023Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventor: Sachin Prabhakarrao Kadu
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Patent number: 11546241Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.Type: GrantFiled: October 18, 2021Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Yoni Landau, Janardhan H. Satyanarayana, Assaf Benhamou, Mark A. Bordogna
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Patent number: 11514492Abstract: In general, techniques are disclosed to facilitate communicating within computer networks. For example, a layer three (L3) router including a service card and an interface card may be configured to perform the techniques. The interface card receives a query from a network that sources communications in accordance with a plurality of models. The query may specify a customer device and one of the sourced communications, and request that the service card select one of the models for the specified sourced communication and the specified customer device. The service card further stores data defining a profile for the one of the customer devices. The service card may also, in response to the query, analyze the profile data for the specified customer device to determine the selected one of the models for the specified sourced communication with respect to the specified customer device.Type: GrantFiled: June 25, 2020Date of Patent: November 29, 2022Assignee: Juniper Networks, Inc.Inventors: Ramesh Panwar, David Weinberg
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Patent number: 11498673Abstract: Embodiments are directed to a rotor system for an aircraft comprising a gearbox configured to receive torque from a drive train, a mast having a first end and a second end, wherein the first end is attached to the gearbox and the mast configured to rotate in response to the torque from the drive train, a rotor hub attached to the second end of the mast, a first light transceiver mounted adjacent to the first end of the mast, wherein the first light transceiver is does not rotate relative to the mast, and a second light transceiver mounted adjacent to the second end of the mast, wherein the second light transceiver rotates with the mast.Type: GrantFiled: September 26, 2019Date of Patent: November 15, 2022Assignee: Textron Innovations Inc.Inventors: Michael Raymond Hull, Daniel Duane Donley
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Patent number: 11451600Abstract: In one embodiment, an apparatus includes n electrical communication channels, m optical communication media interfaces, and a plurality of muxes. The plurality of muxes are configured to receive an information stream. The information stream is carried over the n electrical communication channels and the m optical communication media interfaces. The plurality of muxes are further configured to transform the information stream from v virtual lanes. Each virtual lane includes a plurality of data blocks from the information stream and an alignment block, wherein v is a positive integer multiple of the least common multiple of m and n, v is greater than n, and n is equal to m.Type: GrantFiled: July 23, 2020Date of Patent: September 20, 2022Assignee: CISCO TECHNOLOGY, INC.Inventors: Mark A. Gustlin, Oded Trainin, Luca Della Chiesa
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Patent number: 11405162Abstract: A user equipment (UE) transmits uplink control information (UCI) and a base station receives UCI when the UE is configured to have a number of cells configured for operation with carrier aggregation (CA). The base station configures the UE with a code rate and the UE determines a maximum UCI payload to transmit in a subframe that results in a transmission code rate that is no larger than the configured code rate. For transmission of aperiodic channel state information (A-CSI), a number of triggering states depends on the number of cells.Type: GrantFiled: May 22, 2020Date of Patent: August 2, 2022Assignee: Samsung Electronics Co., Ltd.Inventor: Aris Papasakellariou
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Patent number: 11342918Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.Type: GrantFiled: September 25, 2020Date of Patent: May 24, 2022Assignee: Intel CorporationInventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
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Patent number: 11343061Abstract: An Ethernet transceiver includes physical-layer (PHY) circuitry and a signal-loss detector. The PHY circuitry is configured to receive a signal from a peer transceiver, to process the received signal in a series of digital PHY-level processing operations, and to output the processed signal for Medium Access Control (MAC) processing. The signal-loss detector is configured to receive, from the PHY circuitry, a digital version of the received signal, and to detect a signal-loss event based on an amplitude of the digital version of the received signal.Type: GrantFiled: December 4, 2019Date of Patent: May 24, 2022Assignee: MARVELL ASIA PTE LTDInventor: Xing Wu
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Patent number: 11271568Abstract: A frequency divider circuit includes: a first latch circuit that including: a pair of input transistors each having a gate thereof configured to connect to a signal line to which a first voltage is supplied; and a pair of output nodes, and configured to receive a single-phase clock signal; and a second latch circuit of SR-type, the second latch circuit having a set input thereof and a reset input thereof configured to connect to the pair of output nodes of the first latch circuit, and configured to output differential clock signals of which frequency is half a frequency of the single-phase clock signal. The first latch circuit is configured to perform amplification and reset operations alternately repeatedly in response to the single-phase clock signal.Type: GrantFiled: December 10, 2020Date of Patent: March 8, 2022Assignee: SOCIONEXT INC.Inventor: Hideki Kano
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Patent number: 11272270Abstract: The present invention is direct to data communication. In a specific embodiment, multiple independent data streams, which are at a first data rate, are transcoded by separate communication pipelines into data blocks. The data blocks, associated with these separate and independent data streams, are multiplexed with alignment markers to generate an output data stream. The output data stream is transmitted at a second data rate, which is higher than the first data rate.Type: GrantFiled: September 3, 2020Date of Patent: March 8, 2022Assignee: MARVELL ASIA PTE LTD.Inventors: Whay Sing Lee, Arash Farhoodfar, Volodymyr Shvydun, Michael Duckering
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Patent number: 11206024Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.Type: GrantFiled: September 25, 2020Date of Patent: December 21, 2021Assignee: Intel CorporationInventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
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Patent number: 11199663Abstract: A plurality of bandpass filters (2) are arranged side by side in a row on a fixed surface (1a) of a glass block (1) and fixed using an adhesive (3). Each bandpass filter (2) includes a coating film (6) for transmitting or reflecting light depending on a wavelength. Each bandpass filter (2) includes a first surface (2a) fixed to the fixed surface (1a), and a second surface (2b) opposite to the first surface (2a) and having a width larger than that of the first surface (2a). Opposing side surfaces of the adjacent bandpass filters (2) include a first portion (2c) on the first surface (2a) side and a second portion (2d) on the second surface (2b) side. A spacing between the first portions (2c) of the adjacent bandpass filters (2) is wider than a spacing between the second portions (2d) of the adjacent bandpass filters (2).Type: GrantFiled: April 5, 2018Date of Patent: December 14, 2021Assignee: Mitsubishi Electric CorporationInventors: Toshiharu Kato, Shinichi Takagi
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Patent number: 11159444Abstract: A packet processing device includes a first unit, a second unit, and a switching unit. The first unit counts the number of arrived packets in a first period that is from the time slot present after a priority section up to the end of the initial time slot in the subsequently-arriving priority section. When the counted number of arrived packets is positive, the first unit determines that forward mismatch has occurred in an observation cycle. The second unit counts the number of arrived packets in a second period which is from the time slot present immediately after the priority section in the first period of time up to the end of the initial time slot of burst sections in the subsequently-arriving priority section. When the counted number of arrived packets is “0”, the second unit determines that backward mismatch has occurred in the observation cycle.Type: GrantFiled: February 4, 2019Date of Patent: October 26, 2021Assignee: FUJITSU LIMITEDInventor: Kazuto Nishimura
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Patent number: 11159148Abstract: A first-in/first-out (FIFO) buffer includes at least one latch-based FIFO storage line, an input flip-flop stage upstream of the at least one latch-based storage line, an output flip-flop stage downstream of the at least one latch-based storage line. The output flip-flop stage functions as an additional storage line. Clock-gating circuitry separate from the device clock controls timing of the at least one latch-based FIFO storage line, the input flip-flop stage, and the output flip-flop stage. The input flip-flop stage functions as a second additional storage line, or as an input sampling stage. Optional bypass circuitry between the input flip-flop stage and the output flip-flop stage passes data for a storage line directly to the output flip-flop stage, without passing through the at least one latch-based storage line, when the buffer is empty.Type: GrantFiled: January 27, 2020Date of Patent: October 26, 2021Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Lior Moheban, Alex Pinskiy, Yakov Tokar
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Patent number: 11134451Abstract: A terminal apparatus in an initial access calculates, from the RSRP of the SS block, a downlink path loss used for transmission power of the PRACH, and determines a reference used for the downlink path loss used for transmission power of a first PUSCH scheduled by a random access response grant, based on system information included in the random access response grant, wherein the system information further includes a first parameter for indicating a subcarrier spacing for the first PUSCH and a second parameter for indicating a signal waveform for the first PUSCH.Type: GrantFiled: April 24, 2018Date of Patent: September 28, 2021Assignees: FG Innovation Company Limited, Sharp Kabushiki KaishaInventors: Wataru Ouchi, Tomoki Yoshimura, Shoichi Suzuki, Liqing Liu
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Patent number: 11082340Abstract: The present invention relates to a transmitting apparatus, a transmitting method, and a receiving apparatus that are to preferably transmit content composed of a file. A transmission stream is transmitted to a reception side through a predetermined transmission path. In the transmission stream, a first transmission packet including transmission media and a second transmission packet including information related to the transmission media are time-division multiplexed. When the transmission media included in the first transmission packet is divided data of a file that composes predetermined content, identification information for identifying divided data included in the first transmission packet is inserted into the first transmission packet and the second transmission packet.Type: GrantFiled: May 19, 2015Date of Patent: August 3, 2021Assignee: SONY CORPORATIONInventor: Naohisa Kitazato
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Patent number: 11070245Abstract: A transmission method, and corresponding transmitter are provided that use a combination of sparse symbol mapping with non-sparse spreading. This can be used for a low-PAPR multiple access scheme where good performance is achieved by sparse domain multi-user detection. The provided method uses per-frequency block time-domain non-sparse spreading across sparse blocks which provides PAPR reduction. Sparsity patterns are partitioned into groups that allows PAPR reduction. The method may be used to support the transmission of a single-carrier signal, e.g. DFT-spread signal, to provide PAPR reduction. More generally the provided method can use any low-PAPR waveform, for example any single-carrier waveform or any single-subcarrier waveform.Type: GrantFiled: August 21, 2020Date of Patent: July 20, 2021Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Sanjeewa Herath, Monirosharieh Vameghestahbanati, Javad Abdoli
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Patent number: 11064239Abstract: Centralized storage and playback of user-recorded television programming eliminates the need for expensive DVR devices to be deployed in the field. Further, the methods used to initiate storage and provide playback of stored media respect copyright principles.Type: GrantFiled: January 4, 2019Date of Patent: July 13, 2021Assignee: CSC Holdings, LLCInventors: Richard W. Neill, Stephanie Mitchko, Peter Caramanica
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Patent number: 11057135Abstract: A transmitter includes a memory, and a processor configured to generate a first clock parallel signal by performing serial-parallel conversion of a first clock signal acquired by using a reference clock and generate a second clock parallel signal by performing serial-parallel conversion of a second clock signal acquired by using the reference clock, generate first compressed information by compressing the first clock parallel signal on the basis of clock periodicity and generate second compressed information by compressing the second clock parallel signal based on the clock periodicity, generate a serial signal by adding a synchronization signal indicating a top of a multiplexed signal to the multiplexed signal generated by time-division multiplexing of the first compressed information and the second compressed information, and transmit the serial signal to a receiver.Type: GrantFiled: February 5, 2019Date of Patent: July 6, 2021Assignee: FUJITSU LIMITEDInventors: Hitomi Toyoda, Eiji Gobaru, Haruhisa Fukano, Takuya Nishioka, Atsunori Machida
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Patent number: 11049536Abstract: A memory device includes a memory control unit and a write output clock device. The memory control unit is used to provide a write input clock and a first control value. The write output clock device produces a plurality of internal clocks based on the write input clock, and selects a target internal clock from the plurality of internal clocks, and further delays the target internal clock to become a write output clock to a memory unit based on the first control value. The memory unit produces a data signal based on the write output clock. The memory control unit identifies whether the write output clock meets the time-sequence requirements of the memory unit. If the time-sequence requirements are not met, the memory control unit changes the first control value and/or changes the selected target internal clock to change the write output clock.Type: GrantFiled: October 8, 2019Date of Patent: June 29, 2021Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.Inventors: Chen Chen, Qiang Si
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Patent number: 10911796Abstract: A content provider might be responsible for content transmitted over a large number of channels, including premium channels that may have fixed quality settings. In order to provide the appropriate quality, the encoders for the premium channels are able to obtain the bit rates (and other capacity) needed. The total bit rate used for the premium channels can then be compared against a maximum bit rate for all channels for the provider to determine a remaining bit rate. The remaining bit rate can then be allocated, evenly or otherwise, across the various non-premium channels. Transmission components such as statmuxes used for the non-premium channels can be configured to adjust the bit rates as necessary based at least in part upon the allocation. Such an approach enables the premium channels to provide the fixed quality ensuring that the aggregate bandwidth meets the bit rate limit.Type: GrantFiled: November 19, 2019Date of Patent: February 2, 2021Assignee: Amazon Technologies, Inc.Inventor: Olaf Nielsen
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Patent number: 10855507Abstract: Disclosed herein is a method of receiving a broadcast signal. The method comprises receiving the broadcast signal; an Orthogonal Frequency Division Multiplexing (OFDM) demodulating on the received broadcast signal; parsing at least one signal frame from the demodulated broadcast signal to extract service data or service component data; converting the service data or service component data into bits; decoding the converted bits; and outputting a data stream comprising the decoded bits.Type: GrantFiled: February 7, 2020Date of Patent: December 1, 2020Assignee: LG ELECTRONICS INC.Inventors: Jongseob Baek, Woosuk Ko, Sungryong Hong
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Patent number: 10831954Abstract: Efficiency of electronic design automation is increased by accessing a data structure characterizing a hierarchical integrated circuit design including sub-blocks each with a plurality of ports. For each given one of the ports of each of the sub-blocks, obtain a wire specification for a corresponding net connected to the given one of the ports in the design, and based on the wire specification, consult a technology-specific lookup table to determine at least one of a corresponding default driving cell and default electrical model for an external wire coupling one of the default driving cell and an actual driving cell to the given one of the ports. Optimize each of the sub-blocks out-of-context based on the at least one of default driving cells and default electrical models; verify in-context closure for the optimized sub-blocks; and, responsive to the in-context closure, update the data structure to reflect the optimized sub-blocks.Type: GrantFiled: October 29, 2019Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Debjit Sinha, Ravi Chander Ledalla, Chaobo Li, Adil Bhanji, Gregory Schaeffer, Michael Hemsley Wood
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Patent number: 10790827Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.Type: GrantFiled: December 27, 2018Date of Patent: September 29, 2020Assignee: Intel CorporationInventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
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Patent number: 10783102Abstract: Techniques are provided for configuring and operating hardware to sustain real-time hashing throughput. In an embodiment, during a first set of clock cycles, a particular amount of data items of a first data column are transferred into multiple hash lanes. During a second set of clock cycles, the same particular amount of data items of a second data column are transferred into the hash lanes. The transferred data items of the first and second data columns are then processed to calculate a set of hash values. When combined with techniques such as pipelining and horizontal scaling, the loading, hashing, and other processing occur in real time at the full speed of the underlying data path. For example, hashing throughput may sustainably equal or exceed the throughput of main memory.Type: GrantFiled: October 11, 2016Date of Patent: September 22, 2020Assignee: Oracle International CorporationInventors: David Brown, Rishabh Jain, David Hawkins
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Patent number: 10713265Abstract: Methods and systems quantize and compress time series data generated by a resource of a distributed computing system. The time series data is partitioned according to a set of quantiles. Quantized time series data is generated from the time series data and the quantiles. The quantized time series data is compressed by deleting sequential duplicate quantized data points from the quantized time series data to obtain compress time series data. Quantization and compression are performed for different combinations of quantiles. The user may choose to minimize information loss of information due to quantization while selecting a lower bound for the compression rate. Alternatively, the user may choose to maximize the compression rate while placing an upper limit on the loss of information due to quantization. The compressed time series data that satisfies the user selected optimization conditions may be used to replace the original time series data in the data-storage device.Type: GrantFiled: June 20, 2017Date of Patent: July 14, 2020Assignee: VMware, Inc.Inventors: Arnak Poghosyan, Ashot Nshan Harutyunyan, Naira Movses Grigoryan
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Patent number: 10699310Abstract: In general, techniques are disclosed to facilitate communicating within computer networks. For example, a layer three (L3) router including a service card and an interface card may be configured to perform the techniques. The interface card receives a query from a network that sources communications in accordance with a plurality of models. The query may specify a customer device and one of the sourced communications, and request that the service card select one of the models for the specified sourced communication and the specified customer device. The service card further stores data defining a profile for the one of the customer devices. The service card may also, in response to the query, analyze the profile data for the specified customer device to determine the selected one of the models for the specified sourced communication with respect to the specified customer device.Type: GrantFiled: May 11, 2016Date of Patent: June 30, 2020Assignee: Juniper Networks, Inc.Inventors: Ramesh Panwar, David Weinberg
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Patent number: 10678354Abstract: An electronic system is provided, which includes a mainboard, a pointing stick and a touchpad module, a first transmission path and a second transmission path. The mainboard is disposed with a first connecting unit. The pointing stick is connected to the first connecting unit through a transmission line. The touchpad module includes a circuit board, a second connecting unit and a controller. The circuit board includes a touch sensor. The first transmission path and the second transmission path are connected between the first connecting unit and the second connecting unit. The sensing signal outputted by the pointing stick is transmitted to the controller through the transmission line, the first connecting unit, the first transmission path and the second connecting unit. The output signal of the controller is transmitted to the mainboard through the second connecting unit, the second transmission path and the first connecting unit.Type: GrantFiled: March 21, 2019Date of Patent: June 9, 2020Assignee: ELAN MICROELECTRONICS CORPORATIONInventors: Yen-Shih Lin, Tien-Wen Pao, Nan-Jung Liu
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Patent number: 10666413Abstract: A user equipment (UE) transmits uplink control information (UCI) and a base station receives UCI when the UE is configured to have a number of cells configured for operation with carrier aggregation (CA). The base station configures the UE with a code rate and the UE determines a maximum UCI payload to transmit in a subframe that results in a transmission code rate that is no larger than the configured code rate. For transmission of aperiodic channel state information (A-CSI), a number of triggering states depends on the number of cells.Type: GrantFiled: January 22, 2018Date of Patent: May 26, 2020Assignee: Samsung Electronics Co., Ltd.Inventor: Aris Papasakellariou
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Patent number: 10666361Abstract: Provided is a sending control apparatus including a transmission path determination section that determines, from a plurality of transmission paths connected to different sending sections, respectively, one or more sending transmission paths that transmits one or a plurality of transmission object signals, respectively, obtained from sending data, on a basis of the number of sending transmission paths and prescribed information and a sending control section that controls the sending section connected to the sending transmission path so that the transmission object signal is sent via the sending transmission path.Type: GrantFiled: September 12, 2016Date of Patent: May 26, 2020Assignee: SONY CORPORATIONInventors: Toshihisa Hyakudai, Toshiyuki Miyauchi
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Patent number: 10616056Abstract: Aspects of the subject disclosure may include, a system for receiving first electromagnetic waves that propagate along a transmission medium, where the first electromagnetic waves convey first data, generating first signals by frequency-shifting the first electromagnetic waves without demodulating the first electromagnetic waves, and providing the first signals to one or more modems that facilitate demodulation of the first signals to second signals, and distribution of a first portion of data conveyed by the second signals to an access point, a second portion of the data to a second waveguide system, or combinations thereof. Other embodiments are disclosed.Type: GrantFiled: March 27, 2018Date of Patent: April 7, 2020Assignee: AT&T Intellectual Property I, L.P.Inventors: Farhad Barzegar, Giovanni Vannucci, Paul Shala Henry, Thomas M. Willis, III, Irwin Gerszberg, Robert Bennett, Donald J. Barnickel