Abstract: A device for modulating communication signals comprises a transceiver for receiving and transmitting the signal, a storage medium storing computer implemented programme code components to generate sequences and a processor in communication with the storage medium and transceiver. The processor executes computer implemented programme code components to generate a family of shift sequences or arrays using exponential, logarithmic or index functions and a polynomial or a rational function polynomial in i?p?1 for a finite field p of prime p. Multiple columns of the arrays are substituted with pseudo-noise sequences or other suitable good correlation sequences in a cyclic shift equal to the shift sequence for the respective column to generate a substituted array. The substituted array, or a sequence unfolded using the CRT from the array when the array dimensions are relatively prime, is applied to a carrier wave of the communication signal to generate a modulated communication signal.

Abstract: A device for modulating communication signals comprises a transceiver for receiving and transmitting the signal, a storage medium storing computer implemented program code components to generate sequences and a processor in communication with the storage medium and transceiver. The processor executes computer implemented program code components to generate a family of shift sequences or arrays using exponential, logarithmic or index functions and a polynomial in i?Zp?1 for a finite field Zp of prime p. Multiple columns of the arrays are substituted with pseudo-noise sequences in a cyclic shift equal to the shift sequence for the respective column to generate a substituted array. The substituted array, or a sequence unfolded using the CRT from the array when the array dimensions are relatively prime, is applied to a carrier wave of the communication signal to generate a modulated communication signal.

Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header may include an invert bit to alter the majority sign of an n-bit portion. Other aspects of the present invention are also described herein.

Abstract: An Ethernet physical layer (PHY) module is provided with a method for transceiving between a 10GBASE-R client interface and a 100G attachment interface. On each of ten client interface logical lanes a 10GBASE-R signal is accepted. Each 10GBASE-R logical lane is demultiplexed into two 5 gigabit per second (Gbps) pseudo 100GBASE-R logical lanes, creating a total of twenty pseudo 100GBASE-R logical lanes. The pseudo 100GBASE-R logical lanes are arranged into n groups of 20/n pseudo 100GBASE-R logical lanes. Further, the pseudo 100GBASE-R logical lanes from each group are arranged into a 100G attachment logical lane. Finally, a 100G attachment logical lane is transmitted at an attachment interface on each of n physical lanes. In the reverse direction, each of n physical lanes accepts a 100G attachment logical lane at the attachment interface, and a de-aggregation process supplies a 10GBASE-R signal on each of ten client interface logical lanes.

Abstract: The present invention provides systems and methods for adaptive digital data transmission rate control. A digital data transmission system for adaptively transferring packets over a transmission link includes a client device having a bandwidth control module and a host device coupled to the client device over the transmission link. The host device includes one or more bandwidth control registers and a packet builder. The bandwidth control module determines a packet speed and/or size for packets transmitted from the host device to the client device over the transmission link. The bandwidth control registers store the requested packet size and/or rate. The packet builder accesses these registers when transmitting packets to determine the requested packet size and/or rate.

Abstract: An apparatus and media are provided for more effectively utilizing modems in a WiMAX environment. The apparatus connects a computing device to a network-based information system through at least a first WiMAX modem that is located within the apparatus. A second WiMAX modem can be removably coupled to the apparatus so as to connect the first computing device to the network in combination with the first WiMAX modem. In the event the second WiMAX modem is removed, network connectivity provided by the first WiMAX modem is maintained.

Abstract: Certain aspects of the present disclosure provides techniques for a handshaking protocol, and corresponding circuit elements, for an asynchronous network. The techniques utilize a clock-less delay insensitive data encoding scheme. The proposed network may operate correctly regardless of the delay in the interconnecting wires.

Abstract: The present invention provides systems and methods for adaptive digital data transmission rate control. A digital data transmission system for adaptively transferring packets over a transmission link includes a client device having a bandwidth control module and a host device coupled to the client device over the transmission link. The host device includes one or more bandwidth control registers and a packet builder. The bandwidth control module determines a packet speed and/or size for packets transmitted from the host device to the client device over the transmission link. The bandwidth control registers store the requested packet size and/or rate. The packet builder accesses these registers when transmitting packets to determine the requested packet size and/or rate.

Abstract: This document describes tools useful in relaying a data stream from a data device to a network tunnel, such as by injecting in-band control messages without impacting a data rate. For example, the tools may receive data packets on a first link and then relay the data packets to a data device on a second link. While doing so, the tools may periodically free an amount of link time by reducing the length of the relayed data packets by reducing the length of a header of each data packet. The tools may then consume the freed link time by sending a control message on the second link to the data device.

Abstract: Given a hardware platform capable of capturing framed data in a multiplexed fashion from multiple sources, a method and apparatus are shown for providing a constant frame rate for each logical stream.

Abstract: A digital broadcast transmitting/receiving system and a method for processing data are disclosed. The method for processing data may enhance the receiving performance of the receiving system by performing additional coding and multiplexing processes on the traffic information data and transmitting the processed data. Thus, robustness is provided to the traffic information data, thereby enabling the data to respond strongly against the channel environment which is always under constant and vast change.

Abstract: To improve transmission of digital broadcast information, there is proposed a method of transmitting digital broadcast information from a main transmitter (12) to at least one repeater (14). There is generated a composite digital broadcast signal carrying first digital broadcast information according to a first digital broadcast specification (DVB-T) and second digital broadcast information according to a second digital broadcast specification (DVB-H). The composite digital broadcast is then broadcasted such that the second digital broadcast information (DVB-H) is sent in a transmission mode used for transmission of the first digital broadcast information (DVB-T).

Abstract: A system and method are provided for more effectively utilizing modems in a WiMAX environment, so as to improve network connectivity while providing access for both fixed as well as portable computing devices. The apparatus connects one or more computing devices to a network-based information system through at least a first WiMAX modem that is located within the apparatus. A second WiMAX modem can be removably coupled to the apparatus so as to improve network connectivity and operability. In the event, the second WiMAX modem is removed and coupled to a portable computing device, network connectivity provided by the first WiMAX modem is maintained.

Abstract: A method and apparatus for reducing service impairment in a LAG are provided. The method includes: dividing a service packet into multiple service sub-flows, and allocating the multiple service sub-flows to all the physical ports averagely; after a new port is added, configuring a preset quantity of service sub-flows for the new port; or, after a port is deleted, allocating the service sub-flows on the deleted port to other ports; and finding a forwarding physical port through a service packet according to the service sub-flows. An apparatus for reducing service impairment in a LAG includes: an initializing module, a new port processing module or a deleted port processing module, and a forwarding port search module. In the case of adding or deleting a port, only the affected service sub-flows are operated, thus minimizing the impact.

Abstract: In retransmission processing due to a failure of transmission of data packets, a plurality of data packets are simultaneously transmitted between two STAs by utilizing multiple wireless channels and MIMO, and the number of idle channels and the number of retransmission packets are compared. Then, when both of the numbers are different or only when the number of idle channels is larger than the number of retransmission packets, the retransmission packets are reconstructed according to the number of idle channels, and the reconstructed retransmission packets are simultaneously transmitted by using the idle channels.

Abstract: A demultiplexer includes an input terminal for providing an input signal, a plurality of output terminals for outputting the input signal, and a switching circuit coupled among the input terminal and the plurality of output terminals, and outputting the input signal selectively from the plurality of output terminals according to a plurality of control signals provided to a plurality of control terminals. For miniaturizing the demultiplexer, the switching circuit includes one or more switch elements connected between the input terminal and each of the output terminals in series, wherein at least two of the switch elements coupled to different output terminals are simultaneously switched in response to one control signal from the plurality of control terminals.

Abstract: Systems and methods for conveying multiple low-bit-rate data streams over a data transport medium which is configured to transport data in a single, high-bit-rate data stream. In one embodiment, a plurality of low-bit-rate signals are received and a corresponding data rate is determined. Each of the signals is formatted in frames comprising a payload and overhead data. The high-bit-rate signal is also formatted in frames comprising a payload and overhead data, but the frames (including payload and overhead) contain more bits than those of the low-bit-rate frames. The payloads of the low-bit-rate frames are mapped into the payloads of the high-bit-rate frames. The overhead and timing data of the low-bit-rate frames are mapped into the unused portion of the overhead of the high-bit-rate frames. After the high-bit-rate signal is transported, the payload, overhead and timing data of each of the low-bit-rate signals is extracted, and the corresponding signals are reproduced.

Abstract: The present invention a synchronous peer to peer transfer model that utilizes all available network bandwidth to deploy application code to an entire cluster as fast as it can be sent to one machine. A method in accordance with an embodiment of the present invention includes: determining a number N of simultaneous connections that should be opened to the cluster members to maximize network bandwidth; and synchronously deploying the application to the cluster members using the N simultaneous connections.

Abstract: Methods and systems for dual digital microphone processing in an audio CODEC are disclosed and may include demultiplexing one or more received time-multiplexed digital audio signals from one or more digital microphones, and separately processing each of the demultiplexed digital audio signals. The digital microphones may include microelectromechanical (MEMS) microphones. The demultiplexed digital audio signals may be level-converted, downshifted, and/or filtered. The filtering may include a finite impulse response (FIR) filter. A sampling rate of the one or more demultiplexed digital audio signals may be converted by repeating the demultiplexed digital audio signals. Audio beamforming and/or diversity processing may be performed utilizing the digital microphones.

Abstract: A wireless repeater on a communication line has a structure that includes a plurality of wireless communication media, and a band control unit that changes the first bandwidth of the communications line according to increase and decrease in the number of wireless communication media by an operation dividing the first bandwidth of the communications line into a plurality of second bandwidths and an operation multiplexing a plurality of second bandwidths adjusting to the first bandwidth, responding to the number of the wireless communication media.

Abstract: In a data communication circuit, data is multiplexed onto a communication link through multiple multiplexer stages and demultiplexed from the communication link through multiple demultiplexer stages in order that a clock signal applied to each multiplexing circuit need only be precisely distributed to a limited, high frequency portion of the circuit. Each circuit is clocked by a multiplying delayed locked loop bit clock generator. Where the number of parallel bits in the signal between the two stages is greater than two, the higher frequency stage coupled to the communication link is clocked by an N-phase overlapping clock. In the case of a multiplexer, the intermediate frequency signal is enabled in the higher frequency data multiplexer by concurrence of two clock phases.

Abstract: In the face of data loss on connections between a content source and a content consumer, additional connections therebetween are opened. These additional connections are preferably opened between the content source and a proxy disposed between the content source and the content consumer. The proxy may then seam together data streams received from the content source across the additional connections in a recording on a computer-readable medium. The seamed stream may be constructed by filling in information gaps in any of the data streams received from the content source with content derived from others of the data streams received from the content source. This derivation may be made on the basis of identifying characteristics (e.g., packet contents) of packets from each of the data streams received from the content source.

Abstract: Systems and methods for conveying multiple low-bit-rate data streams over a data transport medium which is configured to transport data in a single, high-bit-rate data stream. In one embodiment, a plurality of low-bit-rate signals are received and a corresponding data rate is determined. Each of the signals is formatted in frames comprising a payload and overhead data. The high-bit-rate signal is also formatted in frames comprising a payload and overhead data, but the frames (including payload and overhead) contain more bits than those of the low-bit-rate frames. The payloads of the low-bit-rate frames are mapped into the payloads of the high-bit-rate frames. The overhead and timing data of the low-bit-rate frames are mapped into the unused portion of the overhead of the high-bit-rate frames. After the high-bit-rate signal is transported, the payload, overhead and timing data of each of the low-bit-rate signals is extracted, and the corresponding signals are reproduced.

Abstract: An OC3 to three DS3 SONET multiplexer is provided employing a field programmable gate array and other components in a single Type 400 mechanics card to achieve a form factor that is substantially reduced when compared to existing SONET multiplexers. The OC3 to three DS3 SONET multiplexer has integral optical redundancy and automated provisioning. Manual switches are provided to select continue/drop and line build out for each DS3. Switches are also provided for loopback options. The face plate for the multiplexer provides front access to all of the OC3 and DS3 connectors. The multiplexer is interchangeable with DS3 to DS1 multiplexer cards and WDM cards in a compact M13 SONET enclosure that is particularly useful at wireless cell sites.

Abstract: The preferred embodiment of the present invention provides an improved transport demultiplexor that can receive and filter different data types before sending the data to system memory. The preferred embodiment provides a string comparator to facilitate real time filtering of continuous incoming data before loading the data into system memory. The string comparator preferably uses a bit-maskable matching filter that filters system data in real time as the data is being delivered to system memory. When data matching the filter is located, the destination address of that data is determined and delivered to the processor. This allows the processor to quickly locate the desired data and thus facilitates the real time processing of that data.

Abstract: A SONET multiplexed system architecture that permits greater levels of integration. The architecture includes a time slot interchanger for routing information from at least one SONET input signal path associated with a respective first time slot to at least one SONET output signal path associated with a respective second time slot. Each input signal path includes a pointer interpreter, and each output signal path includes a FIFO buffer serially coupled to a pointer generator. The architecture further includes a synchronization buffer in each input signal path for transferring the input signal to the clock rate of the time slot interchanger. The architecture permits greater levels of integration when the time slot interchanger has more inputs than outputs, and/or the time slot interchanger provides the output signal to a pointer processor to transfer the output signal to the clock rate of the output signal path.

Abstract: Variable bit rate information is transmitted across a transmission link (20) at a constant bit rate by multiplexing individual variable bit rate elementary data streams (161 and 162) into a composite data stream (18) having a constant bit rate. A receiving device (22) receives the constant bit rate stream but delays processing thereof by an interval typically a fraction of the transmission interval. Following the delay interval, the receiving device processes the data at a rate that is independent of, but typically not greater than, the constant bit rate.

Abstract: The present invention provides methods and apparatus for reconfiguring protocol data for a multiplexed data stream which is reduced to carry fewer services for cable-side transmission in a cable television plant or the like. More particularly, the present invention provides methods and apparatus for reconfiguring protocol data for a desired combination of multiplexed data stream subgroups contained within an incoming high data rate data stream, such as a high data rate Quadrature Phase Shift Keying (QPSK) modulated multiplexed data stream, when the incoming multiplexed data stream is reduced.

Abstract: In a control device for a storage device in which data streams are respectively divided into unit data, which are distributed to storage parts and are sequentially read therefrom for every unit data, there is provided a buffer memory which stores data to be written into the storage parts and data read from the storage parts. An input/output control part causes the unit data from the storage parts in an access cycle corresponding to a bit rate to be stored in the buffer memory and causes the unit data stored in the buffer memory at the bit rate to be written into the storage parts. An input/output interface part reads the unit data from the buffer memory at the bit rate and causes the data transferred at the bit rate to be stored in the buffer memory.

Abstract: A transmitting device cyclically distributes a plurality of cells to a plurality of lines in a predetermined order. The transmitting unit loads the same cell block number into the cells to be distributed to the lines in the same cycle, and transmits the cells to the lines. A receiving device, whenever receiving the cells from the transmitting device via the lines, arranges the cells into which the same cell block number is loaded in the predetermined order.

Abstract: A technique for performing a time slot interchange in a processor. The TSI process is surrounded by a multiplexing/demultiplexing circuit for converting a plurality of PCM highways into a single input serial data stream. The mux/demux circuit includes elastic stores to align frames and shift resisters to mux/demux with a minimum of delay. The TSI processor includes an input and an output buffered serial port, a pair of input buffers, one to receive even-numbered frames from the PCM highways and one to receive odd-numbered frames, and an output buffer. Data is read from the appropriate input buffer in a non-sequential fashion as commanded by the processor in accordance with information stored in connection arrays (address buffers). The data is then written to the output buffer sequentially. The timing of the reading and writing steps is optimized relative to free running buffered serial port pointers for each BSP to reduce the frame delay.

Abstract: A multicarrier transmission system (100) routes data symbols from a data source (142) to a multicarrier modulator (145). Each modulator (201, 202, 203) within the multicarrier modulator (145) is coupled to a corresponding gain adjuster (211, 212, 213) that distributes the available transmit power across various subcarriers. Power distribution, is determined in part, upon the noise sensitivity of the transmitted information. In accordance, data stream symbols of like sensitivity are grouped (520) and transmitted during defined time intervals. Each such group is assigned a unique transmission power level (530). At any given moment in time, all subcarrier transmission power levels will have an identical amplitude, thereby mitigating the impact of subchannel-to-subchannel interference.

Abstract: An interface device is provided which may be used to perform rate adaptation and time slot assignment, in either the transmit or receive directions, in a multiplexing unit for interfacing a high rate optical carrier line to a plurality of lower rate information carrier lines. The high rate optical carrier line may be a SONET or SDH carrier line. The interface device according to the present invention may be operationally configured to provide data rate adaptation and time slot assignment between an optical carrier line operating at an OC-12 rate with lower rate lines operating according to OC-3, OC-1, DS-3, or DS-1 protocols, or even virtual channels. A plurality of identical interface devices may be cascaded together and used to perform interface support for various channels operating at various rates, merely by manipulating the operational configuration of the individual interface devices in the cascade.

Abstract: A method for initializing a network for data transmission between a plurality of subscribers being connected to one another in ring-like fashion, includes sending a clock signal through the network in a continuous data stream, originating at a network position. In each subscriber, a process of locking onto the clock frequency is started after reception of the data stream, and the data stream is forwarded to the next subscribers in succession after locking on is completed. In order to speed up the initializing process, the arriving data stream is split into two identical streams at each subscriber, as long as it has not yet locked on. One of the streams is used for the locking-on process and the other of the streams is immediately forwarded to the next subscriber.

Abstract: An interface unit having a digital hierarchy interface function for a communication device has parts disposed on a printed-wiring board in a Layout to maintain desired interface unit characteristics. The interface unit includes a plurality of parallel B/U converter blocks for converting bipolar signals in a plurality of channels into a plurality of unipolar signals, respectively, a plurality of parallel U/B converter blocks for converting unipolar signals in a plurality of channels into a plurality of bipolar signals, respectively, a connector disposed near the B/U converter blocks for connecting the B/U converter blocks to an external device, a shared processor LSI circuit connected to the B/U converter blocks and the U/B converter blocks and disposed near the U/B converter blocks, for interfacing the signals in the channels at a low speed, and a printed-wiring board supporting the B/U converter blocks, the U/B converter blocks, the connector, and the shared processor LSI circuit.

Abstract: In known optical distribution systems, a signal intended for the subscribers is distributed from a transmitting point to all network terminations (point-to-multipoint transmission). The receivers, which are connected to a passive optical network, are adapted to a common bit rate. If a need for a higher data rate arises at a network termination, this need can only be satisfied in the prior art by converting all receivers. This is not possible without interrupting the service. Furthermore, the conversion entails great expense, since the receivers of these network terminations where the need for information is unchanged have to be converted as well. By a time-division-multiplexing method, a time-division multiplex signal is generated which has a frame whose duration is equal to one bit period (T) of a digital signal, and which is divided into k time slots (ZS). At least two time slots (ZS) are used for one digital signal, and one respective time slot (ZS) is used for each of the remaining digital signals.

Abstract: A linear phase detector used with half-speed quadrature clock architecture is provided. The linear phase detector includes a first circuit receiving a data signal, a first half-speed quadrature clock signal and a second half-speed quadrature clock signal. The first circuit generates an adjusted data signal and a polarity representing signal of the first half-speed quadrature clock signal. A high speed phase detector is coupled to the first circuit for generating a linear phase correction signal.