Abstract: The invention relates to a method for streaming of media from a streaming server (111) to a mobile client device (101) over an air-interface, wherein, after a cell reselection, the method comprises requesting the streaming server (111) to resend streaming media which the mobile client device (101) was not able to receive due to the cell reselection.

Abstract: The invention is relevant to optical fiber transmission systems, and in particular, pertains to the transceiver cards in an optical fiber transport system. In particular the invention teaches an improved transceiver card architecture that allows high density, flexibility and interchangeability of functionality.

Abstract: A high-speed interface for implementation in a programmable device such as, e.g., a programmable logic device (“PLD”) is described. Multi-gigabit transceivers of the PLD provide transmit and receive lock signals and have inputs for reference transmit and receive clock signals. One of the multi-gigabit transceivers provides a first transmit clock signal, a first receive clock signal, and a second receive clock signal. A data rate converter fractionally multiplies a second transmit clock signal to provide the reference transmit clock signal. A skew synchronization block obtains respective transmit and receive lock signals from the multi-gigabit transceivers and provides respective receive and transmit synch adjustment signals to the multi-gigabit transceivers. Synchronous operation of the multi-gigabit transceivers in receive and transmit directions is adjusted with receive and transmit synch adjustment signals to maintain lane-to-lane skew for the high-speed interface within a target range.

Abstract: A system and method for processing of MPEG transport streams. Specifically, the system may receive a variable bit rate input transport stream with one or more programs. The variable bit rate transport stream is converted into a constant bit rate stream with compliant Program Clock References. Null packets are added to the transport stream at suitable locations to pad it to a constant bit rate. Program clock reference packets are re-stamped to ensure all timing requirements are met.

Abstract: A bit stream multiplexer and a bit stream demultiplexer of the present invention couples a communication Application Specific Integrate Circuit (ASIC) to a high-speed bit stream media. The bit stream multiplexer includes a first transmit data multiplexing integrated circuit having an input that receives a first plurality of bit streams at a first bit rate from the communication ASIC and an output that produces a second plurality of bit streams at a second bit rate, the second plurality having fewer bit streams than said first plurality. It further includes a second transmit data multiplexing integrated circuit having an input that receives the second plurality of bit streams at the second bit rate and an output that produces a single bit stream at a line bit rate, the single bit stream having a predetermined bit order. The bit stream demultiplexer includes similar demultiplexing integrated circuits.

Abstract: A system and method are provided for a sampled accumulation method that maps information into Synchronous Payload Envelopes (SPEs). The method buffers data from a plurality of tributaries, and sequentially stores buffer-fill information for each tributary in a first memory, at a rate of up to one tributary per system clock (Fsys) cycle. A stored accumulation of buffer-fill information for each tributary is updated at a sample rate frequency (Fsample), where Fsample?Fsys. The stored accumulation of buffer-fill information is used to calculate stuff bit opportunities for each tributary. As a result, the rate of data being mapped into outgoing tributaries is regulated, and the outgoing mapped tributaries are combined in a SPE.

Abstract: The object of the invention is to enhance data transmission efficiency by considering a clock frequency, a data transmission method and a data storage method.

Abstract: A mechanism for implementing a single-interrupt-based voice playout buffer transfer operation. The contents of each respective channel of a multi-channel voice playout buffer are encapsulated so as to prepend a four byte ATM header, a HEC byte, and a four byte AAL2 header to a forty-four byte voice channel field to realize a standard fifty-three byte ATM cell. Within the AAL2 header, a channel identification byte (CID) provides selective mapping to timeslots of a TDM frame, to accommodate variations among different vendor equipments. The next to last bit of the last byte of the ATM header is used as an interrupt to the network processor. Only the highest voice channel asserts this next to last bit as an interrupt bit.

Abstract: Embodiments of the present invention provide a system for transferring data between a receiver chip and a transmitter chip. The system includes a set of data path circuits in the transmitter chip and a set of data path circuits in the receiver chip coupled to a shared data channel. In addition, the system includes a set of asynchronous control circuits for controlling corresponding data path circuits in the transmitter chip and receiver chip. Upon detecting the transition of a control signal for an asynchronous control circuit in the transmitter chip, the asynchronous control circuit is configured to enable a transfer of data from the corresponding data path circuit in the transmitter chip across the data channel to a corresponding data path circuit in the receiver chip, and generate a control signal to cause a next asynchronous control circuit to commence the transfer of a data signal.

Abstract: A wireless system has a high rate data channel for time multiplexed communications to multiple mobile stations (MSs). Control channels include a forward link common power control channel and reverse link feedback channels for pilot, forward channel quality, and data acknowledgements from each MS. An MS can have an active state for data communications, for which these control channels are used at the full (time slot) rate, or a control hold state, in which acknowledgements are not needed and the others of these control channels can be shared among a plurality of MSs in the control hold state and each using a reduced rate such as ½, ¼, or ? of the full rate. The arrangement can support an increased number of active MSs, facilitating an increased total throughput on the high rate data channel, without increasing system resources for the control channels.

Abstract: A high-speed serial demultiplexer receives over four high-speed serial data lines at a nominal rate of 10 GBPS and demultiplexes the data to 16 lines with a rate of 2.5 GHz each. The demultiplexer circuits are configured as two D type latches, one of which latches data on the positive edge of a 5 GHz clock, the other of which latches every other bit of the 10 GBPS data on the negative edge of the 5 GHz clock, alternating with the first D latch. Each of the two D latches is configured as a master-slave flip-flop that includes a master D latch and a slave D latch. The master receives the data at the 10 GBPS rate and clocks every other bit to its output using an edge of the 5 GHz clock (the positive edge for one of the D-latches, the negative for the other). The slave clocks the data form the master to its output on the opposite edge of the clock following the master.

Abstract: This invention relates to a flexible rate matching method, comprising the steps of: a) receiving a continuous stream of data items at a prespecified rate of a clock signal in a configurable data shift register; b) storing, for each data item stored in the data shirt register, an associated indication of validity in a configurable validity shift register and shifting the indications of validity at said prespecified rate; c) modifying the contents of the data shift register and the validity shift register through puncture/repetition operations so as to achieve a rate matching, and d) outputting valid data items at said prespecified rate using said indications of validity stored in the validity shift register. The invention also relates to a corresponding flexible rate matching apparatus as well as to a computer program product and a processor program product.

Abstract: A method converts an input data rate associated with N units of data to an output data rate associated with M units of data. The method includes calculating N write-control parameters each associated with one of M addresses of an output memory, directing each of N values of input data to an associated address of the output memory in response to the N calculated write-control parameters, and reading the output memory to provide output data associated with the output data rate. If N is greater than M, some of the N write-control parameters are associated with at least one shared address of the M addresses. If M is greater than N, all of the N write-control parameters are associated with different addresses of the M addresses. An apparatus is configured to implement this method.

Abstract: A communication system includes a link module having a first serial interface for interfacing to a serial link. The link module also including a second serial interface. The system also includes a Media Access Control (MAC) module including a parallel interface. The system also includes a converter module, coupled between the parallel interface and the second serial interface, configured to convert symbols, transferred between the parallel interface and the second serial interface, between a parallel format at the parallel interface and a serial format at the serial interface.

Abstract: A technique for provisioning cross-connects in network switching environment includes receiving a portion of the an input data stream including having header data and the payload data, the payload data occurring at a first offset relative to the header data and generating a delayed version of the portion of the input data stream. The technique also includes generating a portion of a retimed data stream by selecting between the portion of the input data stream and the delayed version of the portion of the input data stream, the retimed data stream including the header data and the payload data, the payload data occurring at a second offset relative to the header data.

Abstract: Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.

Abstract: A voice playout buffer for a dual PHY-based integrated access device platform has a plurality of voice signal buffer sections. A respective buffer section has a capacity in excess of the number of digitized voice signal bytes contained in a respective cell-based communication signal. The storage capacity of a buffer section accommodates a communications control processor writing new outgoing digitized voice signal bytes into the first portion of the voice signal buffer section for transport over a TDM communication link, prior to digitized voice signals newly received from the TDM communication link being written into the first portion of the voice signal buffer section.

Abstract: A transmission circuit for realizing a rate adaptation layer of a digital communication system. The transmission circuit includes a processor and a format conversion circuit. The processor is capable of managing transmission rates of input and output digital signals of the digital communication system. The format conversion circuit includes a plurality of input units and output units; each input unit is for receiving a bit according to the input digital signal, and each output unit is for transmitting a bit to form the output signal. Each input unit and output unit are connected by hardware wires to realize data formatting such as bit-reordering, command insertion.

Abstract: An asynchronous sample rate converter interpolates and filters a digital audio input signal to produce a filtered, up-sampled first signal. A FIFO memory receives the first signal and stores samples thereof at locations determined by a write address and presents stored samples from locations determined by a read address. The presented samples are passed through an interpolation and resampling circuit to produce a continuous-time signal which is re-sampled to produce a signal that is up-sampled relative to a desired output. That signal then is filtered and down-sampled to produce the output signal. Sample rate estimating circuitry computes a difference signal representative of a time at which a data sample of the audio input signal is received and a time at which a corresponding audio output sample is required, and address generation circuitry generates the read and write addresses.

Abstract: A method and apparatus for data rate matching, wherein elements to be transmitted are distributed over a number of radio frames via an interleaver and are punctured or repeated, with the puncturing or repetition being carried out in such a manner that, when it is related to the original arrangement of the element before interleaving, the pattern avoids puncturing or repetition of adjacent elements, or of elements which are not far apart from one another.

Abstract: The present invention relates to a circuit termination method and a circuit terminating apparatus that are used for metallic circuits that offer high-speed communication. When a transmission speed is required to be changed due to a change in conditions of a circuit and the like through an opposite circuit terminating apparatus, a service suspension and resumption of a predetermined bit position common to each frame of multi frames, and a service suspension and resumption of a continuous bit string of a predetermined bit length starting from a predetermined bit position of a predetermined frame of the multi frames are performed, and an inputting speed and an outputting speed of a terminal connected to the circuit terminating apparatus is adjusted to be consistent with a transmission speed between the circuit terminating apparatus and a second circuit terminating apparatus.

Abstract: Systems and methods, consistent with the present invention, provide a high-speed line interface for networking devices. Such an interface may be used in networking devices, such as routers and switches, for receiving data from, and transmitting data to, high-speed links, such as those lines carrying data at rates of 2.5 Gbit/sec, 10 Gbit/sec, and 40 Gbit/sec and more. In a preferred embodiment, the interface deserializes data from an incoming data stream onto a multi-line bus so that the data may be processed at a lower clock speed. Packets are extracted from the data on the multi-line bus and distributed among a plurality of switching/forwarding modules for processing.

Abstract: In a transmission system with a transmitter coupled to a receiver a main signal encoded according to a coding property is transmitted together with an auxiliary signal (AUX). In order to transmit the auxiliary signal without needing additional space in the the transmission frame, the auxiliary signal is transmitted by changing the coding property according to a predetermined sequence. This is done by means of the sequencer. In the receiver the decoding of the predetermined sequence is performed by a decoder.

Abstract: A method and apparatus for the transmission of data through multiple clock domains using synchronous and asynchronous FIFOs are described. In an embodiment, a method includes receiving data at a first data transfer rate. Additionally, the method includes storing the data at the first data transfer rate in a synchronous storage device having a first storage area. The data at the first data transfer rate stored in the synchronous storage device is processed. The processing includes removing the data from the synchronous storage device. The processing also includes storing the data at the first data transfer rate in an asynchronous storage device having a second storage area. Additionally, the processing includes transmitting the data out from the asynchronous storage device at a second data transfer rate, wherein the storage area of the synchronous storage device is larger than the second storage area of the asynchronous storage device.

Abstract: Briefly, in accordance with one embodiment, a circuit to encode binary digital signals so as to reduce EMI emissions during signal transmission across a bus or interconnect includes circuitry to apply a pseudo-random pattern of binary digital signals to encode selected binary digital signals so as to reduce the harmonic content of the selected binary digital signals. Briefly, in accordance with another embodiment, a method of encoding binary digital signals so as to reduce EMI emissions during signal transmission across a bus or interconnect includes applying a pseudo-random pattern of binary digital signals to encode selected binary digital signals so as to reduce the harmonic content of the selected binary digital signals.

Abstract: The invention relates to a multiplexing method used in a PDH network. Standard PCM signals are received in the network element, at least some of which are multiplexed on a time-division basis into the same outbound transmission frame, the capacity of the payload portion of the frame substantially corresponding to the capacity required by N PCM signals. In order that ATM cells may be transferred more advantageously than heretofore through an existing PDH network, the multiplexing is implemented as configurable in such a way that the total capacity of the payload portion cab be divided between at least two parts of variable capacity in such a way that each part can be allocated a desired portion of the total capacity of the payload portion in accordance with the current transmission requirement.

Abstract: Data is transferred between a plurality of networks which are not synchronized in clock with each other, without creating either an overflow or an underflow. Data output from a first DVCR is transferred to a second DVCR via a first IEEE-1394 serial bus, a first ATM/IEEE-1394 data transfer apparatus, a first UNI, a first ATM network, an NNI 101, a second ATM network, a second UNI, a second ATM/IEEE-1394 data transfer apparatus, and a second IEEE-1394 serial bus. The second ATM/IEEE-1394 data transfer apparatus stores data in a buffer for each flow and deletes or inserts an empty packet depending upon the amount of data stored in the buffer so as to prevent an overflow and an underflow. A deviation of a time stamp caused by the insertion or the deletion of the empty packet is gradually corrected.

Abstract: A network connection device allowing high-speed data conversion to ensure sufficiently high throughput is disclosed. The network connection device includes a plurality of conversion processors and a layer-4 switch. The layer-4 switch forwards an incoming IP packet to a selected one of the plurality of conversion processors depending on a result of analyzing the IP packet at layer 4. Therefore, the processing of data packet and the processing of control packet can be performed in parallel by the plurality of conversion processors, resulting in high-speed packet transfer.

Abstract: An Ethernet mapping enables high speed Ethernet data streams having a data rate of 10 Gb/s to be transported across a synchronous packet switched network fabric having a standard SONET OC-192 line rate of 9.953280 Gbaud. The 10 Gb/s Ethernet data stream is compressed by removing interframe gaps between successive MAC frames to produce a compressed data stream, which is then mapped to a synchronous container. The synchronous container is then launched across the synchronous packet switched network fabric at a standard SONET OC-192 line rate of 9.953280 Gbaud. The synchronous container is preferably provided as a stripped STS-192c frame having only A1 and A2 octets of the Transport Overhead (TOH).

Abstract: A system for transmitting data includes a receiver that receives data at a first data transfer rate. A processor buffers the data into sequential frames of a predetermined length of time and arranges the frames into a byte of data. A transmitter transmits the byte of data a number of times greater than one and equal to a second data transfer rate divided by the first data transfer rate.

Abstract: In one embodiment of the present invention, a system is provided for use in transmitting data and related control information from a first clock domain to a second clock domain. The system may include a first logic section that may generate respective identification information that may be used to identify respective types of information represented by respective data and related control information. The system may also include memory that may receive and store, at a first clock rate used in the first clock domain, the respective data and related control information. The memory also may store, in association with the respective data and related control information, the respective identification information. The memory may be configured to permit the retrieval, at a second clock rate used in the second clock domain, of the respective data, the respective related control information, and the respective identification information stored in the memory.

Abstract: The present invention makes it possible to efficiently transmit data for statistical multiplexing which is required for control using statistical multiplexing. By utilizing private packets, respective encoding devices transmit encoding difficulties serving as the data for statistical multiplexing to a multiplexer (4) via the same transmission channels as encoded video data and audio data are transmitted. The multiplexer (4) conducts multiplexing processing on data supplied from the respective encoding devices at a first rate R1 larger than a transmission rate on a transmission channel of a subsequent stage, and outputs a transport stream (TSd including the private packets to a statistical multiplexing computer.

Abstract: A low-speed subscriber extension type system interfaces with a switch link through a system backboard, receives a cell transmitted from the switch link, then multiplexes/demultiplexes the received cell through a UTOPIA interface after a switch link and ATM layer processing. A low-speed subscriber physical layer board transmits data, which is physical layer-processed in the low-speed subscriber board, to a low-speed subscriber, and serializes a cell transmitted from the low-speed subscriber board into a clock and data before transmission. Each low-speed extension board exchanges a cell with the low-speed multiplexing/demultiplexing board through a low-speed bus, performs physical layer processing on the cell of the corresponding board, and transmits a received cell to the corresponding subscriber through the low-speed extension physical layer board.

Abstract: The invention pertains to a communication system (300) including one or more communication channels (10), each channel comprising a transmitter unit (20) and a receiver unit (40). Each transmitter unit (20) is connected through an optical fiber link (30) to its associated receiver unit (40). In operation, each receiver unit (20) receives payload data from its associated sending client and adds overhead data to the payload data to generate corresponding aggregate data (600). The aggregate data of each transmitter unit (20) is conveyed through the fiber link (30) to its associated receiver unit (40) which receives the aggregate data, decodes it to separate the payload data from the overhead data and then outputs the payload data to its associated receiving client. The receiver unit (40) interprets the overhead data and uses it for controlling and managing the payload data in the system (300).

Abstract: A demultiplexer, capable of extracting specific individual data from among packets in which the specific individual data is stored in predetermined units with a high efficiency, for A packet demultiplexer demultiplexes first to third packets and an extractor extracts additional information from the third pocket. The extractor has a first comparator for comparing control data in a harder region of the third packet and first comparison data based on mask data, and a second comparing comparator for comparing the control data and second comparison data based on the first comparison data and the mask data. The additional information is extracted from the third packet when the result of comparison of the first comparator indicates coincidence and result of comparison of the second comparator indicates noncoincidence.

Abstract: An electronic apparatus is used for synchronizing a data stream synchronized with a first clock signal with a second clock signal. It comprises a plurality of parallel latches wherein successive states of the data stream are written cyclically in synchronization with the first clock signal into the parallel latches and wherein the states written into the parallel latches in synchronization with the second clock signal are cyclically read. The apparatus also indicates the validity latch.

Abstract: A method and apparatus for bus repeater tapering. The sizing of repeaters on a portion of one transmission line is chosen to propagate a signal transition at a particular rate. The sizing of repeaters on a substantially parallel portion of another transmission line, is chosen to propagate a second signal transition at a different rate. Thus, the worst-case capacitance coupling factor between the two transmission lines may be reduced.

Abstract: An asynchronous sample rate converter interpolates and filters a digital audio input signal to produce a filtered, up-sampled first signal. A FIFO memory receives the first signal and stores samples thereof at locations determined by a write address and presents stored samples from locations determined by a read address. The presented samples are passed through an interpolation and resampling circuit to produce a continuous-time signal which is re-sampled to produce a signal that is up-sampled relative to a desired output. That signal then is filtered and down-sampled to produce the output signal. Sample rate estimating circuitry computes a difference signal representative of a time at which a data sample of the audio input signal is received and a time at which a corresponding audio output sample is required, and address generation circuitry generates the read and write addresses.

Abstract: Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.

Abstract: A system, method, and apparatus for a multiple data rate communication system is presented herein. The communication system receives data samples that are either sampled at a narrowband rate or a wideband rate and provides various functions and services, such as echo cancellation, DTMF detection and generation, and call discrimination. For wideband signals, a down-sampled signal is provided for each of the foregoing function and service. The output of the function or services is then recombined with the wideband signal.

Abstract: A data receiving circuit has a data input terminal, a conversion circuit converting an input signal received via the data input terminal, and a decision circuit making a decision on an output of the conversion circuit. The conversion circuit has a demultiplexer converting the input signal into a signal of a lower frequency than the frequency thereof at the data input terminal, and an output of the demultiplexer is obtained at the drain side of each of a plurality of first transistors having a common source.

Abstract: In a transmission system with a transmitter (4) coupled to a receiver (6) a main signal (SPEECH INPUT) encoded according to a coding property is transmitted together with an auxiliary signal (AUX).

Abstract: A method and apparatus for sample rate conversion in an analog to digital converter. Such a method and apparatus include processing that begins by receiving an input digital stream at a first clock rate from an oversampling quantizer (e.g., a sigma delta modulator). The processing continues by integrating the input digital stream over multiple clock cycles at the first clock rate to produce an integrated digital signal. The processing continues by determining when an interpolated digital value of the integrated digital signal is to be passed to a differentiation stage based on a difference between a sample rate conversion value and a reference value. The processing continues by, when the difference is within a targeted range (e.g.

Abstract: A video teleconferencing system uses digital transcoding to obtain algorithm transcoding, transmission rate matching, and spatial mixing. The video teleconferencing system comprises a multipoint control unit (MCU) for allowing multiple audiovisual terminals, which send and receive compressed digital data signals, to communicate with each other in a conference. The MCU has a video processing unit (VPU) that performs algorithm transcoding, rate matching, and spatial mixing among the terminals within a conference. The VPU includes a time division multiplex pixel bus and a plurality of processors. Each processor is assignable to an audiovisual terminal in the conference and is coupled to the pixel bus. In a receive mode, each processor receives and decodes compressed video signals from its assigned terminal and puts the decoded signal onto the pixel bus. In a transmit mode, each processor receives from the pixel bus uncompressed video signals from any terminal in the conference.

Abstract: In a transmission system with a transmitter coupled to a receiver a main signal encoded according to a coding property is transmitted together with an auxiliary signal (AUX). In order to transmit the auxiliary signal without needing additional space in the transmission frame, the auxiliary signal is transmitted by changing the coding property according to a predetermined sequence. This is done by means of the sequencer. In the receiver, the decoding of the predetermined sequence is performed by a decoder.

Abstract: Methods and apparatus for transmitting and receiving data using framing circuitry designed to generate data frames of a first duration at a first data rate. According to the invention, data frames are generated and decomposed at lower data rates than the rate for which the framing circuitry was originally designed, i.e., the first data rate. The framing circuitry is programmed to organize a data stream into a sequence of data frames of the first duration or to decompose such data frames into a data stream. According to the invention, such a sequence of data frames corresponds to a selected one of a plurality of equivalent data rates. Each of the equivalent data rates are lower than the first data rate.

Abstract: An apparatus comprising a first circuit, a deserializer circuit and a framer circuit. The first circuit may be configured to present a clock signal and a data signal having a second data rate in response to an input signal having a first data rate. The deserializer circuit may comprise (a) a parallel register bank configured to generate an output signal in response to (i) the clock signal, (ii) the data signal and (iii) one or more select signals and (b) a state machine configured to generate the one or more select signals in response to one or more control signals. The framer circuit may be configured to generate the one or more control signals in response to (i) one or more input control signals and (ii) the output signal.

Abstract: A SONET format signal transport system and method providing an increased transport capacity. The transport system includes multiple low speed transport systems wherein each low speed transport system can have a pair of low speed terminals connected by N working channels and one protection channel. A clear channel high speed SONET transport system is connected between the low speed transport systems. The clear channel high speed SONET transport system has N+1 working channels that each terminate at a high speed terminal. The low speed system protection channels are multiplexed into a protection channel of the clear channel high speed system, while each working channel of each individual low speed system is multiplexed into different high speed channels.

Abstract: A method and device for converting high rate serial data into low rate serial data are disclosed.

Abstract: A bridging device for mapping and demapping Ethernet data packets onto a SONET network includes an Ethernet controller chip set which receives packet data, a SONET framer for a SONET interface, a UTOPIA interface for the SONET framer, and an FPGA (or ASIC) which bridges the UTOPIA interface and a system bus interface of the Ethernet controller. The FPGA is preferably implemented in VHDL software code as several modules: an Ethernet controller interface module, a chunk memory module, a UTOPIA interface module, a microprocessor interface module, and a UTOPIA OUT module. In a transmit mode, the Ethernet controller interface module interfaces with the data and control signals from a thirty-two bit data bus of the Ethernet controller chip set and writes the data to chunk memory implemented in the FPGA. The chunk memory module implements the chunk memory to a programmable size.