Abstract: Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an asynchronous packet network; a plurality of configurable circuits arranged in an array, each configurable circuit coupled to the asynchronous packet network and adapted to perform a plurality of computations; and a dispatch interface circuit adapted to partition the plurality of configurable circuits into one or more separate partitions of configurable circuits and to load one or more computation kernels into each partition of configurable circuits. The dispatch interface circuit may load balance across the partitions of configurable circuits by starting threads for execution in the partition having the highest number of available thread identifiers. The dispatch interface may also assert a partition enable signal to merge the one or more separate partitions and assert a stop signal to all configurable circuits of the one or more separate partitions of configurable circuits.

Abstract: In a vectored Discrete Multi-Tone (DMT) system that employs trellis encoding, tones of a DMT signal are paired by a trellis encoder, and parity information is shared between the paired tones. In accordance with some embodiments, the tones are paired based on an interpolation pattern that is used to calculate vectoring coefficients in an effort to mitigate interpolation error. Specifically, a tone having a vectoring coefficient with a relatively large interpolation error may be paired with a tone having a vectoring coefficient with a relatively small interpolation error thereby reducing the peak interpolation error among paired tones within the system. By reducing the peak interpolation error in the paired tones, the number of communication lines included in a vectoring group can be increased without significantly degrading signal quality.

Abstract: Provided is a communication device, which is enabled to improve the throughput of a communication system by reducing the difference of a transmission power between an SCCH and an SDCH thereby to satisfy the required quality of a PAPR. In this device, an MCS selection unit (111) of a transmission unit (110) decides, with reference to a CQI lookup table, an MCS pattern (MCS1) of the SDCH, an MCS pattern (MCS2) of the SCCH and information (multiplex information) on multiplex positions on the time axes of those two channels, on the basis of the CQI information. On the basis of the MCS2 and the MCS1, encoding modulation units (112 and 113) perform encoding and modulating operations. According to the multiplex information, a channel multiplexing unit (114) time-division multiplexes the SCCH and the SDCH thereby to generate a transmission signal.

Abstract: Methods and systems for hybrid point to multipoint communication systems having multiple downlink channels and a single uplink channel, including the steps of centrally allocating bandwidth to, and synchronizing communications with, a first and a second wireless clients; transmitting, over a shared signal wired distribution line, a first downlink signal transported over a first frequency, a second downlink signal transported over a second frequency, and an uplink signal transported over a fifth frequency; converting the frequency of the first downlink signal to a third frequency, and bi-directionally wirelessly communicating with a first wireless client over the third frequency; converting the frequency of the second downlink signal to a fourth frequency, and bi-directionally wirelessly communicating with a second wireless client over the fourth frequency; and converting and superpositioning a first received wireless uplink signal having the third frequency and a second received wireless uplink signal having

Abstract: A hybrid network system and method is used for incrementally upgrading a gaming system from legacy equipment to broadband equipment while maintaining the capability to support the assets and functionality of both legacy gaming devices and networks and modern gaming devices and networks. The hybrid network system enables new gaming devices and networks to coexist in the same system as existing, legacy gaming devices and networks, and thereby upgrade components as resources and availability allow. The hybrid network system enables the addition of modern devices and networks having new capabilities while continuing to support legacy equipment that is currently in use.

Abstract: Methods, computer program products, electronic devices and information blocks are provided that improve both efficiency of transmission and efficiency of segmentation by enabling an intelligent transport block size determination and a flexible segmentation scheme suitable for utilization with retransmission. One exemplary method involves steps of: determining a size of a transport block based on criteria including a size of at least one data block to be transmitted, wherein the transport block size is determined such that the transport block will include at least one segment of a data block of the at least one data block; segmenting the data block of the at least one data block into a plurality of segments including the at least one segment; and populating the transport block with at least the at least one segment.

Abstract: Apparatus, methods and techniques for adjusting the phase offset used in sampling rate conversion uses a Farrow structure or the like to compensate for clock problems such as “clock jitter” and/or “clock drift” effects, which typically arise where one clock is truly independent of the other. A phase offset adjustment value ?? based on the measured data flow between clock domains across a transition interface and/or through a buffer is calculated. Where an output FIFO buffer is used, the measured data flow value represents the number of data words written to and read from the FIFO buffer, such as the current number of data words stored in the FIFO buffer or a counter value representing the net number of data words written to the FIFO buffer. The measured data flow value is compared to a target data flow value, which may be a range of values. The phase offset adjustment value may be updated and/or recalculated continuously and/or periodically and is added to or subtracted from the phase offset ? as necessary.

Abstract: Apparatus, methods and techniques for adjusting the phase offset used in sampling rate conversion uses a Farrow structure or the like to compensate for clock problems such as “clock jitter” and/or “clock drift” effects, which typically arise where one clock is truly independent of the other. A phase offset adjustment value ?? based on the measured data flow between clock domains across a transition interface and/or through a buffer is calculated. Where an output FIFO buffer is used, the measured data flow value represents the number of data words written to and read from the FIFO buffer, such as the current number of data words stored in the FIFO buffer or a counter value representing the net number of data words written to the FIFO buffer. The measured data flow value is compared to a target data flow value, which may be a range of values. The phase offset adjustment value may be updated and/or recalculated continuously and/or periodically and is added to or subtracted from the phase offset ? as necessary.

Abstract: Data processor emulation information that has been collected and arranged into a plurality of first information blocks during the collection process is re-arranged into a plurality of second information blocks which differ in size from the first information blocks. A sequence of the second information blocks is output from the data processor via a plurality of terminals thereof.

Abstract: In a variable rate wireless communication system, an explicit reduced-bit rate indicator is used to communicate the data rate and configuration of the transmission to the receiver. Data throughput is increased by reducing the number of bits required to indicate data rate and channel configuration. Related allocation of total transmit power, and related receive processing are conserved. Reception is enhanced by increased probability of correct decoding. Receiver performance is enhanced by reducing the probability of false erasures and associated outerloop setpoint adjustment errors when the receiver is notified of channels with zero data rates. Power consumption is reduced by using fewer bits to communicate data rate and channel configuration information, and by more accurate setpoint adjustment.

Abstract: An apparatus comprising a first circuit, a deserializer circuit and a framer circuit. The first circuit may be configured to present a clock signal and a data signal having a second data rate in response to an input signal having a first data rate. The deserializer circuit may comprise (a) a parallel register bank configured to generate an output signal in response to (i) the clock signal, (ii) the data signal and (iii) one or more select signals and (b) a state machine configured to generate the one or more select signals in response to one or more control signals. The framer circuit may be configured to generate the one or more control signals in response to (i) one or more input control signals and (ii) the output signal.

Abstract: The present invention includes a time-division-multiple-access (TDMA) communication system having a base station and at least one mobile station, each transmitting and receiving an analog radio-frequency signal carrying digitally coded speech. The speech is encoded using a vocoder which samples a voice signal at variable encoding rates. During periods when the radio-frequency channel is experiencing high levels of channel interference, the encoded voice channel having a lower encoding rate is chosen. This low-rate encoded voice is combined with the high degree of channel coding necessary to ensure reliable transmission. When the radio-frequency channel is experiencing low levels of channel interference, less channel coding is necessary and the vocoder having a higher encoding rate is used. The high-rate encoded voice is combined with the lower degree of channel coding necessary to ensure reliable transmission.

Abstract: A method and device for converting high rate serial data into low rate serial data are disclosed.

Abstract: The invention relates to an adapter (10) and a method for a communication card (20), preferably a PCMCIA card, comprising communication electronics by means of a host unit (18) I/O port. The adapter (10) automatically configures the communication card (20) and initiates an automatic connection to a connected host unit with the power supply on, so-called power on. Moreover, it transmits data transparently between the card (20) and the host unit (18) in perceiving changes in data speed and in data format.

Abstract: A novel and improved method and apparatus for generating a constant data rate channel supporting signaling data transmission in an adjustable rate wireless communication system is described. In accordance with one aspect of the invention the rate at which the channel operates may be adjusted based on the particular use and environmental conditions such that the appropriate data rate up to a maximum capability can be achieved. User data is then placed into frames based on the selected rate. When available, signaling data is added into each frames in a predetermined amount. The resulting frame is encoded, repeated and punctured based on the selected rate and whether signaling data has been introduced, and transmitted via RF signals to the receive system. Upon reception, the frame is processed in accordance with having only user data and with having signaling data. That is, the frame is processed both as if it had signaling data and as if no signaling data were present.

Abstract: A local subscriber loop architecture embeds digitized POTS signals into the framing format of high bit rate digital subscriber loop signals being transported over a local loop for serving both subscriber digital terminal equipment and a POTS telephone. The remote transceiver unit is line-powered from the central office unit, facilitating installation of a reliable (office-powered) POTS interface (containing codec and subscriber line interface circuitry providing BORSHT functions) into the remote unit. The data rate of the added digital POTS signal is relatively small with respect to the data rate of the DSL channels, so that there is only slight increase in the overall data rate. As a consequence, adding the digital POTS signal has negligible impact on transport range.

Abstract: A multi-rate transmission system (10) includes a receive section (12) and a transmit section (14). The receive section includes a receiver (16), a clock recovery unit (18), and a serial to parallel converter (20) all operating at a first clock rate (M). The receiver (16) also has a frame recovery unit (22) that operates at any of a plurality of clock rates, including the first clock rate (M) and a second clock rate (M/n). When the frame recovery unit operates at the first clock rate (M), frame information received by the receiver section (12) has unique bits occupying each bit position associated with each clock pulse of the first clock rate (M). When the frame recovery unit (22) operates at the second clock rate (M/n), each unique bit of the frame information occupies a number of bit positions according to a ratio of the first clock rate (M) to the second clock rate (M/n). Similar operation occurs with respect to a frame formatter (30) in the transmit section (14) of the multi-rate transmission system (10).

Abstract: A multi-channel transcoder with rate adapter converts the data rate of GSM and PSTN network data in a multi-channel network. A transcoder having echo-cancellation features uses the robust voice activity detection functions of the GSM transcoder functions to enhance the accuracy of echo-cancellation of near-end signals. A method for decoding a GSM signal in which the transmission of the audio data over the network is commenced prior to the completing of the decoding process. A transcoder unit having rate adaption and echo-cancellation with improved decoding is implemented in a single DSP and processes multiple traffic channels simultaneously.

Abstract: A transceiver (34) includes a rate adaptation buffer (74) that synchronizes a data stream received at a 4.0 kHz rate to a data stream that is transmitted at a 4.05 kHz rate. A transmit section (62) of the transceiver (34) performs rate adaptation using a single rate adaptation buffer. The transmit section (62) includes four autonomous modules which are able to access the data in the rate adaptation buffer (74) independently of one another. These four modules include a CRC-scrambler (72), a FEC encoder (76), an interleaver (78), and a constellation encoder (80). A timing controller (84) prevents contention for accesses to the rate adaptation buffer (74). In addition, each of the four modules perform their respective functions quickly enough to prevent overflow or underflow conditions in the rate adaptation buffer (74). A receive section (64) functions similarly to the transmit section (62).

Abstract: A 1:N divider 40 divides an input high rate data signal into N (N being 2 or greater integer) division data signals. Data transmission rate converters 70.sub.1 -70.sub.N for converting the transmission rate of each of the N division data signals. The respective N division data signals are transmitted through N transmission lines 30.sub.1 -30.sub.n. A multiplier 50 multiplies the transmitted N division data signals into a single high rate data signal.