Abstract: A device is disclosed for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal. The device comprises a merging unit (4′) for merging a 1-bit merging word at equidistant positions in the serial datastream of the binary source signal, so as to obtain a composite binary source signal. A shuffling step is carried out on the composite binary source signal in a shuffling unit (8′). Next a conversion is carried out in a converter unit (10′), resulting in the channel signal (FIG. 2). Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.

Abstract: A pulse-density modulator (10) for producing a pulse density output signal on an output line (36) representing successive parallel digital input words on input terminals (12) has a plurality of full adders (14, 16, 18), each having a carry output (C), and an input (A) for receiving a respective bit of a concurrently applied bit of the parallel input digital words. The overflow output (C) of each of the adders (14, 16, 18) is added as an input (B) of an adder of a next successively higher bit order. A latch (30) receives the carry output (C) of one of the adders (14) in a most significant bit position, with an output of the latch provides a pulse density modulated signal on an output line (36) representing the input digital words. A clock (35) applies clock pulses to the latches (20, 22, 24, 30) at a frequency at least as high as the frequency at which the successive parallel digital input words are applied to the inputs (12) of the adders (14, 16, 18).

Abstract: A sensor device includes a voltage-to-pulse-number converter having a timing controller. When power is supplied to the converter from a power circuit through a power line, a timer circuit inhibits itself from performing a control operation until operations of a sensor and an amplifier become stable. After a predetermined period of time has passed, the inhibition of the controls is canceled. Then, an analog-to-digital (A-D) conversion of an output of the amplifier by the A-D converter is performed. Subsequently, a counter counts down from a value obtained from the A-D conversion. When the output of the counter becomes 0, the operation of the counter is stopped. Clock signals used for the operation of the counter are input to the pulse output circuit which is enabled only when the counter operates. Thereby, the timing controller outputs to an event counter a pulse signal having a number of pulses proportional to an output of the sensor. The sensor device obtains high precision data.

Abstract: A pulse density signaling input/output (PDSIO) scheme is implemented to provide a two-way, two-wire hybrid analog/digital communications system. PDSIO signals are sent as logic pulses from a "master" port to one or more "slave" ports over a twisted pair. From one to a predetermined maximum number of logic pulses are transmitted over two wires at baseband by a master port during a defined period. The modulation used by the master port is pulse density modulation at base band so that the transmitted signal appears to be a d.c. logic signal. The pulses transmitted to the slave port are also used to power the slave port. The slave port communicates with the master port over the same two wires using a pulsed current modulation that multiplexes data on the pulse signals from the master port.

Abstract: This contribution involves the generation, transmission, propagation and selective reception of electrical, magnetic or electromagnetic energy in the form of a halfwave sinusoidal pulse signal, from one location to another, whereby intelligence input for transmission is recovered from one sinusoidal pulse, or from a plurality of sinusoidal pulses. In a transmitter embodiment, one or more sinusoidal halfwave pulse generators are provided, where each pulse signal may be generated asynchronously, with varying polarity, duration and amplitude on a continuous serial sampled information basis. Complementary pulse signal filtering and recovering of transmitted intelligence is provided in a signal receiver embodiment. Another transmitter embodiment includes a software-driven signal synthesizing capability, wherein a plurality of timed sinusoidal halfways pulses are linearly summed as elementary signal components of an information-carrying propagable signal.

Abstract: A binary code is divided into 2-bit data units. Pulse position modulation is performed on each unit rather than on each bit. Since a pulse is not formed for each bit, the transmission interval and transmission frame interval for the modulated signal is shortened, thus enabling high speed transmission. Since the pulse interval of the signal contains the information of the 2-bit data unit, only the leading edge of the pulse needs to be detected. This feature allows reliable demodulation even under adverse conditions such as a long-distance transmission route or a noisy transmission route. Since there is no need to demodulate by comparing each bit with an immediately preceding bit, complex demodulation schemes and decoding registers are not needed on the receiving side. Since the width of the pulse does not contain any transmission information, the pulse width is made as short as possible, thereby reducing battery consumption within the transmitter.

Abstract: Biphase or FM encoding is combined with Flash modulation in infrared (IR) communication. By shrinking the coded pulse width in the modulation process, power dissipation is effectively reduced to the point where FM encoding can be advantageously adapted to IR communication in a synchronous communication system. Noise filtering is also described.

Abstract: A transmitted data stream in a remote control system is a serial data stream having a synchronization sequence and a data sequence. The data sequence is encoded into a symbol comprised of a series of data bits wherein a 110 may represent a logic 1 and a 011 may represent a logic 0. A self adaptive filter adjusts its gain and offset to determine the duration of one bit. Providing a serial code format wherein the synchronization sequence has a smiller duty cycle as the duty cycle of a symbol aids the self adaptive filter to set its threshold switching level accurately and quickly, thus aiding the receiver to decode the transmitted data stream.

Abstract: A method and circuit arrangement for a single-wire bus system wherein a commercially available processor reads data from a transmitter. The transfer of the data over a single-wire line is controlled exclusively by the processor. The processor generates a pulse sequence on the single-wire line that is stopped by the transmitter after attainment of a predetermined number (N) of pulses by locking the single-wire line at a predetermined voltage level.