Abstract: The multilevel data encoding and modulation technique uses a pair of complementary logic sets. In its most basic form, the sets are binary sets each containing a line level for a logical one and a line level for a logical zero for a total of four logic levels. The encoding technique requires a polar change in the line level after every bit. An optional fifth level may be used in order to skew the frequency or to enable automatic gain control circuitry to ensure consistent level discrimination. The encoding technique may be used in a bipolar device, or a bias level may be applied to the signal for unipolar transmission. The encoding technique involves inverting the polarity of alternating bits, filtering out all odd harmonics, transmitting and receiving the waveform, and decoding the demodulated waveform by comparing the absolute value of the half-cycle peak-to-peak voltage gain to a predetermined table.

Abstract: A variable-length encoding apparatus capable of encoding two data groups in parallel, and a method and computer program for the same. A first encoding unit and a second encoding unit execute variable-length encoding in parallel. In order to concatenate first variable-length encoding data output from the first encoding unit and second variable-length encoding data output from the second encoding unit, the second variable-length encoding data is shifted by the number of bits of the first variable-length encoding data.

Abstract: A desired bit sequence (x) can be communicated over a wireless communication link (15) by including the desired bit sequence in each of a plurality of transmissions over the wireless communication link. In response to each of the plurality of transmissions, a received bit sequence corresponding to the desired bit sequence can be produced at the receiving end. A determination of the desired bit sequence can be made based on the received bit sequences (r1–rN) and information (SNR1–SNRN, ?1–?N) indicative of communication quality associated with each of the plurality of transmissions.

Abstract: A code rate adaptive encoding/decoding arrangement and method for a pulse code modulation system comprises a code rate adaptor and a code capacity meter to dynamically produce a code rate adaptive signal for the code length of the pulse code modulation adaptive to actual situations during the encoding/decoding process.

Abstract: A method and apparatus for modulating data modulates data having a length of m-bits to a variable length code having a basic code length of n-bits. A SYNC bit inserting section adds a sync signal to a train of codes, after a minimum run. The sync signal has a pattern that breaks a maximum run.

Abstract: An apparatus and method for modulating and demodulating data to transmit or record the data on a recoding medium. Data is modulated and demodulated into a variable-length code. The modulated data comprises a sync signal adding means for adding a sync signal to a train of codes after adding a minimum run. The demodulated data comprises a sync signal detecting means for detecting, from a train of codes, a sync signal having a pattern that breaks a maximum run, after detecting a minimum run. A SYNC bit inserting section adds a sync signal to a train of codes, after adding a minimum run, where the sync signal has a pattern that breaks a maximum run.

Abstract: The present invention relates to a method of inserting sync patterns of different lengths in modulated data, and a recording medium having sync patterns produced by the method. The sector sync and the frame sync pattern to be inserted in modulated data in accordance with the present invention must satisfy the given (d,k) constraints, have distinctive 0's run the modulated channel data can not have, and be as short as it can. In addition, the frame sync pattern is shorter than the sector sync pattern because the frame sync pattern is more frequently inserted than the sector one. Owing to the present sync patterns, the storage capacity reduction of a recording medium due to necessary insertion of sync patterns can be minimized under a given modulation condition.

Abstract: How to record and play back data at a high line density. A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit.

Abstract: A DSV control bit determining/inserting unit inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit. This modulation unit converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit. The conversion table used by the modulation unit includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remaineder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.

Abstract: A data-demodulating method for demodulating a variable-length code (d, k; m, n; r) having a basic code length of n bits to data having a basic data length of m bits. A train of codes is received, and a sync signal having a pattern that breaks a maximum run is detected. The pattern is repeated twice continuously and the minimum run is repeated no more than six times. The first bit of the sync signal is “1” when the train of modulated codes that immediately precedes the sync signal is included in a termination table used to terminate, at a desired position, a code when less than a predetermined number of variable length codes are available.

Abstract: A method of modulating data having a basic data length of m bits, to a variable-length code (d, k; m, n; r) having a basic code length of n bits. A sync signal is added to a received train of codes after a minimum run. The sync signal has a pattern that is repeated twice continuously. The minimum run is repeated no more than six times; and the sync signal exhibits seven types of sync signal IDs, with any adjacent two bits of a sync signal ID being spaced apart by a distance of 2.

Abstract: A data-demodulating apparatus for demodulating a variable-length code (d, k; m, n; r) having a basic code length of n bits to data having a basic data length of m bits. A train of codes is received, and a sync signal having a pattern that breaks a maximum run is detected. The pattern is repeated twice continuously and the minimum run is repeated no more than six times. The first bit of the sync signal is “1” when the train of modulated codes that immediately precedes the sync signal is included in a termination table used to terminate, at a desired position, a code when less than a predetermined number of variable length codes are available.

Abstract: Apparatus for modulating data having a basic data length of m bits, to a variable-length code (d, k; m, n; r) having a basic code length of n bits. A sync signal is added to a received train of codes after a minimum run. The sync signal has a pattern that is repeated twice continuously. The minimum run is repeated no more than six times; and the sync signal exhibits seven types of sync signal IDs, with any adjacent two bits of a sync signal ID being spaced apart by a distance of 2.

Abstract: A digital sum variation (DSV) computation method and system is proposed, which is capable of determining the DSV value of a bit stream of channel-bit symbols to thereby find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols. This DSV computation method and system is characterized in the use of a Zero Digital Sum Variation (ZDSV) principle to determine the DSV. This DSV computation method and system can find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols in a more cost-effective manner with the need for a reduced amount of memory and utilizes a lookup table requiring a reduced amount of memory space for storage so that memory space can be reduced as compared to the prior art. This DSV computation method and system is therefore more advantageous to use than the prior art.

Abstract: Coding a data stream is provided, wherein the data stream comprises at least one packet having a given packet length and respective partitions of the at least one packet are coded with different error protection rates, the respective lengths of the respective partitions being determined by respective predetermined percentages of the packet length or a fraction of the packet length.

Abstract: A data transmission method etc. are provided. At the transmitting side, an error-detecting code of the transmitted data is calculated, frame by frame, the error-detecting code is arranged after the corresponding transmitted data, and frame data is generated in such a way that bit arrangements of the transmitted data and of the error-detecting code are set in a reverse order to each other. At the receiving side, the transmitted data and the error-detecting code are assumed by assuming a final bit position of the frame data, frame by frame, for the received frame data and the error-detecting code of the assumed transmitted data is calculated. A position such where the assumed error-detecting code agrees with an error-detecting code calculated on the basis of the assumed transmitted data is determined to be the final bit position of the frame data.

Abstract: A communication system for performing transmission and reception of a signal over a communication channel assesses a state of the communication channel and produces channel state information accordingly. A block length selector selects block lengths that are dependent on the channel state information and that are selected from a group of block lengths having an integral multiple relationship to produce a schedule of block lengths. Encoding and decoding is performed based on the schedule of block lengths.

Abstract: The present invention relates to a method for coding a data stream, in which the digital sum value of the coded data stream should be close to zero and two alternative code words can be used for the coding at least for some of the possible data values. It is the object of the invention to propose a method for coding a data stream which provides for simple coding of the data stream while at the same time ensuring a digital sum value close to zero. According to the invention, the object is achieved by a method in which the digital sum value of the coded data stream is determined, this value is compared with a first or a second boundary value in dependence on the polarity of the coded data stream and a received data value is coded by a first or a second code word belonging to the respective boundary value in dependence on the result of the comparison.

Abstract: A data-modulating apparatus for modulating data having a basic data length of m bits, to a variable-length code(d, k; m, n: r) having a basic code length of n bits. A sync signal is added to a recieved train of codes after a minimum run, the sync signal having a pattern that breaks a maximum run. The pattern is repeated twice continuously, and the minimum run is repeated no more than six times. The first bit of the sync signal is “1” when the train of modulated codes that immediately precedes the sync signal is included in the termination table used to terminate, at a desired position, a code when less than a predetermined number of variable length codes are available.

Abstract: The present embodiments address the need for an apparatus and method that provides additional orthogonal codes without trading off RF capacity. When a system is operating near its RF capacity and running out of available orthogonal codes, one or more channels are allocated using a new radio configuration (510) that utilizes longer orthogonal codes. This new radio configuration increases the number of available orthogonal codes without sacrificing RF capacity. Instead, it reduces the peak data rate such a channel can provide.

Abstract: A demapping system and method for demapping symbols into bits, is provided. An embodiment of the system comprises a processor, and a memory that is coupled to the processor. The memory comprises a memory module that comprises a program that finds a hard demapper output d based on a received symbol r; finds a challenger ci for each i, the challenger ci is a challenger of the hard demapper output d, i is an integer whose maximum value is a number of bits of the challenger ci; calculates reliability mi for each i, the reliability mi is the reliability of the hard demapper output d; and calculates soft bit xi for each i, the soft bit xi is calculated based on the reliability mi.

Abstract: A method and apparatus for modulating data modulates data having a length of m-bits to a variable length code having a basic code length of n-bits. A SYNC but insertion section adds a sync signal to a train of codes, after a minimum run. The sync signal has a pattern that breaks a maximum run.

Abstract: A digital sum variation (DSV) computation method and system is proposed, which is capable of determining the DSV value of a bit stream of channel-bit symbols to thereby find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols. This DSV computation method and system is characterized in the use of a Zero Digital Sum Variation (ZDSV) principle to determine the DSV. This DSV computation method and system can find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols in a more cost-effective manner with the need for a reduced amount of memory and utilizes a lookup table requiring a reduced amount of memory space for storage so that memory space can be reduced as compared to the prior art. This DSV computation method and system is therefore more advantageous to use than the prior art.

Abstract: With audio data reduction on the basis of ISO/IEC standard 11172-3, a frame length varying by 8 bits is used at a sampling frequency of 44.1 kHz in order to arrive, on average, at a particular fixed data rate. The lengthening of a data frame is signalled by a padding bit in the header of the frames. The invention dispenses with evaluation of the padding bit. Instead, the mean frame length L is calculated, L is rounded down to the next integer, for the subsequent frame it is first established whether the expected sync word for this frame appears, and, if this is so, this frame is decoded without taking into account the padding bit, but if the expected sync word for this frame does not appear, the decoding of the frame is started one 8-bit later without taking into account the padding bit.

Abstract: The present invention relates to method and apparatus of converting a series of data words into modulated signals. This method divides a data word, which a sync signal is to be added in front or rear of when it is written in a recording medium, into two or more word segments, generates for each word segment a number of intermediate sequences by combining mutually different digital words with that word segment, scrambles these intermediate sequences to form alternative sequences, translates each alternative sequence into a (d, k) constrained sequence, checks how many undesired sub-sequences are contained in each (d, k) constrained sequence, and selects one (d, k) constrained sequence for recording on an optical or magneto-optical recording medium among the (d, k) constrained sequences not having the undesired sub-sequence. Applying this method to a modulating device, DSV control can be conducted by much simpler hardware.

Abstract: The present invention provides a computationally efficient technique for compression encoding of an audio signal, and further provides a technique to enhance the sound quality of the encoded audio signal. This is accomplished by including more accurate attack detection and a computationally efficient quantization technique. The improved audio coder converts the input audio signal to a digital audio signal. The audio coder then divides the digital audio signal into larger frames having a long-block frame length and partitions each of the frames into multiple short-blocks. The audio coder then computes short-block audio signal characteristics for each of the partitioned short-blocks based on changes in the input audio signal.

Abstract: Several code detectors in parallel simultaneously examine varying overlapping segments of a data stream containing variable length codes, referred to as a data window. The data window segments directly address memory structures within each of the code detectors without any previous logic stages. Each code detector is responsible for a range of code lengths, and ignores data window bits that are not relevant to its code length range. Each code detector outputs a possible result to a layer of logic that selects the possible result of the single code detector which contains result data corresponding to a variable length code in the data window.

Abstract: A data bus arrangement and method for connecting a plurality of nodes to one another through a star coupler arrangement of a data bus which uses a logical decision gate having a plurality of inputs corresponding to said plurality of nodes wherein the logical decision gate inputs receive electrical signals and outputs an electrical signal to be routed back to each of said plurality of nodes. Some of the nodes are connected through opt0-electric transducers to the inputs of the logical decision gate. These transducers convert optical input signals from the nodes to electric signals to the inputs of the logical decision gate and also convert the output from the logical decision gate back to optical signals to the nodes. A signal conditioning circuit modifies the output signal of the logical decision gate.

Abstract: A dc-free coding scheme that also provides channel gain employs a code that is based on an alphabet of two and comprises a list of N-dimensional vectors, where N is even, with a maximum run of two symbols. From this list, all vectors which begin or end in two identical symbols are eliminated. This avoids runs of longer than two consecutive symbols when vectors are concatenated. With this scheme, if the baseband transmission of a “+” is realized with positive voltage V and transmission of a “−” is realized with a negative voltage −V, then any concatenation of symbols is dc-free. Improved coding gain is realized by mapping modulated signals onto convolutional code trellises.

Abstract: A method and apparatus for encoding and decoding data. A primary data channel comprising a parallel data word has a bit of a secondary data channel associated with the parallel data word. ECC bits are generated based upon the parallel data word and the monitor bit and the ECC bits are appended to the data comprising the primary and secondary channel data to form an extended width parallel word. The extended width parallel data word is divided into a plurality of lesser width data words which are each scrambled using respective side scrambler for form respective cipher data words. An ECC control bit and a parity bit is generated for each channel, and associated with the cipher data words to form extended cipher data words. The cipher data words are serialized and transmitted over a serial link. The received serial data is deserialized, word framed and word aligned across the respective channels, and descrambled to obtain the data contained in the primary and secondary data channels.

Abstract: A variable-length encode/decode processor includes a central processing unit and an instruction buffer and a getbits processing engine coupled to the central processing unit. Such a processor can be used to encode data as variable-length symbols or to decode variable-length symbols such as those found in an MPEG bitstream.

Abstract: In order to transmit variable length encoded data in low signal to noise ratio environments, a first data pattern is added to a beginning portion of encoded data to signify a beginning of the encoded data. Further, a second data pattern is added to end portion of the encoded data to signify and end of the encoded data. Additionally, since the encoded data may naturally include the second data pattern and thereby mistakenly indicate an end of the encoded data, the encoded data is first checked for such a pattern. If the pattern is found within the encoded data, a new pattern is substituted therefore. In order to counter errors, patterns similar to the first data pattern are also substituted with new patterns. As such, a variable length encoded data can be transmitted in a low signal to noise ratio environment, and can thereafter be easily decoded.

Abstract: Encoding tables are accorded with variable-length encoding rules using a variable constraint length. A DSV control bit is periodically inserted into a first input bit stream to generate a second input bit stream. Every m-bit piece of the second input bit stream is encoded into an n-bit output signal forming at least a portion of an output code word by referring to the encoding tables. Thereby, the second input bit stream is converted into a first output bit stream composed of output code words and observing RLL (d, k). A sync word is inserted into the first output bit stream for every frame to generate a second output bit stream. A frame-end output code word is terminated at a position before a next-frame sync word. DSV control of the second output bit stream is implemented in response to the inserted DSV control bits.

Abstract: Items of additional bits 1, 2 are input to right shifters (503, 501), respectively, whereby the data is shifted rightward by numbers of bits corresponding to variable-length code-word lengths that enter from variable-length encoding tables (504, 501), respectively. The additional bits that has been shifted rightward is input to OR gates (508, 510), respectively. The OR gates (508, 510) obtain the ORs between the shifted data and variable-length codes words 1, 2 that enter from variable-length encoding tables (504, 501), respectively. The output of the OR gate (510) is input to a right shifter (511), the other input to which is a number of bits measured by a code-length measurement unit (530) (the number of bits is the number of bits of the code length of variable-length code word 1 plus the number of bits of the additional bits 1). A shifter (511) shifts the output of the OR gate (510) rightward by the number of bits measured.

Abstract: How to record and play back data at a high line density. A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit.

Abstract: A method of providing time tracking between a first signal and a second signal in a communication device. In one embodiment, a first signal is generated by the communication device and a second signal is received from an outside source. Then correlation data between a first signal, at a plurality of timing conditions, and a second signal is generated by hardware. Next, the correlation data is filtered by software or firmware at a plurality of timing conditions. Afterward, the correlation data is compared to a threshold value to evaluate accuracy of a system timing for the first signal to obtain a result. Finally, the system timing for the first signal is corrected based upon said result of the comparing step.

Abstract: A digital modulation method in which at a head of an input block (pre-translation), each of a plurality of different types of initial data of t bits is multiplexed to generate a plurality of different types of multiplexed blocks, t bits at the head and immediately following t bits of each of the multiplexed blocks are subjected to exclusive OR operation, the immediately following t bits are replaced by the result of operation, the replaced t bits and the immediately following t bits are subjected to an exclusive OR operation, and the immediately following t bits are replaced by the result of operation, and thereafter in the similar manner, a convolution operation is executed. A plurality of different types of translated blocks are produced by the convolution operation, and DC components of thus provided translated blocks are calculated, respectively, absolute values of the respective DC components are compared with each other, and a translated block having the minimum value is selected and output externally.

Abstract: An input digital audio signal is divided into sub-band signals in respective sub-bands. Scale factors of the respective sub-bands are determined on the basis of the sub-band signals for every frame. Calculation is made as to differences between the determined scale factors for a first frame and the determined scale factors for a second frame preceding the first frame. Absolute values of the calculated scale-factor differences are calculated, and data representative of the calculated absolute values are generated. The data representative of the calculated absolute values are encoded into data of a Huffman code. Sign bits are generated which represent signs of the calculated scale-factor differences. The sub-band signals are quantized in response to the determined scale factors for every frame to generate quantized samples of the sub-band signals. The Huffman-code data, the generated sign bits, and the quantized samples of the sub-band signals are combined into a bit stream.

Abstract: A serial data receiver receives a serial data including first data defined as a judgment data indicative of at least one of a data reception rate and a reception data length. A shift register receives the serial data. The first data of the serial data received by the shift register is decoded by a decoder. The decoded result of the decoder is stored in a state register. A control circuit determines at least one of a data reception rate and a reception data length for the reception of the second and subsequent data of the serial data by the shift register based on the decoded result stored in the state register.

Abstract: A method and apparatus of converting a series of data words into modulated signals are provided. This method generates for each data word a number of intermediate sequences by combining mutually different digital words with that data word, scrambles these intermediate sequences to form alternative sequences, translates each alternative sequence into a (d,k) constrained sequence, checks whether each (d,k) constrained sequence contains undesired sub-sequence of more than kSET “0”s where kSET is smaller than k, and selects one (d,k) constrained sequence for recording on an optical or magneto-optical recording medium among the (d,k) constrained sequences not having the undesired sub-sequence, thereby recording edge information more frequently which will result in stable clock while conducting DSV control normally.

Abstract: Systems and methods for transcoding a video stream. An incoming video stream is spatially transcoded to reduce the bit rate of the video stream. The incoming video stream is decoded and the stream parameters are saved for use in generating the output video stream. The decoded video stream is resampled and the images are spatially reduced. Using the stream parameters of the incoming video stream, an outgoing video stream is generated. Some of the stream parameters are unchanged while others are re-computed for the outgoing video stream.

Abstract: Encoding tables are accorded with variable-length encoding rules using a variable constraint length. A DSV control bit is periodically inserted into a first input bit stream to generate a second input bit stream. Every m-bit piece of the second input bit stream is encoded into an n-bit output signal forming at least a portion of an output code word by referring to the encoding tables. Thereby, the second input bit stream is converted into a first output bit stream composed of output code words and observing RLL (d, k). A sync word is inserted into the first output bit stream for every frame to generate a second output bit stream. A frame-end output code word is terminated at a position before a next-frame sync word. DSV control of the second output bit stream is implemented in response to the inserted DSV control bits.

Abstract: A method of data transmission according to one embodiment of the invention includes encoding a set of data values to produce a corresponding series of ordered n-tuples. The method also includes transmitting, according to the series of ordered n-tuples, a plurality of bursts over a plurality n of frequency bands. Specifically, for each of the plurality of bursts, a frequency band occupied by the burst is indicated by the order within its n-tuple of an element corresponding to the burst. A bandwidth of at least one of the plurality of bursts is at least two percent of the center frequency of the burst.

Abstract: In order to transmit variable length encoded data in low signal to noise ratio environments, a first data pattern is added to a beginning portion of encoded data to signify a beginning of the encoded data. Further, a second data pattern is added to end portion of the encoded data to signify and end of the encoded data. Additionally, since the encoded data may naturally include the second data pattern and thereby mistakenly indicate an end of the encoded data, the encoded data is first checked for such a pattern. If the pattern is found within the encoded data, a new pattern is substituted therefore. In order to counter errors, patterns similar to the first data pattern are also substituted with new patterns. As such, a variable length encoded data can be transmitted in a low signal to noise ratio environment, and can thereafter be easily decoded.

Abstract: A method and apparatus for producing a variable rate precoded signal are presented in which a variable rate encoder receives a rate control signal and a data signal and generates a constellation size signal and data symbols. The data symbols and constellation size signal can be used by a precoder to produce a variable rate precoded signal. The precoder can be a Tomlinson/Harashima-Miyakawa precoder which uses the constellation size signal as part of the quantization process. The system can also be used to generate a variable rate modulation encoded signal. The invention provides the ability to create a variable rate signal which can be precoded and to which error correcting codes can be readily applied.

Abstract: A method includes a data encoding scheme that has a run length limit of (1,6) and a 25% duty cycle. With error correction, the method achieves an effective run length limit of (2,9). The method can be used in conjunction with a packetized communication protocol to allow multiple controllers to communicate with multiple peripheral devices in a wireless data network. Peripheral devices include pointing devices, keyboards and game pads.

Abstract: The invention relates to a method of encoding a digital signal, to a receiver and to a transmitter comprising means (308) for encoding symbols, comprised of bits, in blocks of a given length, means (308) for encoding each block into a given number of channel symbols to be transmitted over several separate channels, and at least three transmit antenna paths (314 to 318) for transmitting the channel symbols. In the solution of the invention, the transmitter comprises means (304, 208) for converting the symbols into a form in which the sum energy of channel symbols mapping at least one symbol in a block is higher than the sum energy of channel symbols mapping another symbol in the block.

Abstract: A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number.

Abstract: A processing circuit of bit modeling simultaneously generates contexts and decisions which change according to a state of significance flags of a bit to be processed and ambient bit group and a state of a sign bit with a sig pass, adopts the context and the decision of the sign bit only when a value of the bit to be processed is 1 so as to update the significance flag, disposes of the context and the decision when the value of the bit to be processed is 0, and updates the processed flag whether the value of the bit to be processed is 1 or 0. The processing circuit is simultaneously applied to bits O0 to O3 in one group so as to process the bits in parallel.

Abstract: A DSV control bit determining/inserting unit inserts DSV control bits into an input data string and outputs the string including the DSV control bits to a modulation unit which converts the string with basic data length of 2 bits into variable length code with basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit. The conversion table includes substitution codes for limiting the number of consecutive appearances of a minimum run and substitution codes for keeping a run length limit. The conversion table enforces a conversion rule: the remainder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 equals the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.