Abstract: A time-to-digital converter (TDC) circuit includes phase error calculation circuitry to: determine phase error values based on a time difference between a input reference clock and a feedback clock of a digital phase-locked loop (DPLL) circuit, the input reference clock and the feedback clock being unsynchronized; and provide the phase error values to a digital loop filter (DLF) of the DPLL circuit. The TDC circuit further includes clock generation circuitry to: generate a filter clock that asserts a clock pulse in response to detecting each last-received pulse of the input reference clock and the feedback clock; and provide the filter clock to the DLF concurrently with providing the phase error values to the DLF that are synchronized to the filter clock.

Abstract: A technology is described for a repeater. A repeater can comprise: a server port; a donor port; a first uplink (UL) amplification and filtering path coupled between the server port and the donor port, wherein the UL amplification and filtering path is configured to pass a UL signal of a first band and a UL signal of a second band through a first bandpass filter; a first downlink (DL) amplification and filtering path coupled between the server port and the donor port, wherein the first DL amplification and filtering path is configured to pass a DL signal of the first band and a DL signal of a third band through a second bandpass filter.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit an indication associated with phase noise characteristics of the UE. The UE may receive an indication of pilot allocation sizes, for different data modulation and coding schemes (MCSs) for communications, of frequency-domain contiguous pilots for phase noise mitigation based at least in part on the indication associated with the phase noise characteristics of the UE. Numerous other aspects are described.

Abstract: Systems and methods for managing a network are disclosed. One method can comprise determining signal information relating to a first network device such as an access point. The signal information may be associated with signal characteristics such as a radio frequency signal strength over a communication channel. An attenuation value for one or more receiving paths of the first network device may be determined using the signal information. The one or more receiving paths of the first network device may be attenuated based on the determined attenuation value. A transmission power of the first network device may be configured based on the determined attenuation value.

Abstract: A time-to-digital converter (TDC) circuit includes phase error calculation circuitry to: determine phase error values based on a time difference between a input reference clock and a feedback clock of a digital phase-locked loop (DPLL) circuit, the input reference clock and the feedback clock being unsynchronized; and provide the phase error values to a digital loop filter (DLF) of the DPLL circuit. The TDC circuit further includes clock generation circuitry to: generate a filter clock that asserts a clock pulse in response to detecting each last-received pulse of the input reference clock and the feedback clock; and provide the filter clock to the DLF concurrently with providing the phase error values to the DLF that are synchronized to the filter clock.

Abstract: An apparatus including a handshake window enabler having a pair of differential inputs and a window enablement output, a common mode detector coupled to a power input and a ground input and having a handshake inhibit output, and a handshake disabler coupled to the handshake window enabler, the common mode detector, and the pair of differential inputs. If a common mode voltage that out of range (“too high”) is detected, high speed handshake protocols are such that the bus operates a lower data rate.

Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A method of operating a base station in a wireless communications network, the base station being arranged to communicate with a mobile terminal to provide on-demand System Information, SI.

Abstract: In a closed-loop wireless communication system, a codebook-based feedback mechanism is provided to enable non-unitary precoding for multi-stream transmission, where in each stream is optimized with suitable transmission power allocation and AMC. The codebook-based feedback mechanism uses a precoding codebook having a power allocation matrix which is constrained to specify that beamforming always applies full power to a predetermined beam. With this constraint, a one-bit power allocation feedback index may be used to switch between beamforming and spatial multiplexing.

Abstract: Systems and methods for transpositional modulation and demodulation are provided. One such method for generating a signal includes the steps of providing a look-up table having a plurality of quarter-cycle waveforms, each of said quarter-cycle waveforms associated with a respective input level; receiving an input signal; and outputting quarter-cycle waveforms associated with levels of the received input signal. Systems for transpositional modulation are also provided. One such system for generating a signal includes a look-up table having a plurality of quarter-cycle waveforms. Each of the quarter-cycle waveforms are associated with a respective input level, and the look-up table is configured to receive an input signal, and output quarter-cycle waveforms associated with levels of the received input signal.

Abstract: In order to compensate for phase offset between different sets of circuitry having different synchronous clock domains, transmit (TX) circuitry of one domain is configured to transmit a pattern signal (e.g., a pseudo random bit sequence) to receive (RX) circuitry of the other domain. The RX circuitry cycles through a number of different phase-shifted RX clock signals to determine which selected clock signals result in valid RX pattern signals. The RX circuitry is then able to select one of the phase-shifted clock signals for use in normal processing of an RX data signal received from the TX circuitry.

Abstract: A method and apparatus for reducing the contribution of noise to digitally sampled signals includes a statistical processor and a slope limiter. The statistical processor determines an average value (mean and/or standard deviation) of the filtered signal which is used to determine a slope limit corresponding to an expected maximum first derivative value of a target signal frequency. This slope limit is applied to constrain the output of an analog to digital converter, to prevent the output of the analog to digital converter from exceeding this maximum rate of rise or fall. By constraining the output of the analog to digital converter, it is possible to digitally sample analog signals without first utilizing an anti-aliasing filter, since the post processing of the digitally sampled signals limits the contribution of the higher frequency components of the signal to thereby enable a fully digital sampling and filtering circuit to be provided for receiving signals.

Abstract: The present invention relates to methods and an apparatus for estimating a residual frequency error. According to an embodiment, an expected vector for selected subcarriers of a received symbol is estimated using a channel estimate vector and a reference vector; a sampling frequency mismatch is removed and a dot product is calculated using the expected and a received vector. An angle of the product is estimated and a change in angle from a previous symbol is calculated. The residual frequency is estimated using the calculated change in angle. In another embodiment, an expected subcarrier is estimated based on a channel estimate and on a reference subcarrier, an angle and magnitude of the multiplication between the expected and a received subcarrier are estimated; a phase offset is removed; a weighted mean value of the angles is calculated and the residual frequency error is estimated using a change in weighted mean angle.

Abstract: A method for determining temporary Base Station (BS) Identifiers (IDs) to efficiently set a multi-BS Multiple Input Multiple Output (MIMO) transmission mode and an apparatus for implementing the same in a broadband wireless access system are disclosed. To perform a multi-BS MIMO operation, a Mobile Station (MS) receives a first broadcast message including system information about a plurality of neighbor BSs from a serving BS, receives a second broadcast message including BS set information from the serving BS, the BS set information specifying indexes of one or more neighbor BSs which can be involved in the multi-BS MIMO operation among the plurality of neighbor BSs, and determines a temporary BS ID of each BS included in the BS set information using the specified indexes.

Abstract: One embodiment relates to an integrated circuit which includes a transmitter buffer circuit, a duty cycle distortion (DCD) detector, correction logic, and a duty cycle adjuster. The DCD detector is configured to selectively couple to the serial output of the transmitter buffer circuit. The correction logic is configured to generate control signals based on the output of the DCD detector. The duty cycle adjuster is configured to adjust a duty cycle of the serial input signal based on the control signals. Another embodiment relates to a method of correcting duty cycle distortion in a transmitter. Other embodiments and features are also disclosed.

Abstract: Various embodiments of the present invention provide systems, apparatuses and methods for performing analog to digital conversion. For example, an analog to digital converter circuit is discussed that includes an analog input, a number of analog to digital converters and a generalized beamformer. The analog to digital converters are operable to receive the analog input and to yield a number of digital streams. Each of the analog to digital converters samples the analog input with different phase offsets. The generalized beamformer is operable to weight and combine the digital streams to yield a digital output.

Abstract: Various techniques are provided to detect a state of a communication signal. In one example, a method of detecting a state of a signal includes receiving a differential communication signal comprising a positive portion and a complementary negative portion. The method also includes filtering the positive portion of the communication signal through a first low pass filter to provide a filtered positive portion of the communication signal. The method also includes filtering the negative portion of the communication signal through a second low pass filter to provide a filtered negative portion of the communication signal. The method also includes comparing the filtered positive portion of the communication signal with an internal reference voltage. The method also includes comparing the filtered negative portion of the communication signal with the internal reference voltage.

Abstract: A MIMO system supports multiple spatial multiplexing modes for improved performance and greater flexibility. These modes may include (1) a single-user steered mode that transmits multiple data streams on orthogonal spatial channels to a single receiver, (2) a single-user non-steered mode that transmits multiple data streams from multiple antennas to a single receiver without spatial processing at a transmitter, (3) a multi-user steered mode that transmits multiple data streams simultaneously to multiple receivers with spatial processing at a transmitter, and (4) a multi-user non-steered mode that transmits multiple data streams from multiple antennas (co-located or non co-located) without spatial processing at the transmitter(s) to receiver(s) having multiple antennas. For each set of user terminal(s) selected for data transmission on the downlink and/or uplink, a spatial multiplexing mode is selected for the user terminal set from among the multiple spatial multiplexing modes supported by the system.

Abstract: Embodiments of the invention describe a method for antenna selection (AS) in a wireless communication network, the network comprising user equipment (UE), wherein the UE comprises a plurality of subsets of antennas including a first subset of antennas and a second subset of antennas, and wherein the UE is configured to transmit a sounding reference signal (SRS) from a subset of antennas at a time. The method transmits a first SRS from the first subset of antennas, transmits a second SRS from the second subset of antennas, receives, in response to the transmitting the first SRS and the second SRS, information identifying an optimal subset of antennas from the first subset of antennas and the second subset of antennas, and transmits user data from the optimal subset of antennas.

Abstract: A multiple-access MIMO WLAN system that employs MIMO, OFDM, and TDD. The system (1) uses a channel structure with a number of configurable transport channels, (2) supports multiple rates and transmission modes, which are configurable based on channel conditions and user terminal capabilities, (3) employs a pilot structure with several types of pilot (e.g., beacon, MIMO, steered reference, and carrier pilots) for different functions, (4) implements rate, timing, and power control loops for proper system operation, and (5) employs random access for system access by the user terminals, fast acknowledgment, and quick resource assignments. Calibration may be performed to account for differences in the frequency responses of transmit/receive chains at the access point and user terminals. The spatial processing may then be simplified by taking advantage of the reciprocal nature of the downlink and uplink and the calibration.

Abstract: Disclosed herein is a clock data recovery circuit including: a first phase detector; a loop filter; a charge pump; a voltage-controlled oscillator; a second phase detector; a phase correction information generation section; and a phase correction information addition section.

Abstract: In a closed-loop wireless communication system, a codebook-based feedback mechanism is provided to enable non-unitary precoding for multi-stream transmission, where in each stream is optimized with suitable transmission power allocation and AMC. The codebook-based feedback mechanism uses a precoding codebook having a power allocation matrix which is constrained to specify that beamforming always applies full power to a predetermined beam. With this constraint, a one-bit power allocation feedback index may be used to switch between beamforming and spatial multiplexing.

Abstract: Disclosed is a method of detecting signals at a receiver of a communication system with a multiple input multiple output antenna. With the signal detection method, a square of the distance between a received signal vector and a channel status-considered transmission symbol vector is calculated first, and the square of the distance is then classified into first and second components. The first component is minimized to calculate a plurality of first soft symbol estimates. A solution set of the first component is calculated on the basis of the plurality of first soft symbol estimates. The second component is minimized to calculate a plurality of second soft symbol estimates. A solution set of the second component is calculated on the basis of the plurality of second soft symbol estimates. A final solution set is calculated by doing the sum of the first component solution set and the second component solution.

Abstract: A method for signal detection using a log likelihood ratio in a multi-input multi-output communication system includes reconfiguring the signals received through the reception antennas on the basis of channel characteristics and acquiring candidate groups for each transmission symbol by acquiring a signal constellation of one quadrant with respect to signals generatable for each transmission symbol and signal constellations for the remaining quadrants on the basis of the reconfigured signals.

Abstract: A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.

Abstract: The present invention provides systems and methods for band amplification with a shared amplifier. In an exemplary embodiment, the wireless band amplification device has with an amplifier with an input port and an output port. The wireless band amplification device also provides two circulators, the first circulator in communication with the input port of the amplifier and the second circulator in communication with the output port of the amplifier. Additionally, two duplexer devices are provided in communication with both circulators. The input port of the amplifier is enabled to receive at least a first frequency band downlink signal and a first frequency band uplink signal. In an alternate embodiment, the input port of the amplifier can be further adapted to receive a second frequency band downlink signal and a second frequency band uplink signal. Additionally, the input port of the amplifier can be further adapted to receive a third frequency band downlink signal and a third frequency band uplink signal.

Abstract: An apparatus and method for reducing error in converting a multi-bit signal to a single bit signal. An analog delta-sigma modulator receives an analog signal and converts it to a multi-bit digital signal that is provided to a digital delta-sigma modulator. The digital delta-sigma modulator introduces error by converting the multi-bit signal to a single-bit signal. The error from the conversion is fed back to the analog delta-sigma modulator which incorporates the error information into the analog signal before it is converted to a multi-bit digital signal.

Abstract: A method and apparatus for allocating subcarriers in an orthogonal frequency division multiple access (OFDMA) system is described. In one embodiment, the method comprises allocating at least one diversity cluster of subcarriers to a first subscriber and allocating at least one coherence cluster to a second subscriber.

Abstract: A method and apparatus for allocating subcarriers in an orthogonal frequency division multiple access (OFDMA) system is described. In one embodiment, the method comprises allocating at least one diversity cluster of subcarriers to a first subscriber and allocating at least one coherence cluster to a second subscriber.

Abstract: A digital phase locked loop (DPLL) for providing clock synchronization in backplane bus systems has a loop filter with selectable high and low bandwidth modes. The DPLL is thus capable of respectively attenuating or tracking jitter from an input reference clock.

Abstract: Input signals are electronically watermarked using an uneven or non-uniform sampling rate. The uneven or non-uniform sampling may be pseudo-random. The uneven or non-uniform sampling meets the Nyquist criterion so that aliasing and loss of content are avoided. The resulting sampling pattern in the sampled data is detectable by a comparison with the original source data.

Abstract: A digital phase locked loop (DPLL) for providing clock synchronization in backplane bus systems has a loop filter with selectable high and low bandwidth modes. The DPLL is thus capable of respectively attenuating or tracking jitter from an input reference clock.

Abstract: A non-propagating magnetic field-based communication system transmits and receives digital data within a limited coverage area environment. The system includes a compact transmitter unit, such as that contained in an ‘tracking’ tag affixed to an object, and a digital detector/demodulator unit. In order to generate and FSK-modulate a non-propagating magnetic field in accordance with modulation signals representative of the digital data, the transmitter unit contains a magnetic field coil and one or more capacitors controllably switched in circuit with the coil in accordance with the data, so as to change the resonant frequency of an inductor-capacitor transmitter resonant circuit. The receiver unit includes a magnetic field-sensing coil in circuit with a capacitor, to form a receiver resonant circuit that resonates at a frequency between the FSK frequencies modulated by the transmitter unit.

Abstract: A signal FSK-modulated with a binary data signal has first signal portions representing first logical level data contained in the binary data signal and second signal portions representing second logical level data contained in the binary data signal. Each of the first signal portions has a first frequency and lasts for a first time period and each of the second signal portions has a second frequency and lasts for a second time period. These first and second time periods are determined such that a number of cycles of the FSK-modulated signal appearing in each of the first time periods is equal to a number of cycles of the FSK-modulated signal appearing in each of the second time periods.

Abstract: A differential pulse encoding and decoding approach for binary data transmissions, such as binary frequency shift keying (BFSK) data transmissions, for sending and recovering a serial, binary digital data stream by differentiating the pulses thereof. A method and system are disclosed for transmitting from a transmitter to a receiver a digital data signal containing a stream of binary data bits having a first high value and a second low value. At the transmitter, the digital signal is transformed into a differential signal which contains pulses corresponding to transitions between the first and second values. The digital signal is transformed into the differential signal by an encoder which can be a differentiator circuit or an RC high-pass filter circuit. If frequency spectrum is a concern, a low-pass filter can filter the output of the encoder. The differential signal is then transmitted, and received by the receiver which reconstructs the original digital signal therefrom.

Abstract: Biphase or FM encoding is combined with Flash modulation in infrared (IR) communication. By shrinking the coded pulse width in the modulation process, power dissipation is effectively reduced to the point where FM encoding can be advantageously adapted to IR communication in a synchronous communication system. Noise filtering is also described.

Abstract: An arrangement is disclosed for determining a byte error rate (ByER) of a received digital signal. In particular, a local byte clock signal is generated and a complement of the received signal (or clock signal) is compared to the clock signal (or received signal). When both are the same logic value, as determined by a series of logic gates, an error is deemed to have occurred. A counter is utilized to track a number of occurrences N over a predetermined period of time T.