Abstract: It is intended to reduce the rate of occurrence of prediction value judgment errors. Where a prediction value x'.sub.n-1 of a 1-clock preceding code is 0, a judgment circuit 1 outputs a value "1" as a prediction value x'.sub.n if a reproduction signal value y.sub.n sampled at time n is greater than or equal to a threshold value .eta. that is supplied from a threshold value generating circuit 6, and outputs a value "-1" as the prediction value x'.sub.n if y.sub.n <.eta.. Where x'.sub.n-1 is not 0, the judgment circuit 1 outputs a value "0" as the prediction value x'.sub.n. Therefore, the control circuit 1 outputs a value "0" every other clock as a prediction value. During the interval between the first two clocks, the threshold value .eta. is set at 0. Then, when supplied with codes of a given pattern that are arranged at the start, a switch 2 selects the prediction value x'.sub.n that is supplied from the judgment circuit 1. An operation circuit 16 calculates a phase error .DELTA..tau..sub.

Abstract: In digital, magnetic and optical storage systems for audio/video/data, a Viterbi detector is extended by a control output, and a PLL is controlled by a variable delay line at the output or inside of the PLL.

Abstract: An analog waveshaping circuit is capable of performing waveshaping of an AC analog signal in which the positive and negative peak levels with respect to a reference level are not the same, while considering a DC offset component of the reference level of the analog waveform, so that the positive and negative levels with respect to the reference level are made equal.

Abstract: A method and apparatus for decoding a partial response encoded signal to generate a decoded signal. The first stage of the apparatus, a first delay filter, receives the partial response encoded signal and filters it with a delay characteristic of (1-D.sup.2)(1+D). The second stage, a timing system, generates a digital signal representative of the first filtered signal. The timing system includes an equalizer with an EPR4 equalization characteristic. The third stage, a second delay filter, filters the signal with a delay characteristic of 1-D. The final stage, a partial Viterbi decoder, generates the decoded signal.

Abstract: Improved self-synchronization in a sampled magnetic recording channel employing time-domain equalization. The channel includes a time-domain equalizer which filters an input, readback signal to an approximation of a selected target waveform. The equalizer includes a plurality of serially connected analog filter sections having associated tap locations, analog multipliers which multiply the tap signals present at the tap locations by tap weight signals to generate product signals and a summer which sums the product signals to generate an equalized output signal. A self-synchronization circuit, responsive to the main tap of the equalizer, synchronizes the data recovery process used by the channel with the rate of the readback signals provided to the channel.

Abstract: A system for reproducing data recorded on a magnetic recording medium at high density is provided as a simple configuration. Quadripartite reproduction data is output from a Viterbi detection circuit to an adder, which then subtracts the quadripartite reproduction data from a signal before PR4-ML method data determination. An adder is used to perform a (1+D) process for the result. An error signal pattern detection circuit performs maximum likelihood estimation for an PR4-ML method detection error. Further, when a detected determination error matches an actual reproduction data string, a data correction circuit corrects the reproduction data string.

Abstract: A partial response class-IV (PR4) read channel is disclosed for magnetic recording including a coding scheme which improves timing recovery by providing a more accurate phase error estimate. The conventional 1/(1+D.sup.2) precoder is not used in the present invention (to avoid the ambiguous initial state), so that the read channel can directly control the flux transitions written onto the magnetic disc. This enables the read channel to encode user data according to a criteria that creates well defined slopes in the analog read signal at the sample instances, thereby improving the accuracy of the timing recovery phase error estimate.

Abstract: A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes. The bits in each of the data bytes are selectively complemented in accordance with the number of logical `1` signals in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity.

Abstract: In a magnetic disk drive for writing write data by a head to a magnetic disk, equalizing a reproduced signal read out from the magnetic disk by a head at the time of reproduction, and effecting maximum likelihood detection for the reproduced signal after equalization and thus demodulating the read data, "1s" are periodically inserted as dummy bits into a data string of the write data. On the other hand, a timing signal and a clock signal which are synchronous with the positions of the dummy bits are generated from the reproduced signals after equalization, and a threshold level of binary/ternary judgement is switched by this timing signal. Binary judgement is made at the position of the dummy bit in the reproduced signal after equalization and path merge is unconditionally regarded as existing at the position of the dummy bit in the reproduced signal after equalization, and path retrieval is made, while ternary judgement is made for other code strings to execute maximum likelihood detection.

Abstract: A signal processing channel and method for reducing intersymbol interference in a sequence of data symbols includes a pre-shaping filter for sharpening leading edges of data symbols and providing trailing edges that approximate a decaying exponential. The output of the pre-shaping filter is combined with a cancellation output from a resistance-capacitance circuit having a time constant selected to provide pulse responses that complement the exponentially decaying trailing edges. The combination of the shaped output and the cancellation output is input to a slicer or other decision device. The 2-level output from the slicer is an input to a decision feedback filter that generates the cancellation output. In addition to the resistance-capacitance circuit, the decision feedback filter includes a delay to properly time the coincidence of the cancellation output with the shaped output from the pre-shaping filter.

Abstract: A read system for implementing PR4 and higher order PRML signals includes: a continuous time programmable filter, for receiving a read signal representative of a binary signal from a storage medium and for shaping the read signal into a PR4 shaped read signal; an analog finite impulse response (AFIR) filter, responsive to the continuous time programmable filter, for sampling and forming the PR4 shaped read signal into a PR4 shaped multilevel read signal; an analog to digital converter, responsive to the AFIR filter, for converting the PR4 shaped multilevel read signal from analog to digital; a data sequence filter, responsive to the analog to digital converter, for transforming the PR4 shaped multilevel digital read signal to a predetermined order PRML signal; and a Viterbi detector, responsive to the data sequence filter, for detecting the binary signal from the predetermined order PRML signal.

Abstract: In a digital information reproducing apparatus in which a clock signal can be recovered stably when reproduced digital information signals are detected by utilizing a partial response (PR) class 4 detection method, a digital information signal reproduced from a magnetic tape is equalized into a PR (1, -1) signal by means of an equalizer circuit, then equalized eventually into the PR class 4 signal by means of a (1+D) operation circuit and supplied to a ternary discriminator circuit to provide original digital information. A signal equalized into the PR (1, -1) signal and delivered out of the equalizer circuit is supplied to a clock component extractor circuit comprised of, for example, two squaring circuits, and a signal spectrum is generated in which a bright-line spectrum of high level develops at a bit frequency component of the reproduced digital information signal. The signal spectrum is supplied to a PLL circuit and a clock signal phase-locked to the bit frequency component can be obtained.

Abstract: Disclosed is a phase difference detection circuit for detecting a phase difference between an equalized signal obtained by equalizing an extended partial-response class-4 signal and a sampling clock. This phase difference detection circuit has a sample hold circuit for sampling and holding the equalized signal at the sampling clock, a comparator circuit for comparing the sampled and held signals with at least four slice levels and converting them into determination level signals having at least quinary values and a phase difference generation circuit for generating a phase difference on the basis of at least the quinary determination level signals from the comparator circuit and outputs of the sample hold circuit. The EPR-4 signals are quinary-determined, and it is therefore possible to measure the phase difference by accurately detecting a peak position or a zero cross position of the signal.

Abstract: An EPR4 detector comprises a PR4 Viterbi detector and an EPR4 post-processor for improving estimated output sequence at an output of the PR4 Viterbi. The PR4 Viterbi detector produces digital estimates of coded digital information values into the channel in accordance with a path through a PR4 trellis and produces other path information relating to other paths through the PR4 trellis.

Abstract: A data receiving and processing channel including analog signal processing circuitry operable for receiving data in the form of an input analog signal, and modifying the input signal in accordance with selected parameters so as to generate a modified analog input signal. According to one embodiment, there is provided a charge domain signal equalizer which initially transforms the modified analog input signal into a corresponding analog charge domain signal, the equalizer performing waveform shaping of the analog charge domain signal in accordance with a predetermined signal response template; a charge domain analog-to-digital converter operable for converting the analog charge domain signal into a corresponding digital signal; and a digital signal processor operable for recovering a digital bit stream from the digital signal which is indicative of the original data.

Abstract: A data demodulator operating to recover symbols from a data signal including, an estimator, coupled to the data signal, for estimating a reference parameter, and a decision function that is responsive to the reference parameter and the data signal, for selecting a symbol for a symbol time from a set of predetermined symbols where the symbol is coupled to the estimator for updating the reference parameter when the symbol is representative of the reference parameter.

Abstract: An improved adaptive three tap transversal equalizer for partial-response signaling. The invention reduces the complexity of the hardware, as well as reducing the sensitivity of the equalizer to gain and timing errors. The present invention employs an algorithm based on sample values around zero. The resulting decrease in average magnitude of the error results in decreased sensitivity to gain errors. The algorithm of the present invention improves cancellation of sample timing errors. In the present invention, the coefficient of an adaptive cosine equalizer is updated by integration of a stochastic gradient. To calculate the gradient, the product of the quantized output from the previous sample and the output from the present sample is summed together with the product of the output from the previous sample and the quantized output from the present sample. In addition, the equalizer output is masked such that values quantizing to non-zero values are discarded in the update algorithm.

Abstract: Disclosed are a partial-response record signal regenerating method of and an apparatus for regenerating a record signal of a data area which is read from a storage disc by use of an equalizing circuit after training a circuit constant of said equalizing circuit with a training signal of the record signal read from the storage disc. The record signal regenerating method comprises: a Viterbi decode step of Viterbi-decoding an output into which the record signal is equalized by the equalizing circuit; a decode step of converting an m-bit output which is Viterbi-decoded into n-bits (m>n); and a synchronism detecting step of detecting the training signal from the m-bit output which is Viterbi-decoded and indicating a start of decoding the record signal of the data area.

Abstract: A method and apparatus are provided for maximum-likelihood data detection in a partial-response (PR) data channel including a head and disk assembly providing an analog signal coupled to an analog to digital converter (ADC) providing digital samples. A plurality of digital samples are received from the ADC. The received digital samples are applied to a selected first filter and a selected second filter. The first filtered digital samples are applied to a first data detector, and the second filtered digital samples are applied to a second data detector. A predetermined parameter is identified, and at least one of the first and second data detectors is selected responsive to the identified predetermined parameter.

Abstract: In a digital transmission system including a transmitter (2) coupled via a channel (4) to a receiver (6) a detection signal r.sub.k is compared with a number of reference values to determine the destination symbols a.sub.k. Since the size of the received signal r.sub.k is not known in advance, the ratio between the detection signal and the reference values is to be determined by an adapting circuit (16) on the basis of the received signal and the decisions made. The problem may then occur that as a result of an initially erroneous value of the ratio between detection signal and reference values not a correct adaptation is made. By recognizing such a situation because specific values of the symbols a.sub.k are lacking, in such a situation said ratio can be brought to such a value by the correction circuit (18) that all the values of a.sub.k again occur.

Abstract: A method and means for detecting spectral null sequences of a spectrally-constrained code at the output of a noisy communications channel by tracking the spectral content of said sequences with a Viterbi detector using an N stage trellis and mapping each spectral null sequence to a unique path of acyclic successive states and edges through said trellis by selectively outsplitting counterpart states at preselected times modulo N in said trellis such that no pair of unique paths support the same spectral null sequence.

Abstract: An EPR4 detector comprises a PR4 Viterbi detector and an EPR4 post-processor for improving estimated output sequence at an output of the PR4 Viterbi. The PR4 Viterbi detector produces digital estimates of coded digital information values into the channel in accordance with a path through a PR4 trellis and produces other path information relating to other paths through the PR4 trellis.

Abstract: A simplified architecture is provided for a partial response read channel. One digital equalizer is used in conjunction with a simple shaping circuit to minimize power consumption while concurrently optimizing both the data recovery and timing extraction functions.

Abstract: An optical reproducing apparatus, for example, an optical magnetic disc device for reproducing data, has been recorded on a disc recording medium by applying the Viterbi decoding method, or the like, and can effectively avoid the deterioration of bit error rate even if the DC level fluctuates. When Viterbi decoding the reproducing signal by converting it into digital values, if a transition pattern in which the signal level of the reproducing signal transits across the center level is detected, the center level is corrected.

Abstract: A transceiver (20) communicates audio and non-audio data between a variety of digital audio sources and sinks. Transceiver (20) has a receiver (34, 38) which communicates data between a modulated digital audio source (12) and an unmodulated digital audio sink (28), and a transmitter (42, 46) which communicates data between an unmodulated digital audio source (22) and a modulated digital audio sink (16). Digital data is transferred from receiver (34, 38) or received in transmitter (42, 46) in one of a plurality of eight formats. Each of the formats is designed to enable transceiver (20) to interface with a variety of digital audio sinks and sources without additional circuitry. A plurality of mode control pins determine the format provided to transceiver (20) when transmitting or receiving digital audio data.

Abstract: An improved adaptive three tap transversal equalizer for partial-response signaling. The invention reduces the complexity of the hardware, as well as reducing the sensitivity of the equalizer to gain and timing errors. The present invention employs an algorithm based on sample values around zero. The resulting decrease in average magnitude of the error results in decreased sensitivity to gain errors. The algorithm of the present invention improves cancellation of sample timing errors. In the present invention, the coefficient of an adaptive cosine equalizer is updated by integration of a stochastic gradient. To calculate the gradient, the product of the quantized output from the previous sample and the output from the present sample is summed together with the product of the output from the previous sample and the quantized output from the present sample. In addition, the equalizer output is masked such that values quantizing to non-zero values are discarded in the update algorithm.

Abstract: Method and apparatus for controlling the timing of the sampling of signals and signal amplitude in a PRML read channel. A VCO generates a read clock and a clock generator connected to the VCO generates even and odd clock signals corresponding to even and odd cycles of operation of the VCO. Serially connected even sample and hold circuits respond to clock signals to store samples of the read channel signal taken during successive odd cycles and serially connected odd sample and hold circuits store samples taken during successive even cycles. Comparator circuits compare the samples taken in each cycle to reference signals and the comparisons are clocked through two stage, even and odd shift registers to provide estimates of the presence or absence of nonzero samples for each even and odd cycle.

Abstract: A digital communications system suitable for high-speed data transmission includes a transmitter and a receiver providing the ability to selectively switch between multiple coding and decoding methods. The transmitter includes a plurality of trellis coders, each of which performs a different type of coding on a transmission signal. The receiver includes a plurality of Viterbi decoders, corresponding to the different types of coders in the transmitter, for decoding the transmission signal. The receiver also includes a selector for determining which of the decoder outputs to choose from based on the frequency of code violations detected in the transmission signal. The present invention thus provides a flexible apparatus for improving the quality of high-speed data transmissions.

Abstract: A maximum likelihood detector for a disc drive in which data files are stored along tracks as a sequence of magnetically written data elements that give rise to a signal in the disc drive read chapel. The detector includes even and odd Viterbi decoders that determine the most likely even and odd subsequences of data elements from even and odd samples of the signal and a postcoder that generates the most likely sequence of bits of encoded user data from the subsequences.

Abstract: A Viterbi decoder having a recursive processor modified to process each node in a trellis of a partial response coded signal to shift the branch metric additions over the node to effectuate compare, select, add operation order on the predecessor survivor metrics terminating in that node, to compare the metrics of the predecessor sequences terminating in the node, to select a survivor sequence, and to add the shifted branch metrics to the metric of the selected survivor sequence.

Abstract: Timing loop apparatus and method are provided for data detection in a partial-response maximum-likelihood (PRML) data channel. The PRML data channel includes an analog to digital converter (ADC) providing samples to a digital filter during a tracking mode and to a gain and timing control during an acquisition mode. Sample values from the ADC are received at peaks and zeros on sync field pattern. An error absolute value is calculated from the received ADC sample values and an error sign of the calculated error absolute valve calculated using a most significant bit of the current and a previous sample. Timing correction values are calculated responsive to the calculated error absolute value and applied to a clock gated register that latches and holds the generated timing correction values for a predefined number of clock cycles.