Abstract: An automatic input threshold selector includes a maximum value level decision circuit, and an input threshold setting circuit. The maximum value level decision circuit decides, among m+1 level layers defined by m maximum value decision levels, a level layer to which the maximum value of an input signal belongs. The input threshold setting circuit sets an input threshold by selecting one of n input threshold candidates in response to the level layer to which the input signal maximum value belongs. These circuits are implemented as a simple combination of a voltage comparator, logic gates and the like. This makes it possible to solve a problem of a conventional automatic input threshold selector in that its circuit scale and power consumption is rather large because it includes a peak-hold circuit and a bottom-hold circuit.

Abstract: A digital receiver circuit is easily integrated into a single chip. A differential output amplifier circuit is used for performing a binarizing decision by a quantizer for a differential output. A peak detection circuit, an average value detection circuit, an operational amplifier and a transistor are provided for controlling an input impedance and an offset of the differential output amplifier circuit depending upon a differential output. Thus, a capacitor for alternating current coupling as required conventionally, becomes unnecessary to facilitate integration into a single chip with minimum number of parts by full DC coupling.

Abstract: In a method for deciding the level of an input signal, positive and negative signals are provided in response to the input signal. A peak of the positive signal is detected to provide a positive-peak value. A peak of the negative signal is detected to provide a negative-peak value. The positive signal and the negative-peak value are combined to provide a first combination signal. The negative signal and the positive-peak value are combined to provide a second combination signal. The first and second combination signals are compared to provide an output signal of zero or one.

Abstract: A miniature RF receiver in the UHF frequency band. This receiver design is specific to the implementation of a digital module, as it contains no downconversion elements, and provides the capability of defining the operational frequency with cascaded tunable filter stages. The tunable filters are combline filters with tuning varactor diodes terminating each printed resonator. The 1 dB bandwidth of the filter is 7 Mhz, and for resonator length of 31 degrees (at the center frequency), the filter bandwidth remains nearly constant across the tunable frequency range. The capacitance of a varactor diode is a function of applied voltage. By controlling the voltage to each varactor, the filter response can be tuned across the operational frequency range of 50 Mhz.

Abstract: A device and method for digitizing a RSSI signal in a wireless transmission system is disclosed, which comprises a micro-controller having a ring counter and a controller, a low-pass filter, and a comparator. To start a digitization process, the controller gradually increases a numeric control signal to control a ring counter to generate a square wave with different duty cycle. Subsequently, the square wave is filtered by a low-pass filter to obtain a DC threshold voltage. If the threshold voltage is larger than the RSSI voltage, the digitization process is complete and the final numeric control signal represents the digitized RSSI signal.

Abstract: A differentiating circuit and a clock generating circuit that do not include unwanted frequency components in a differentiated signal. An inverted signal of an NRZ (Non Return Zero) data signal is delayed by a fixed time in a delay circuit and added to a non inverted signal to generate a differentiated signal. A clock signal is generated by driving a resonator using a rectified signal produced by full wave rectifying the differentiated signal. At this time, resonant components arising due to impedance mismatching are removed by providing a LPF.

Abstract: A pre-amplifier circuit, which may be used in a variety of data recovery circuits to accurately recover data transmissions, includes an input regulatory circuit, a feedback circuit, and an amplifier. The input regulatory circuit regulates the magnitude of the data signal provided to the amplifier based on feedback signals from a feedback circuit. For low level data signals, the input regulatory circuit provides a full, or almost full, representation of the data signal to the amplifier for amplification. But, when the data signal levels increase, the input regulatory circuit attenuates, based on the feedback signals, the data signals more and more before providing them to the amplifier, such that the output of the amplifier stays within a certain range.

Abstract: The present invention provides an input receiver that slows the signal fluctuation by limiting the amount of electrical currents flowing through the input receiver. The limiting of electrical current flowing through the input receiver slows the input signal of the receiver which in effect filters out some level of glitches of an input signal. In one embodiment, the input receiver is constructed and implemented in a structure similar to a differential amplifier for a single interface. In another embodiment, the input receiver is constructed and implemented in a modified differential amplifier for a single interface. In a further embodiment, the input receiver is constructed and implemented in a modified differential amplifier for multiple interfaces.

Abstract: A digital super-regenerative receiver is provided having an analog RF detector and a regenerative oscillator. The output of the RF detector is used to generate a digital signal from which the oscillator bias is adjusted, in order to maintain the oscillator start-up time at a fixed level. The circuit senses if the start-up time is earlier or later than the predetermined start-up time and produces an output when the majority of the start times are ahead of the expected start time.

Abstract: A dual reference voltage input receiver comprises a latch, comparison logic for determining the voltage level of a data signal relative to that of first and second reference voltage levels, and selection logic for determining which of the reference voltage levels is operative for a given data interval, e.g. clock cycle. The latch couples the determined voltage level of the data signal to a subsequent stage and to the selection logic for determining the operative reference voltage level in the next data interval. In one embodiment of the invention, the comparison logic includes first and second comparators for comparing the data signal with first and second reference voltages, and the selection logic is a MUX having its data inputs coupled to the comparators' outputs and its selection input coupled to the data output of the latch.

Abstract: A circuit for restoring bits transmitted by an asynchronous signal includes a first comparator for comparing the level of the asynchronous signal with a first threshold adjusted as a function of the output of the first comparator during synchronization bursts of the asynchronous signal, and at least a second comparator for comparing the level of the asynchronous signal with a second threshold correlated to the first threshold.

Abstract: A pre-amplifier circuit, which may be used in a variety of data recovery circuits to accurately recover data transmissions, includes an input regulatory circuit, a feedback circuit, and an amplifier. The input regulatory circuit regulates the magnitude of the data signal provided to the amplifier based on feedback signals from a feedback circuit. For low level data signals, the input regulatory circuit provides a full, or almost full, representation of the data signal to the amplifier for amplification. But, when the data signal levels increase, the input regulatory circuit attenuates, based on the feedback signals, the data signals more and more before providing them to the amplifier, such that the output of the amplifier stays within a certain range.

Abstract: An optical signal is converted by a light-receiving element into a photoelectric current. The photoelectric current is converted by a preamplifier into a positive phase voltage and the opposite phase voltage. The peaks of the positive phase output and opposite phase output are sensed and held by a first and second peak sensing circuits. The median between the output of the second peak sensing circuit and the positive phase output of the preamplifier is determined by a first median output circuit. The median between the output of the first peak sensing circuit and the opposite phase output of the preamplifier is determined by a second median output circuit. A level comparison circuit compares the outputs of the first and second median output circuits and produces a signal voltage with a constant amplitude within a specific input voltage range, thereby producing a reception signal.

Abstract: An output signal of an opto-electric conversion element 1 is amplified by a differential type pre-amplifier 3 to a predetermined level and input to an ATC circuit 5 as a positive phase signal and an inverted phase signal. These signals are held in respective peak holding circuits 51 and 52 of the ATC circuit 5. The positive phase signal held in the peak holding circuit 51 is added by an adder 57 to the inverted phase signal from the pre-amplifier 3 and the inverted phase signal held in the peak holding circuit 52 is added by an adder 58 to the positive phase signal from the pre-amplifier 3. Resultant sum signals are compared by a comparator 7 with a reference and discriminated as logical "1" and "0". The positive phase signal from the pre-amplifier 3 is input to a self-reset circuit 9 including a level detector 91, a reset pulse generator and a reset circuit 93. The level detector 91 detects a signal from the pre-amplifier 3.

Abstract: A local area network line system having a bus line and a plurality of devices is disclosed. Each of the devices comprises a data receiver circuit coupled to the bus line for detecting a communication start request from a signal applied on the bus line and being in a sleep mode when the data receiver circuit receives a sleep command signal and a transmitting circuit coupled to the bus line for outputting a transmitting signal in response to a transmit control signal. Each of the devices further comprises an edge detection circuit coupled to the bus line for detecting a level variation of the signal applied on the bus line and outputting a detection signal in response to the detected level variation and a communication control circuit coupled to the data receiver circuit, the transmitting circuit and the edge detection circuit for outputting the transmit control signal to the transmitting circuit.

Abstract: A pulse sensor for sensing keyed pulses for a keyed AFC which is used in a hi-vision satellite broadcast receiver, has a differentiating circuit that differentiates pulse signals supplied thereto so as to be amplified by a dc amplifier. The amplified signal is transformed by a window comparator such that a resultant signal having a fixed voltage level is output as a pulse sense signal. The sensor circuit is simplified and can be easily manufactured in an integrated circuit configuration.

Abstract: A method and apparatus for passing a high frequency signal across an isolation barrier while rejecting low frequency common mode interference is provided. A high frequency signal is coupled across an isolation barrier. A circuit comprising an element having an impedance that is a function of frequency rejects low frequency common mode interference. The high frequency signal is provided as an output. The present invention is useful, for example, for isolating telephone apparatus, such as a telephone modem, from a telephone line.

Abstract: A transmission-reception circuit, including a transmitter circuit and a receiver circuit connected to each end of a transmission line, for transmitting and receiving a signal to another receiver circuit and from another transmitter circuit at the other end across the transmission line, wherein in order to enable logical decision on a receiving signal to be made accurately and secure high reliability in a fully duplex simultaneous two-way communication, power supply lines are laid at opposite ends of the transmission line and threshold voltages for logical decision on a signal received by the receiver circuit are supplied from a power unit used for the transmitter circuit and the receiver circuit at the other end of the transmission line.

Abstract: A digital data receiver comprises a pre-amplifier for receiving a digital data input signal and a correction signal to produce a data output signal. A dc offset cancelling circuit is responsive to the data output signal for generating the correction signal to cancel dc offset contained in the digital data input signal. A post-amplifier receives the data output signal from the pre-amplifier and a reference signal. A peak detector is responsive to an output of the post-amplifier for detecting a peak amplitude thereof and generating the reference signal so that the post-amplifier has a first gain value during the time the data input signal is absent or less than its peak amplitude, and a second gain value approximately equal to twice the first gain value for a predetermined time after the peak amplitude of the data input signal is reached. The post-amplifier and peak detector have substantially equal operating characteristics.

Abstract: A dc-coupled packet mode digital data receiver, for use with an optical bus uses peak detectors to adaptively establish an instantaneous logic threshold at the beginning of a data burst. A dc compensator, responsive to outputs of the peak detectors, shunts dc or low frequency currents, corresponding to "dark level" optical signals, from the input of the receiver.