Abstract: An apparatus for synchronizing frequency to a symbol timing, the apparatus including: a master oscillator to generate a master clock signal; an interpolator to accumulate a frequency error estimate between a symbol timing frequency and the master clock signal; and a frequency controller to transfer a portion of the frequency error estimate to the master oscillator to obtain a lock between the symbol timing and the master clock signal of the master oscillator in a manner that zeros-out the frequency error estimate.

Abstract: An electronic device capable of performing automatic frequency control (AFC) to maintain frequency and timing without good received bursts, in which an oscillation unit and a baseband processing unit are provided. Wherein, the baseband processing unit computes a compensation adjustment according to a prediction model and stored information regarding a previous digital value adjustment when detecting that the baseband processing unit is incapable of controlling the oscillation unit according to received bursts from the remote communication unit, and adjusts the oscillation unit according to the determined compensation adjustment.

Abstract: A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source VSS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source VDD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.

Abstract: A center frequency of an adjustable filter is controlled to achieve a compromise between DC offset rejection and image rejection.

Abstract: A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source VSS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source VDD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.

Abstract: In accordance with a method for identifying a preamble sequence and for estimating an integer carrier frequency offset, a signal that comprises a preamble sequence from a set of possible preamble sequences is received. A reduced set of integer carrier frequency offset (CFO) candidates may be determined. Cross-correlation operations may be performed with respect to the received signal and multiple candidate transmitted signals. Each candidate transmitted signal may include one of the set of possible preamble sequences. In addition, each candidate transmitted signal may correspond to one of the reduced set of integer CFO candidates. Multiple correlation values may be determined as a result of the cross-correlation operations. The correlation values may be used to identify the preamble sequence and to estimate the integer CFO.

Abstract: Disclosed herein is a receiving apparatus including a preamble analyzer configured to receive a frame of DVB-T2 made up of an OFDM signal and analyze a preamble contained in the received frame; an offset detector configured to detect a fine offset and a coarse offset on the basis of the analyzed preamble; a carrier frequency corrector configured to execute carrier frequency correction on an OFDM time domain signal obtained by quadrature demodulation on the basis of the detected fine offset and the detected coarse offset; a determiner configured to determine whether the detection of the coarse offset has been completed; and a control signal outputter configured, if the detection of the coarse offset is determined to be completed, to output a control signal for feeding back the fine offset detected on the basis of an OFDM frequency domain signal obtained by FFT computation to the carrier frequency corrector.

Abstract: A transmitter includes an encoding module, an adaptive hierarchical signal mapping module and a transceiver module. The encoding module receives an input signal and encodes the input signal. The input signal includes data to be transmitted. The adaptive hierarchical signal mapping module modulates the encoded signal according to one or more hierarchical level distance ratios to obtain modulated symbols. The hierarchical level distance ratio defines distances between the modulated symbols. The transceiver module generates a radio frequency signal according to the modulated symbols and transmits the radio frequency signal to an air interface.

Abstract: A timing recovery circuit recovers the symbol timing of a modulation signal. A carrier recovery circuit corrects the frequency shifts of output signals of the timing recovery circuit. An FIR equalizer having a plurality of taps, and corrects the distortions of output signals of the carrier recovery circuit. A control circuit dynamically controls the number of taps used in the FIR equalizer.

Abstract: A receiver having an intermediate frequency error correction circuit includes a mixer having a source input, a local oscillator input, and an IF output, an adjustable frequency local oscillator having an output coupled to the local oscillator input of the mixer, an IF filter having an input coupled to the IF output of the mixer and an IF filtered output, where the IF filter has an IF filter frequency response, and control circuitry coupled to the local oscillator such that the frequency of the local oscillator can be varied to at least: partially correct an IF frequency error.

Abstract: A circuit for producing multiple switching control signals for a harmonic rejection mixer from multiple phases of a digital local oscillator signal is presented, wherein a first waveform combiner circuit is arranged to generate from the multiple phases of the digital local oscillator signal at least one switching control signal by logical combining two from the multiple phases of a digital local oscillator signal, and a second waveform combiner circuit is arranged to generate from the multiple phases of the digital local oscillator signal at least one first switching control signal by logical combining one from the multiple phases of a digital local oscillator signal with a predetermined signal having a static logical value.

Abstract: Frequency of an oscillating signal is temporarily adjusted to adjust frequency and/or phase of an output signal. For example, the frequency of the oscillating signal may be adjusted for a very short period of time to adjust the phase of the output signal. In addition, the frequency of the oscillating signal may be temporarily adjusted in a repeated manner to adjust the effective frequency of the output signal. In some aspects the frequency of the oscillating signal is adjusted by reconfiguration of reactive circuits associated with an oscillator circuit.

Abstract: A system for processing a received signal having at least one code applied thereto, the received signal having a frequency, the system comprising: first correlator circuitry arranged to correlate the received signal with a first code to provide an output; second correlator circuitry arranged to correlate the received signal with a second code to provide an output, wherein the first code and the second code are different; and processor for processing together the outputs of the first and second correlator circuitry to cancel the frequency.

Abstract: A receiver configured to selectively receive an RF signal from an operating band having a plurality of RF channels. The receiver is configured to upconvert the desired RF channel to an intermediate frequency (IF) greater than the RF channel frequencies. The upconverted RF channel is downconverted to baseband or a low IF. The receiver can perform channel selection by filtering the baseband or low IF signal. The baseband or low IF signal can be upconverted to a programmable output IF.

Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal 30 according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock 15.

Abstract: A multilevel QAM demodulator includes a phase difference calculation unit calculating a phase difference signal based on the common phase signal and orthogonal signal after the phase rotation compensation, a phase shift amount calculation unit calculating a phase shift amount indicating a degree of a phase shift based on the common phase signal and orthogonal signal after the phase rotation compensation and phase noise compensation, and a correction unit correcting the phase difference signal based on the phase shift amount. A phase rotation is performed for the phase noise compensation based on the phase difference signal corrected by the correction unit.

Abstract: A multiband receiver is disclosed for receiving a multiband RF signal having first and second RF bands. The first RF band contains a first service RF range, and the second RF band contains a second service RF range. The receiver includes a mixer for converting the RF signal into an IF signal, using a single local oscillator frequency “f,” and an IF bandpass filter for canceling out some of frequencies of the IF signal outside of a predetermined passband. The local oscillator frequency “f” is determined to allow the first and second service IF ranges to lie outside of the predetermined passband, and to allow a frequency portion of the first IF band exclusive of the first service IF range and a frequency portion of the second IF band exclusive of the second service IF range to lie within the predetermined passband.

Abstract: A realtime spectrum trigger system on a realtime oscilloscope considers both the magnitude and phase of an input signal having a periodic component so that successive acquisitions of the input signal are time aligned. A user inputs a frequency, threshold and phase for triggering on the periodic component. Input signal samples are filtered by quadrature filters according to the frequency input to produce quadrature signal components. The square of the magnitude of the input signal is computed from the quadrature signal components, as well as the phase ratio and sign, for comparison with calculated values. When enabled by the magnitude of the input signal, a phase crossing determinator compares the phase ratio and sign with calculated values to determine the phase crossing to generate a trigger, resulting in successive acquisitions of the input signal being in time alignment.

Abstract: A receiver according to one embodiment includes a frequency control unit configured to receive a stream of samples including a plurality of received instances of a transmitted signal. The frequency control unit is configured to output a first correction signal (e.g. indicating a rotation) that is based on more than one of the received instances and a second correction signal (e.g. to control an oscillator) that is also based on more than one of the received instances. In some embodiments, a controlled oscillator is used to receive and/or transmit another signal, such as a signal received from a GPS space vehicle. In other embodiments, the received instances are from a GPS signal. In further embodiments, a fixed-frequency oscillator is used, and the second correction signal is used to receive and/or transmit another signal, such as a GPS signal.

Abstract: A differential receiver which provides for estimation and tracking of frequency offset, together with compensation for the frequency offset. Estimation and tracking of the frequency offset is undertaken in the phase domain, which reduces computational complexity and allows frequency offset estimation and tracking to be accomplished by sharing already-existing components in the receiver. Compensation for the frequency offset can be performed either in the time domain, before differential detection, or in the phase domain, after demodulation, or can be made programmably selectable, for flexibility.

Abstract: A system and method for implementing an IQ generator includes a master latch that generates an I signal in response to a clock input signal, and a slave latch that generates a Q signal in response to an inverted clock input signal. A master selector is configured to provide a communication path from the master latch to the slave latch, and a slave selector is configured to provide a feedback path from the slave latch to the master latch. The foregoing I and Q signals are output directly from the respective master and slave latches without any intervening electronic circuitry.

Abstract: A receiving apparatus includes: a demodulating unit which demodulates an IF signal obtained by subjecting a received RF signal to frequency conversion; a detecting unit which detects a carrier wave frequency error contained in the IF signal; a frequency control unit which sets an initial value of a frequency in the demodulation process by the demodulating unit and for correcting a frequency error of a frequency used for the demodulation process by the demodulating unit based on the carrier wave frequency error detected by the detecting unit; and a control unit which controls a setting of an initial value of a frequency in the demodulation process by the demodulating unit by means of the frequency control unit after a receiving channel is switched, based on the carrier wave frequency error before a receiving channel is switched, the error being detected by the detecting unit, when a receiving channel is switched.

Abstract: A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop.

Abstract: A system and method for communicating a plurality of carrier waves that are received by a single receiver system is provided. The receiver system includes at least one antenna, at least one splitter, a plurality of tuners, and at least one combiner. The antenna receives a plurality of carrier waves. The splitter is in communication with the antenna, and splits the plurality of carrier waves. The plurality of tuners are in communication with the at least one splitter, and the split carrier waves are communicated to a separate tuner. The at least one combiner is in communication with the plurality of tuners, and combines an output of the plurality of tuners to generate an output based upon at least a portion of the received plurality of carrier waves.

Abstract: A device for signal synchronization in a communication system is configured to perform a first sliding correlation for a received signal and a pseudo-random noise (PN) sequence to obtain information on symbol timing, identify a fractional carrier frequency offset (FCFO) using the information on symbol timing and the cyclic extension property of the PN guard interval (GI), and provide a first product by multiplying the received signal with the FCFO. The device is also configured to provide a set of second products by multiplying the first product with each of a set of phases related to integral carrier frequency offsets (ICFOs), perform a second sliding correlation for the PN sequence and each one of the set of the second products to thereby provide a set of peak values, and identify an ICFO by detecting an index number of a maximal value among the set of peak values.

Abstract: In an example embodiment, a clock generation circuit comprises two programmable ring oscillators arranged and configured to operate in a mutually exclusive manner, and a variable programmable delay element (not shown). An input programming pattern is provided as an input to the oscillating circuit, the programming pattern providing data representative of the sequence of frequencies at which the clock signal is required to be generated. The outputs of both the oscillators are connected to a clock switch (16), from which the generated clock signal is output. When a request for a change of frequency is received, the currently idle oscillator is first activated with the next required frequency, the output of the currently operative oscillator is then gated when the clock signal thereof goes low. Next, the previously gated output of oscillator is un-gated when its output goes low, and then oscillator is de-activated.

Abstract: A system comprises a correlation module that receives modulated signals from R antennas, that correlates each of the modulated signals with Y preamble sequences, and that generates Y correlation values for each of the R antennas, where R and Y are integers greater than or equal to 1. A control module generates correlation sums by adding each of the Y correlation values for one of the R antennas to corresponding ones of the Y correlation values for others of the R antennas, that selects a largest correlation sum from the correlation sums, and that detects one of the preamble sequences in the modulated signals when a magnitude of the largest correlation sum is greater than or equal to a first predetermined threshold.

Abstract: In an ultra-wideband receiver for receiving discontinuous pulse signals and for demodulating the receive signals, an amplifier amplifies signals received, and a demodulator demodulates the amplified signals. A controller controls the demodulator and the amplifier based on the signals demodulated by the demodulator. The controller sends a signal to the amplifier to activate the amplifier only when the signals are received in order to decrease the power consumption in the amplifier. Further, the demodulator demodulates the amplified signals by generating a plurality of single pulses as template pulses, multiplies the amplified signals with the plurality of signal pulses, and integrates the multiplied signals to obtain demodulated data.

Abstract: Timing acquisition is performed. A first portion of a preamble having an end is sampled. A first phase value is determined based on the sampled first portion. A second portion of the preamble is sampled and a second phase value is determined based on the sampled second portion. An end phase value is extrapolated based at least in part the first phase value and the second phase value. A clock is adjusted using the extrapolated end phase value.

Abstract: Methods and systems are provided for estimating the DC offset distortion in a receiver. A fast Fourier transform is applied to at least a portion of a preamble portion of the received signal; an impact of the DC offset distortion on one or more empty subcarriers is determined; individual DC estimates are derived based on each of the determinations; and each of the individual DC estimates are combined to obtain an overall DC estimate.

Abstract: A differential receiver which provides for estimation and tracking of frequency offset, together with compensation for the frequency offset. Estimation and tracking of the frequency offset is undertaken in the phase domain, which reduces computational complexity and allows frequency offset estimation and tracking to be accomplished by sharing already-existing components in the receiver. Compensation for the frequency offset can be performed either in the time domain, before differential detection, or in the phase domain, after demodulation, or can be made programmably selectable, for flexibility.

Abstract: A received low-frequency standard radio wave, which is an amplitude modulation signal, is converted to an intermediate frequency signal Sa, and is output to a detection circuit and an AGC circuit. The detection circuit and AGC circuit generates an RF control signal Sf1 and IF control signal Sf2 from the input intermediate frequency signal Sa, and controls an RF control circuit and IF control circuit by outputting the generated RF control signal Sf1 and IF control signal Sf2 to the RF control circuit and IF control circuit. By this a radio wave reception device can speed up AGC operation.

Abstract: A method for communication using a modulation scheme defined in a signal space includes determining demodulation confidence levels at a plurality of points distributed over the signal space. Weights are assigned to the respective points responsively to the demodulation confidence levels. A signal is received and demodulated using an adaptive loop so as to derive a corresponding signal point in the signal space. The adaptive loop is adjusted responsively to a weight assigned to the derived signal point.

Abstract: The invention relates to a method and a circuit arrangement for determining the carrier frequency difference during the demodulating of received symbols (P1, P2) in the complex phase space (I, Q; R, ?) of a quadrature modulation method (QAM), wherein to determine the frequency the received symbols are compared with symbols (S1, S2) at nominal positions in the complex signal space. In order to make the determination independent of a rotation of the coordinate system of the received signals with respect to the coordinate system of the symbols, it is proposed to determine the angle (?(P1, P2)) between two received signal values (P1, P2) and compare it to possible nominal angles of the quadrature modulation method. An angle deviation between the determined angle of the received signal values and the nominal angle can be used as a direct measure of a frequency deviation (?f).

Abstract: A receiver (300) includes a first mixing digital-to-analog converter (DAC) (336, 332), a second mixing DAC (338, 334), a direct digital frequency synthesizer (DDFS) (302), a phase correction circuit (340), a selectable load (306) and a magnitude correction circuit (350). The first mixing DAC (336, 332) includes a first input for receiving an input signal, a second input for receiving a digital first local oscillator (LO) signal and an output. The second mixing DAC (338, 334) includes a first input for receiving the input signal, a second input for receiving a digital second local oscillator (LO) signal and an output. The DDFS (302) is configured to provide the first and second LO signals, which are quadrature signals. The phase correction circuit (340) is configured to provide a phase correction signal to a control input of the DDFS (302). The first selectable load (306) includes an input coupled to the output of the first mixing DAC (336, 332) and a control input.

Abstract: A received low-frequency standard radio wave, which is an amplitude modulation signal, is converted to an intermediate frequency signal Sa, and is output to a detection circuit and an AGC circuit. The detection circuit and AGC circuit generates an RF control signal Sf1 and IF control signal Sf2 from the input intermediate frequency signal Sa, and controls an RF control circuit and IF control circuit by outputting the generated RF control signal Sf1 and IF control signal Sf2 to the RF control circuit and IF control circuit. By this a radio wave reception device can speed up AGC operation.

Abstract: A digital broadcasting receiver, a driving method, and a self-diagnosis method thereof, are provided. The digital broadcasting receiver includes: a digital demodulator for demodulating a digital broadcasting signal; a lock detector for detecting lock signals from the digital demodulator; and a lock processor for controlling the digital demodulator according to the detected lock signal.

Abstract: Provided are a pulse signal generator for UWB radio transception and a radio transceiver having the same. The pulse signal generator includes: an envelope generator generating a plurality of envelope signals; a local oscillator array composed of a plurality of high frequency oscillators, each outputting two oscillation signals having a phase difference from each other; a multiplier array receiving the envelope signals and the oscillation signals and outputting signals obtained by respectively multiplying the envelope signals by the oscillation signals; and an I channel adder and a Q channel adder outputting an I channel pulse signal and a Q channel pulse signal by adding output signals having the same phase components among the signals output from the multiplier array, respectively.

Abstract: A tuner (200) includes a direct digital frequency synthesizer (206) and a mixer (220). The direct digital frequency synthesizer (206) has an output terminal for providing a digital local oscillator signal having a frequency chosen to mix a desired channel to baseband. The mixer (220) has a first input terminal for receiving a tuned radio frequency signal, a second input terminal coupled to the output terminal of the direct digital frequency synthesizer (206), and an output terminal for providing an in-phase baseband signal.

Abstract: Carrier frequency detection for an N-ary modulated signal is achieved by digitizing the N-ary modulated signal, frequency shifting the digitized N-ary modulated signal to prevent aliasing, raising the frequency-shifted signal to the Nth power, transforming the raised signal to frequency domain data and determining an initial maximum frequency peak, iteratively fine shifting the frequency of the N-ary modulated signal around the initial maximum frequency peak and repeating the raising, transforming and determining steps to obtain a plurality of maximum frequency peaks, and calculating the carrier frequency from the maximum frequency peaks and the total related frequency shift.

Abstract: A reference timing signal apparatus with a phase-locked loop has a computer algorithm which adaptively models the multiple frequencies of an oscillator following a training period. The oscillation frequency of the oscillator is controlled in response to a phase detector output. The computer algorithm processes the control signal applied to the oscillator. The computer algorithm updates the characteristics of the model relating to the aging and temperature of the oscillator, using for example, a Kalman filter as an adaptive filter. By the algorithm, the subsequent model predicts the future frequency state of the oscillator on which it was trained. The predicted frequency of the model functions as a reference to correct the frequency of the oscillator in the event that no input reference timing signal is available. In a case of using pre-processing infinite impulse response filters (IIRFs) before the adaptive processor, the time delay caused by the filters are compensated after the adaptive processor.

Abstract: An apparatus comprising a first circuit, a second circuit, a third circuit and a fourth circuit. The first circuit may be configured to generate a demodulated signal in response to (i) a modulated signal and (ii) a seed value. The second circuit may be configured to generate a first control signal in response to the demodulated signal. The third circuit may be configured to generate a second control signal in response to (i) the first control signal and (ii) a compensation signal. The fourth circuit may be configured to generate the seed value in response to the second control signal.

Abstract: A carrier frequency in a filtered received M-ary phase-shift keyed (MPSK) modulated signal having in-phase and quadrature components is detected by processing the filtered received signal to remove modulation components and thereby generate a test signal at the carrier frequency; processing the test signal to provide an amplitude spectrum of samples at different test frequencies; and processing the amplitude spectrum to detect the carrier frequency in accordance with the test frequency at which there is a test statistic of the highest magnitude. The magnitude of the test statistic is determined by processing a signal statistic in relation to a noise statistic. The signal statistic is the amplitude of the largest-amplitude sample. The filtered received signal is processed to provide approximate values of the modulus of the received signal and the phase of the received signal; and the approximate modulus and phase values are processed to generate the test signal.

Abstract: An information recording device in which low-noise and clear image or audio information can be recorded by stopping the generation of a carrier in an oscillation section of wireless communication device during an imaging or sound recording process.

Abstract: A method and apparatus are provided for generating first and second modulation signals from a local oscillator signal for quadrature subharmonic modulation of a quadrature amplitude modulated information signal. The method includes the steps of delaying the local oscillator signal in a plurality of incremental odd and even delay steps to form respective sets of odd and even modulator signals, said odd set of modulator signals together forming the first modulation signal and said even set forming the second modulation signal for quadrature subharmonic modulation of the quadrature amplitude modulated information signal and controlling a magnitude of the incremental delays based upon a predetermined phase offset between the local oscillator signal and a last delay step of the incremental delay steps.

Abstract: A multiple channel receiver (200) includes a communications receiver synthesizer (204) and at least one numerically controlled oscillator (NCO) (406) that produce local oscillator signals that are derived from a common reference oscillator (202). A DSP (212) and CPU (214) perform automatic frequency control (AFC) by adjustment of the reference oscillator (202) based upon a signal received by a receive channel using the local oscillator signal produced by the communications receiver synthesizer (204). The CPU (214) also provides a synchronous indication of adjustments to the reference oscillator (202) to control circuitry for the at least one NCO (406) so that the configuration of the NCO (406) can be altered so as to maintain a substantially constant frequency output during the adjustment of the reference oscillator (202).

Abstract: A method and apparatus are provided for generating first and second modulation signals from a local oscillator signal for quadrature subharmonic modulation of a quadrature amplitude modulated information signal. The method includes the steps of delaying the local oscillator signal in a plurality of incremental odd and even delay steps to form respective sets of odd and even modulator signals, said odd set of modulator signals together forming the first modulation signal and said even set forming the second modulation signal for quadrature subharmonic modulation of the quadrature amplitude modulated information signal and controlling a magnitude of the incremental delays based upon a predetermined phase offset between the local oscillator signal and a last delay step of the incremental delay steps.

Abstract: A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention includes an antenna for receiving transmitting RF signals, a PLL for generating multi-phase clock signals having a frequency different from a carrier frequency in response to the multi-phase clock signals and a reference signal having the carrier frequency, a demodulation-mixing unit for mixing the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output the RF signals having a frequency reduced by the carrier frequency and an A/D converting unit for converting the RF signals from the mixing unit into digital signals.

Abstract: The RF signals received from the LNB and the corresponding IF signal produced by the tuner may be offset in frequency due to reasons other than a frequency drift of the oscillator of the LNB, such as satellite transponder frequency adjustments made by the satellite transmission system. A tuner (9) includes a local oscillator (911) controlled by a controller.

Abstract: A digital demodulator which is capable of simplifying an application specific integrated circuit (ASIC) of a demodulator using a combined sampling technique.