Abstract: A narrowband AJ signaling system includes an AJ processor placed between a high precision analog-to-digital (ADC) converter and a narrowband digital receiver. In another example, the AJ processor is placed between the high precision ADC and a digital-to-analog converter (DAC). The AJ processor of either example may suppress the jammer power down to the level of the noise floor of the system.

Abstract: In one exemplary embodiment of the invention, a device includes: a first frequency search engine configured to receive input values and determine a frequency of a signal to be within a first frequency band; a second delay component configured to store at least a portion of the plurality of input values; and a second frequency search engine configured to determine the frequency of the signal to be within a second band that is a subset of the first band. The first frequency search engine includes: a shift register configured to store bits of the input values; a combining circuit configured to combine bits of the plurality of input values; a first delay component configured to serially store a plurality of accumulator values; and a feedback circuit configured to add a function of the first delay component output to a next accumulator value to obtain a modified next accumulator value.