Data Flow Inside Motion Estimator (epo) Patents (Class 375/E7.101)
  • Patent number: 12192486
    Abstract: Various schemes pertaining to video coding parallelization techniques are described. An apparatus receives video data. The apparatus subsequently calculates a plurality of figures of merits (FOMs), each of the FOM representing how well a particular coding tool may perform in encoding the video data. The apparatus further determines a coding tool that may be suitable for encoding the video data by comparing the FOMs. In determining the coding tool, the apparatus utilizes time-interleaving techniques to parallelly process the video data. The video data may include an array of coding blocks, and the apparatus may receive the video data using a snake-like processing order scanning through the array of coding blocks.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: January 7, 2025
    Assignee: MediaTek Inc.
    Inventors: Cheng-Yen Chuang, Chun-Chia Chen, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
  • Patent number: 12143610
    Abstract: A video encoder including a first buffer containing a plurality of data values defining a macroblock of pixels of a video frame. The video encoder also includes a second buffer and an entropy encoder coupled to the first and second buffers and configured to encode a macroblock based on another macroblock. The entropy encoder identifies a subset of the data values from the first buffer defining a given macroblock and copies the identified subset to the second buffer, the subset of data values being just those data values used by the entropy encoder when subsequently encoding another macroblock.
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: November 12, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Shyam Jagannathan, Naveen Srinivasamurthy
  • Patent number: 12124853
    Abstract: A data loading and storage system includes a storage module, a buffering module, a control module, a plurality of data loading modules, a plurality of data storage modules and a multi-core processor array module. The data is continuously stored in a DDR, and the data computed by the multi-core processor may be arranged continuously or be arranged according to a certain rule. After DMA reads the data into the DATA_BUF module by a BURST mode, in order to support fast loading of the data into the multi-core processor array, the data loading modules (i.e., load modules) are designed. In order to quickly store the computed result of the multi-core processor array into the (DATA_BUF module according to a certain rule, the data storage modules (i.e., store module) are designed.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: October 22, 2024
    Assignee: BEIJING TSINGMICRO INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Pengpeng Zhang, Peng Ouyang
  • Patent number: 12120345
    Abstract: A method for intra-prediction of a current block includes selecting peripheral pixels of the current block, where the peripheral pixels are used to generate a prediction block for the current block; for each prediction pixel of the prediction block, performing steps including selecting two respective pixels of the peripheral pixels; and calculating the prediction pixel by interpolating at least the two respective pixels; and coding a residual block corresponding to a difference between the current block and the prediction block.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: October 15, 2024
    Assignee: GOOGLE LLC
    Inventors: James Bankoski, Debargha Mukherjee
  • Patent number: 12075089
    Abstract: A method for coding a current block using an intra-prediction mode includes obtaining a focal point, the focal point having coordinates (a, b) in a coordinate system; and generating, using first peripheral pixels and second peripheral pixels, a prediction block for the current block, where the first peripheral pixels form a first peripheral pixel line constituting an x-axis, and where the second peripheral pixels form a second peripheral pixel line constituting a y-axis. Generating the prediction block includes, for each location of the prediction block at a location (i, j) of the prediction block, determining at least one of an x-intercept or a y-intercept; and determining a prediction pixel value for the each location of the prediction block using the at least one of the x-intercept or the y-intercept.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: August 27, 2024
    Assignee: GOOGLE LLC
    Inventors: James Bankoski, Debargha Mukherjee
  • Patent number: 11645084
    Abstract: Techniques are disclosed relating to operand routing among SIMD pipelines. In some embodiments, an apparatus includes a set of multiple hardware pipelines configured to execute a single-instruction multiple-data (SIMD) instruction for multiple threads in parallel, wherein the instruction specifies first and second architectural registers. In some embodiments, the pipelines include execution circuitry configured to perform operations using one or more pipeline stages of the pipeline. In some embodiments, the pipelines include routing circuitry configured to select, based on the instruction, a first input operand for the execution circuitry from among: a value from the first architectural register from thread-specific storage for another pipeline and a value from the second architectural register from thread-specific storage for a thread assigned to another pipeline.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: May 9, 2023
    Assignee: Apple Inc.
    Inventors: Christopher A. Burns, Liang-Kai Wang, Robert D. Kenney, Terence M. Potter
  • Patent number: 10474466
    Abstract: Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first data for a first block and second data for a second block. The first data and said second data are comprised of a plurality of rows and columns of pixel data. A block boundary between the first block and the second block is characterized. A correction factor for a deblocking algorithm is calculated with a first instruction for a sign operation that multiplies and with a second instruction for an absolute value operation. Data for pixels located along said block boundary between the first and second block are corrected.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: William W. Macy, Jr., Huy V. Nguyen
  • Patent number: 10303471
    Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Mostafa Hagog, Robert Valentine, Amit Gradstein, Simon Rubanovich, Zeev Sperber
  • Patent number: 9405536
    Abstract: A method provides support for packed sum of absolute difference operations in a floating point execution unit, e.g., a scalar or vector floating point execution unit. Existing adders in a floating point execution unit may be utilized along with minimal additional logic in the floating point execution unit to support efficient execution of a fixed point packed sum of absolute differences instruction within the floating point execution unit, often eliminating the need for a separate vector fixed point execution unit in a processor architecture, and thereby leading to less logic and circuit area, lower power consumption and lower cost.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: August 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Patent number: 8316184
    Abstract: Domain-based cache management methods and systems, including domain event based priority demotion (“EPD”). In EPD, priorities of cached data blocks are demoted upon one or more domain events, such as upon encoding of one or more macroblocks of a video frame. New data blocks may be written over lowest priority cached data blocks. New data blocks may initially be assigned a highest priority. Alternatively, or additionally, one or more new data blocks may initially be assigned one of a plurality of higher priorities based on domain-based information, such as a relative position of a requested data block within a video frame, and/or a relative direction associated with a requested data block. Domain-based cache management may be implemented with one or more other cache management techniques, such as least recently used techniques. Domain-based cache management may be implemented in associative caches, including set associative caches and fully associative caches, and may be implemented with indirect indexing.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: November 20, 2012
    Assignee: Intel Corporation
    Inventors: Zhen Fang, Erik G Hallnor, Nitin B Gupte, Steven Zhang