Abstract: An enable control circuit and a semiconductor memory are provided. The enable control circuit includes: a counting circuit, configured to: count past clock cycles, and determine a clock cycle count value; a selection circuit, configured to determine a target clock cycle count value according to a first config signal; and a control circuit, connected to the counting circuit and the selection circuit, and configured to: control an On Die Termination (ODT) path to be in an enabled state responsive to a level state of an ODT pin signal being inverted, and start the counting circuit; and control the ODT path to switch from the enabled state to a disabled state when the clock cycle count value reaches the target clock cycle count value.

Abstract: Apparatus comprises master counter circuitry to generate a master count signal in response to a clock signal; slave counter circuitry responsive to the clock signal to generate a respective slave count signal; and a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry; the master counter circuitry being configured to provide to the slave counter circuitry via the synchronisation connection: (i) data indicative of a count offset value and (ii) a timing signal defining a timing relationship between the clock signal and the count offset value; and the slave counter circuitry being configured, during a synchronisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the data indicative of the count offset value and a timing signal provided by the master counter circuitry.

Abstract: A device, including: an unsecure non-volatile memory; a secure device including: a processor; and a secure non-volatile memory; wherein the secure device is configured to: calculate a TMC value from an offset and a base value; store a TMC version value in the secure non-volatile memory and the insecure non-volatile memory, wherein the TMC version value is updated when TMC value is incremented the first time after the secure device is powered up; store the base value in the unsecure non-volatile memory; store the offset value in the unsecure non-volatile memory when the secure device is in a system power down state; store the offset value in the secure non-volatile memory when the secure device is in a rescue state; and store a TMC link value in the unsecure memory, wherein the TMC link value is based upon the base value and TMC version value stored in the unsecure memory.

Abstract: Disclosed are a latch circuit receiving a negative output of a next stage latch circuit as a feedback input, a double data rate (DDR) ring counter based on the latch circuit to perform DDR counting of pulse periods and reduce the number of toggles, a hybrid counting device counting lower-bit portion by using the latch-based DDR ring counter and upper-bit portion by using a binary counter, and an analog-to-digital converting device and a CMOS image sensor employing the hybrid counting device. A double data rate ring counter may include a plurality of latches coupled in a ring type. The plurality of latches may include positive-edge-triggered latches and negative-edge-triggered latches arranged alternately. A current stage latch receives an output of a previous latch stage to shift to a next latch stage according to a counter clock, receives an output of the next latch stage to check a data shift to the next latch stage, and falls to a low level if the data shift is checked.

Abstract: An electronic device includes a control logic portion suitable for generating a hold control signal based on a count enable signal, and a counting portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and a counting clock signal.

Abstract: A method for treating pipe string sections being in a set-back and being arranged in a vertical position comprises arranging a remote-controllable manipulator at least at one of the threaded portions of the pipe string sections. In addition, the method comprises providing the remote-controllable manipulator with a tool. The tool is arranged to at least clean or lubricate said threaded portion. Further, the method comprises moving the tool to a threaded portion which is to be treated and at least clean or lubricate the threaded portion.

Abstract: An electronic device includes a control logic portion suitable for generating a hold control signal based on a count enable signal, and a counting portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and a counting clock signal.

Abstract: This solid-state imaging device includes a first substrate and a second substrate which have circuit elements constituting pixels disposed therein are electrically connected to each other. The pixels includes: a photoelectric conversion element disposed in the first substrate; an amplifier circuit that amplifies a signal generated in the photoelectric conversion element to output the amplified signal; a signal accumulation circuit which is disposed in the second substrate and accumulates the amplified signal which is output from the amplifier circuit; and an output circuit that outputs the amplified signal accumulated in the signal accumulation circuit from the pixel.

Abstract: A solid-state image pickup device includes: electrically coupled substrates on which circuit elements constituting a pixel are arranged; a photoelectric conversion element included in the pixel; a reading circuit that reads from the pixel, a signal based on a signal generated by the photoelectric conversion element; and first to n-th circuit sets each including a circuit element that reads a signal by a corresponding one of first to n-th reading modes. n is an integer such that n?2. The circuit elements arranged on one of the substrates is used to complete operations from generation of the signal by the photoelectric conversion element to reading of the signal by at least one of the first to n-th reading modes. The photoelectric conversion element, the reading circuit, and at least one of the first to n-th circuit sets are arranged on the one of the substrates.

Abstract: A double data rate (DDR) counter includes a clock selection unit suitable for selectively inverting a first counting clock based on a control signal and for outputting a second counting clock, a first latch stage suitable for latching the second counting clock based on a counting enable signal and for outputting the least significant bit (LSB) of the DDR counter, a determination unit suitable for generating the control signal based on the last bit state of the LSB in a reset counting period, and a second latch stage suitable for receiving the LSB as a clock input to generate a higher bit of the LSB at least in a main counting period.

Abstract: A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.

Abstract: A method and apparatus for digital I/O expander chip with multi-function timer cells have been disclosed. A series of match reload registers load a series of match registers which are driven by a master counter. The status of the match registers can be retrieved through ports. The master counter is reloaded on rollover by a count limit register. The master counter has increment/decrement control and the rollover can be used in an interrupt control block to generate an interrupt request.

Abstract: A timer device includes a RES input terminal, an OUT output terminal, a delay circuit that delays a signal input to the RES input terminal, and a pre-settable down counter that counts a given set value, and outputs a measurement completion signal via an output terminal when the counting of the set value is completed. When a predetermined signal is input to an input terminal after an output of the measurement completion signal, the pre-settable down counter completes the output of the measurement completion signal based on a delay signal obtained by the delaying the predetermined signal using the delay circuit.

Abstract: A method of implementing a system time in an electronic device using a timer is disclosed. The method comprises storing a first count reset value in the electronic device; increasing a count value; comparing the first count reset value with the count value at a first particular time; resetting the count value when the count value is the same as the first count reset value at the first particular time; and generating an interrupt request signal when the count value is reset.

Abstract: Apparatuses, circuits, methods, and other embodiments associated with digital power on reset are described. In one embodiment, an apparatus includes a digital electronic component configured to produce a clock signal. A first counter is configured to output a first count signal based on the clock signal and a second counter is configured to output a second count signal based on the clock signal. A power on reset logic is configured to provide a power on reset signal based on the first count signal and the second count signal, where the power on reset logic is configured to disable the digital electronic component after providing the power on reset signal to prevent the digital electronic component from drawing power.

Abstract: A digital frequency divider including a parallel output register, a presettable asynchronous counter and a decoder. The parallel output register contains a desired count value. The presettable asynchronous counter has its preset data inputs coupled to the output of the parallel output register. The decoder receives its input from the data outputs of the presettable asynchronous divider and its output coupled to the load input of the presettable asynchronous counter.

Abstract: A battery powered device is able to maintain a clock value when the battery is removed for a short period. During a first time period, while the battery is in the device, clock pulses derived from a first oscillator are counted at a first rate in a first counter that represents the clock value. During a second time period following the first time period, while the battery is removed, the value of the first counter is maintained independent of any clock pulses derived from the first oscillator, clock pulses derived from a second low power oscillator are counted in a second counter. During a recovery time period following the second time period, clock pulses derived from the second oscillator are again counted in the second counter, while clock pulses derived from the first oscillator are counted in the first counter at a second rate higher than the first rate, the duration of the recovery time period being determined based on the number of pulses counted in the second counter during the second time period.

Abstract: A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin.

Abstract: A counter system and method and computer program product for managing counter systems. Counter systems management includes receiving a count event associated with a counter, updating a first stage counter value based on the count event, determining whether to eject the counter value based on a random function of the counter state, and ejecting the counter value. A counter system comprises a first stage update unit configured to accept a count event and to eject a counter. A second stage update unit may be configured to accept an ejected counter value, and includes a second counting module configured to accumulate the ejected counter value.

Abstract: According to one embodiment, S (S is an integer equal to or larger than two) number of sub counters each count S number of clocks of different frequencies, and a clock switching unit is provided for each sub counter and starts a counting operation of a sub counter of a next stage after finishing a counting operation in a sub counter of a local stage.

Abstract: Apparatuses, circuits, methods, and other embodiments associated with digital power on reset are described. In one embodiment, an apparatus is implemented with a digital electronic component that produces a clock signal. The apparatus also includes a first counter that outputs a first count signal based on the clock signal and a second counter that outputs a second count signal based on the clock signal. The apparatus also includes a power on reset logic that selectively provides a power on reset signal based on the first count signal and the second count signal. The power on reset logic can also selectively disable the apparatus upon providing the power on reset signal.

Abstract: A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal. Each of the first to fourth FFs receives a signal at a corresponding input terminal. And each of the first to fourth FFs outputs a signal at a corresponding output terminal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals.

Abstract: According to one embodiment, S (S is an integer equal to or larger than two) number of sub counters each count S number of clocks of different frequencies, and a clock switching unit is provided for each sub counter and starts a counting operation of a sub counter of a next stage after finishing a counting operation in a sub counter of a local stage.

Abstract: A system and method for configuring threshold values for fixed time delay counters of a System on a Chip (SoC) uses a reference clock signal and one or more frequency sub-range control signals corresponding to a frequency sub-range of the reference clock signal. A frequency sub-range of the reference clock signal is determined using the frequency sub-range control signals and the determined frequency sub-range is used to select a counter threshold value. The selected counter threshold value is provided to a counter and the counter then is updated at each cycle of the reference clock signal for a predetermined count based on the counter threshold value.

Abstract: A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal and outputs a signal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals.

Abstract: A method and apparatus for digital I/O expander chip with multi-function timer cells have been disclosed. A series of match reload registers load a series of match registers which are driven by a master counter. The status of the match registers can be retrieved through ports. The master counter is reloaded on rollover by a count limit register. The master counter has increment/decrement control and the rollover can be used in an interrupt control block to generate an interrupt request.

Abstract: An asynchronous ping-pong counter is disclosed. The asynchronous ping-pong counter comprises a first asynchronous counter, a second synchronous counter, and a controller, the asynchronous ping-pong counter operates between a first state and a second state. In the first state, the first asynchronous counter counts a first number of clock edges of a fast clock signal, and the second asynchronous counter holds a first counter output value. In the second state, the second asynchronous counter counts a second number of clock edges of the fast clock signal, and the first asynchronous counter holds a second counter output value. The controller determines a state transition based on a sampling of a slow clock signal by the fast clock signal.

Abstract: A counter increases a counted value at regular time intervals during a transmission time of a request signal Sr transmitted based on trigger signals input from a door unlocking sensor or the like. On the other hand, the counter decreases the counted value at regular time intervals during a non-transmission time of the request signal Sr. A determination unit either prohibits or permits transmission of the request signal Sr to a portable unit, based on comparison results of the counted value with a prohibition value and a lifting value.

Abstract: A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal and outputs a signal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals.

Abstract: An interlocked counter including a synchronous counter, a logic gate for judging end-value, a logic gate for amplifying an interlocking signal, at least one latch circuit for the interlocking signal, a logic gate for the interlocking signal, and a logic gate for an enable signal, wherein behavior of the synchronous counter is stopped when a count number arrived at an end value, by that the synchronous counter counts a number of pulses of a clock signal when the synchronous counter inputted an enable signal, the logic gate for judging end-value generates an interlocking signal when the count number outputted by a synchronous counter coincided with the end value, the logic gate for amplifying interlocking signal amplifies the interlocking signal in order to output to an external part, and the logic gate for enable signal generates the enable signal when the interlocking signal is not generated.

Abstract: An asynchronous ping-pong counter is disclosed. The asynchronous ping-pong counter comprises a first asynchronous counter, a second synchronous counter, and a controller, the asynchronous ping-pong counter operates between a first state and a second state. In the first state, the first asynchronous counter counts a first number of clock edges of a fast clock signal, and the second asynchronous counter holds a first counter output value. In the second state, the second asynchronous counter counts a second number of clock edges of the fast clock signal, and the first asynchronous counter holds a second counter output value. The controller determines a state transition based on a sampling of a slow clock signal by the fast clock signal.

Abstract: A solid-state image pick up device including a pixel array unit having unit pixels arranged in a matrix pattern. Each unit pixel includes a photoelectric converter. Additionally, the solid-state image pick up device has column signal lines that correspond to the respective columns of the matrix pattern, a row scanning means for selectively controlling each unit pixel, and an analog-digital converting unit for converting analog signals output from the unit pixels in a row selectively controlled by the row scanning means. The analog-digital converting unit further includes an asynchronous counter which performs counting in two modes and the asynchronous counter includes a counter processor configured so that when switching between the count modes occurs, a running count value is broken and there is an interval between the count modes and when a mode begins the running count value is reset to the value before the running count value was broken.

Abstract: An asynchronous counter that is capable of switching count mode includes flip-flops, and three-input single-output tri-value switches respectively provided between the adjacent pairs of the flip-flops. The tri-value switches switch among three values, namely, non-inverting outputs and inverting outputs of the flip-flops and a power supply level. Each of the tri-value switches switch among the three input signals according to two-bit control signals, and input a selected signal to a clock terminal of a subsequent flip-flop. When count mode is switched according to the control signals, a count value immediately before the mode switching is set as an initial value, and counting after the mode switching is started from the initial value.

Abstract: In order to provide an IF counting method for realizing an IF counter with a smaller circuit configuration, an IF counter comprises a countdown IF counting unit 1 for counting frequency-divided IF signals, an IF count time period determination unit 2 for determining a count time period, an IF count upper limit presetting unit 3 for providing the countdown IF counting unit 1 with an initial value, a lower-order m-bit comparison unit 5 for comparing the lower-order m bits of the value counted by the countdown IF counting unit 1 with information preset in the IF count upper/lower limit difference presetting unit 3 and a determination unit 6 for determining whether the count value is within a prescribed range, according to the higher-order (n+1?m) bits of the value counted by the countdown IF counting unit 1 and the comparison result of the lower-order m-bit comparison unit.

Abstract: A counter system and method and computer program product for managing counter systems. Counter systems management includes receiving a count event associated with a counter, updating a first stage counter value based on the count event, determining whether to eject the counter value based on a random function of the counter state, and ejecting the counter value. A counter system comprises a first stage update unit configured to accept a count event and to eject a counter. A second stage update unit may be configured to accept an ejected counter value, and includes a second counting module configured to accumulate the ejected counter value.

Abstract: An asynchronous counter that is capable of switching count mode includes flip-flops, and three-input single-output tri-value switches respectively provided between the adjacent pairs of the flip-flops. The tri-value switches switch among three values, namely, non-inverting outputs and inverting outputs of the flip-flops and a power supply level. Each of the tri-value switches switch among the three input signals according to two-bit control signals, and input a selected signal to a clock terminal of a subsequent flip-flop. When count mode is switched according to the control signals, a count value immediately before the mode switching is set as an initial value, and counting after the mode switching is started from the initial value.

Abstract: In a shift register, which is for use in an image display apparatus of the TFT active matrix type in which a driver circuit is integrally provided on a display panel, and which is so arranged as to boost a start pulse SP to a start pulse SPO by using a level shifter, and to supply the start pulse SPO to a flip-flop F1 of a shift register section, the start pulse SP having an amplitude lower than a driving voltage and being supplied thereto, the shift register is provided with an operation control circuit for inactivating the level shifter when the first stage flip-flop F1 outputs an output signal S1 and activates the level shifter when a last stage flip-flop Fn outputs an output signal Sn. Therefore, it is possible to reduce power consumption of the level shifter during a period in which the start pulse SPO is transmitted from a flip-flop F2 to a flip-flop Fn?1.

Abstract: A counter having enhanced counting speed is provided. The counter includes first through N-th output signal generators. The first output signal generator responds to a clock signal and outputs a first output signal in which a low level and a high level are output once per cycle of the clock signal. The second output signal generator responds to the clock signal and the first output signal and outputs a second output signal in which a low level and a high level are output every two cycles of the clock signal. The third output signal generator responds to the clock signal and the second output signal and outputs a third output signal in which a low level and a high level are output every four cycles of the clock signal. The N-th output signal generator responds to the clock signal and the N?1th output signal and outputs an N-th output signal in which a low level and a high level are output every 2N?1 (where N is a natural number greater than 1) cycles of the clock signal.

Abstract: A proportional counting circuit generates count values for use in variably adjusting gain and exposure time of an image sensor array. The count values are adjusted in proportion to the current count value. This technique allows for fast and accurate adjustment of gain and exposure time without sacrificing the visual performance defined by the contrast difference. At least one break-in signal disables counting in some lower bits when a particular higher bit is asserted and allows the count values to be adjusted by a different increment when the count value reaches a predetermined value by asserting the particular higher bit. Break-out signals are used in less significant bits to disable counting in all lower bits than the bit being disabled by the break-in signal from the more significant bit.

Abstract: A value for a first counter is maintained. A value for a second counter based on a content of a non-volatile memory is maintained. Updates to the value for the first counter and to the value for the second counter are controlled.

Abstract: A real time clock counter includes a serially connected plurality of register units, each register unit having a bit register for storing clock data, a half adder for incrementing the clock data stored in the bit register, and an activation circuit for activating the bit register. Each activation circuit includes a first input for receiving an oscillating timing signal and a second input for receiving a binary carry term from the previous bit register unit's half adder. Each activation circuit also includes an output for outputting a first activation signal or a second activation signal according to the first value and the oscillating timing signal such that when the activation circuit outputs the first activation signal, the bit register is activated, and when the activation circuit outputs the second activation signal, the bit register is not activated, saving power.

Abstract: A counter stage generally comprises a flip-flop and a reset circuit. The flip-flop may be configured to toggle a flip-flop signal between a first and a second state in response to a count signal applied to a clock input to effect a counting operation. The reset circuit may be configured to reset the counter stage to a predetermined state without changing the state of the flip-flop signal.

Abstract: An asynchronous up-down counter includes a plurality of counter blocks. Each of the counter blocks has a counter output, an up-down control output, and an up-down control input. A counter signal output from each of the counter blocks has at least two bits. The asynchronous up-down counter also includes a signal bus coupling the up-down control output of a first counter block counting lesser significant bits to the up-down control input of a second counter block counting more significant bits. An up-down control signal output from each of the counter blocks has at least two bits. The up-down control signal may include a first control signal enabling counting operation of the second counter block and a second control signal indicating counting-up and counting-down.

Abstract: The counter circuit comprises the initial value single port RAM having N initial value registers allocated for memorizing N initial values, the counter register single port RAM having N counter registers allocated for memorizing N counting values, and the control circuit for performing a counting operation for each counter register. The control circuit performs the counting operation for each counter register on a time division basis by using a single arithmetic unit.

Abstract: A multi-bit counter of the present invention is capable of high-speed operation because the time needed for increasing count values and combining count bits for a carry can be minimized by presetting all bit combinations for a unit having multiple bits and selecting the preset combinations by a clock signal, i.e., by presetting the state of each of the bit combinations and outputting a next required value.

Abstract: A phase-locked loop (PLL) includes a down counter having a detection circuit configured to determine when the counter reaches its terminal count. The down counter also includes a control line configured to alter the terminal count detected by the detection circuit by an off-set.

Abstract: A clock divider circuit for generating an output clock signal derived from an input clock signal with the output clock signal having a selected frequency and duty cycle. The clock divider circuit comprises a linear shift register with a feedback loop. Data is shifted through the stages of the linear shift register in response to the input clock signal being applied at a clock input port. The output clock signal is derived from the data outputs on selected stages in the linear shift register. In one aspect, the clock divider circuit divides a 667 MHz input clock signal to generate a 44 MHz output clock signal having a 50% duty cycle. In another aspect, the clock divider circuit divides a 669 MHz input clock signal to generate a 45 MHz output clock signal.

Abstract: A counter for synthesizing clock signals with minimal jitter. The inventive counter has a first counter stage; a look-ahead circuit input connected to said first counter stage; and a selection circuit for choosing between an output of said first counter stage and an output of said look-ahead circuit as an output of said counter. In the specific embodiment, the first counter stage is adapted to receive a first clock signal having a frequency of N cycles per second and output a second clock signal having a frequency of M cycles per second. The first counter stage includes an accumulator having a rollover point at which an instantaneous count thereof exceeds the value of N−M. The look-ahead circuit determines for a present clock cycle the rollover point for a preceding clock cycle. The look-ahead circuit is a second counter stage adapted to ascertain whether the rising edge or the trailing edge of the second clock signal is closer to the rollover point and output an indication with respect thereto.

Abstract: A reset circuit outputting a reset signal /RESET when detecting an abnormal state in a ring counter is provided. The reset circuit divides the outputs of flip-flops constituting the ring counter into two groups, and check if either of the groups has “H” data. When “H” data exists in both of the two groups or when “H” data does not exist in either of the two groups, the reset circuit activates the reset signal /RESET to L level. Therefore, a semiconductor device can detect an erroneous state and recover to a normal state quickly.

Abstract: There is provided a counter device comprising a master counter for counting an input signal applied thereto and a plurality of local counters disposed in a plurality of functional blocks, respectively, each for counting the input signal applied thereto, and for holding a count value corresponding to a plurality of bits of a count value of the master counter. A bus is disposed for each of the plurality of functional blocks to refer to remaining bits of the count value of the master counter.