Abstract: A battery charging method includes: determining whether a present charging cycle satisfies a floating charging condition when a first condition is satisfied, the first condition being that in a case where battery capacity is greater than a set capacity, a duration of continuous charging is greater than a set threshold; and charging using a set floating charging mode after determining that the present charging cycle satisfies the floating charging condition. As such, the battery capacity during the charging process is detected in real time. In a case where the battery capacity is greater than the set capacity, the duration of continuous charging is greater than the set threshold and the present charging cycle satisfies the floating charging condition, the floating charging mode is used in time, such that batteries are prevented from dangerous situations such as bulging, expansion and explosion, and the safety of battery charging is improved.

Abstract: Disclosed is a gray code generator. The gray code generator includes a counter that counts first to fourth digital bits in response to a clock signal, and a converter that converts the first to fourth digital bits to first to fourth gray bits. The counter includes a replica flip-flop that outputs the clock signal as the first digital bit, a first flip-flop that inverts the second digital bit in response to the clock signal to output the second digital bit, a second flip-flop that outputs a high level in response to the clock signal when a second inverted digital bit is different from a third inverted digital bit, and a third flip-flop that outputs the high level in response to the clock signal when a result of performing a NOR operation on the second and third inverted digital bits is different from a fourth inverted digital bit.

Abstract: Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.

Abstract: A circuit for pulse width measurement comprises a charging circuit, a comparator and a determining circuit. The charging circuit is configured to charge a capacitive device in response to a periodic signal. The comparator is configured to compare a voltage across the capacitor with a reference voltage level. The determining circuit is configured to determine the number of pulses of the periodic signal in response to a signal from the comparator indicating that the voltage across the capacitor reaches the reference voltage level.

Abstract: A timer device includes a RES input terminal, an OUT output terminal, a delay circuit that delays a signal input to the RES input terminal, and a pre-settable down counter that counts a given set value, and outputs a measurement completion signal via an output terminal when the counting of the set value is completed. When a predetermined signal is input to an input terminal after an output of the measurement completion signal, the pre-settable down counter completes the output of the measurement completion signal based on a delay signal obtained by the delaying the predetermined signal using the delay circuit.

Abstract: An input circuit in high speed counter module for PLC is provided, the input circuit being configured such that various types of pulse signals are changed to a single type of pulse signal and transmitted to an MPU, whereby the type of input pulse is checked or an operation of checking addition/deduction is omitted to increase an interrupt process speed.

Abstract: A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters.

Abstract: An arithmetic counter circuit for high performance CMOS image sensors includes a plurality of flip-flops of a plurality of counter stages and a plurality of multiplexers of the plurality of counter stages being coupled to the plurality of flip-flops. Each of the plurality of multiplexers coupled to receive control signals including at least one of a toggle signal, a keep signal, a shift enable signal, or a mode signal. The control signals select the output of each of the plurality of multiplexers. Each of the plurality of flip-flops is coupled to be in one of a toggle state, a keep state, a reset state or a set state based on inputs received from the plurality of multiplexers. Other embodiments are described.

Abstract: In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The counter includes at least one second stage for generating another bit of the value in the counter. An input clock signal is applied to a data input of the first stage and a clock input of the second stage.

Abstract: In at least one example embodiment, a counter circuit includes a latch stage configured to generate a latch stage output clock based on a first rising edge of an enable signal, a state of a counter clock at a previous falling edge of the enable signal, and a state of the output clock at the previous falling edge of the enable signal such that the latch stage output clock and the counter clock have a different state if the state of the counter clock at the previous falling edge and the state of the output clock at the previous falling edge are the same and such that the latch stage output clock and the counter clock have a same state if the state of the counter clock at the previous falling edge and the state of the output clock at the previous falling edge are different.

Abstract: In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The first stage includes a first clock input and is edge-triggered on one of the rising and falling edges of a signal applied at the first clock input. The counter includes at least one second stage for generating another bit of the value in the counter. The second stage includes a second clock input and is edge-triggered on the other of the rising and falling edges of a signal applied at the second clock input.

Abstract: Embodiments of the present disclosure relate to an electronic sensor including capture means producing a signals comprising x pulses during a given capture time, such that a?<x<b?, wherein a?, b? and x are non-null natural integers, and counting means receiving the signals, which are incremented with each pulse received, including a maximum counting capacity equal to z such that (b??a?)?z<a?, where z is a non-null natural integer, resetting the counting, when the maximum counting capacity z is exceeded and outputting, at the end of the capture time, a number representative of the number of pulses x of the signals, wherein a? is the minimum value and b? is the maximum value of the number of pulses that can be produced by the capture means.

Abstract: In a counter circuit of a control signal generating circuit, a selector circuit selects under control which is in accordance with a selector circuit control signal (CTR) a predetermined one in a signal VSYNC and a signal HSYNC, which are pulse signals, so as to input a pulse signal thus selected to a counter. The counter outputs a counted result of pulses of the inputted pulse signal. By use of the counted result, a VSYNC synchronization signal generating circuit or an HSYNC synchronization signal generating circuit generates a control signal to control the driving of image display.

Abstract: An efficient filter circuit and method for filtering a loss of receiver signal prevents false signals caused by glitches. The short glitches that happen at the positive edge of the clock signal may be prevented from affecting the whole clock cycle. The false signal removal circuitry is effective against both false active high and false active low signals. A selectable majority determination block also measures the number of glitches or average signal strength to determine that a valid signal is present. A mininum pulse width of a glitch is settable.

Abstract: A high speed binary counter includes a counting first flip-flop for each binary bit, a single AND gate for each lower order binary bit beyond B0 and B1, and at least two AND gates for each higher order binary bit. The counter also includes an input factor delay second flip-flop. The counter is further provided with a mechanism for redundant least significant terms for lesser order bits.

Abstract: A frequency divider for dividing a frequency of a clock signal by an odd divisor includes a flip-flop chain for latching signals having a number of flip-flops equal to the divisor. The frequency divider also has an XOR gate having two input nodes and an output node, one input node being electrically connected to the clock signal, the other input node being electrically connected to an inverted output node of the last flip-flop, and the output node of the XOR gate being electrically connected to clock input nodes of the odd flip-flops in the flip-flop chain. The frequency divider further has an inverter, an input node of the inverter being electrically connected to the output node of the XOR gate, an output node of the inverter being electrically connected to clock input nodes of the even flip-flops in the flip-flop chain.

Abstract: A Gray code counter includes a holding circuit, first and second conversin circuit and an operation circuit. The holding circuit stores gray code signals and outputs the stored gray code signals in response to a clock signal. The first conversion circuit receives the gray code signals from the holding circuit and converts the received gray code signals into first binary code signals. The operation circuit applies a logical operation to the first binary code signals so as to generate second binary code signals. The second conversion circuit receives the second binary code signals and converts the received second binary code signals into the gray code signals. The second conversion circuit outputs the gray code signals to the holding circuit.

Abstract: This invention provides a circuit and a method for programmable counters. It consists of a circuit and a method for unique programmable counters that provide half-integral as well as integral steps, such as 1.5, 2, 2.5, 3, 3.5, 4. This circuit and method are the first implementations of providing programmable counting with half-integral steps. The circuit and method of this invention can be extended via the cascading of toggle flip flops at the front end of the circuit of this invention. This provides the ability to enhance the speed of normal integral step counting applications. In addition, the cascading of the multiple copies of the circuit of this invention provides the ability to provide other fractional programmable counters. A key advantage of this invention is that the method of this invention is general enough to use any other type of counter sub-component beside the binary counter sub-component of this invention.

Abstract: This invention provides a circuit and a method for programmable counters. It consists of a circuit and a method for unique programmable counters that provide half-integral as well as integral steps, such as 1.5, 2, 2.5, 3, 3.5, 4. This circuit and method are the first implementations of providing programmable counting with half-integral steps. The circuit and method of this invention can be extended via the cascading of toggle flip flops at the front end of the circuit of this invention. This provides the ability to enhance the speed of normal integral step counting applications. In addition, the cascading of the multiple copies of the circuit of this invention provides the ability to provide other fractional programmable counters. A key advantage of this invention is that the method of this invention is general enough to use any other type of counter sub-component beside the binary counter sub-component of this invention.

Abstract: A bit counter stage, particularly for memory addresses, including: a master storage circuit; a slave storage circuit which is connected to the master storage circuit; a circuit for enabling the transit of an external address in the master storage circuit; a circuit for enabling the connection between the slave storage circuit and the master storage circuit; a circuit for enabling the connection between the master storage circuit and the slave storage circuit; a circuit for calculating the product of the external address and of an input carry signal which arrives from a preceding counter stage; and a circuit for calculating an output carry signal on the basis of the external address and of the input carry signal.

Abstract: A loadable counter circuit which is able to perform multiple contiguous counts. The loadable counter circuit uses a counter for monitoring a number of specified events. A data storage device is coupled to the counter for loading the counter with counter values for each of the contiguous counts. A control logic circuit is coupled to the counter and to the data storage circuit for loading the counter and the data storage device with the counter values.

Abstract: Structure and method for counting a predetermined number of counts is provided. A count end value is identified which is greater than or equal to (not less than) the predetermined number of counts. The count end value is chosen such that it is representable by n symbols (designated n-1, n-2, . . . , m, m-1, . . . , 1, 0) where the most significant n-1 through m symbols are a first binary symbol and the least significant m-1 through 0 symbols are a different second binary symbol, for example "1"0 and "0". An n-symbol current count value (also representable by n-1, n-2, . . . , m, m-1, . . . , 1, 0 symbols) is initialized to a count start value which is equal to the count end value minus the predetermined number of counts, then as the counter counts, the current count value is incremented by one (or some other count increment) for each count or cycle of the counter. After each iteration (or before the next iteration of the counter cycle) each of the n-1, . . .

Abstract: A high modulus counter is provided for receiving a counter enable (CE) signal which switches between digital states. The counter is a single load conditional look ahead counter having a carry chain isolated from a timing critical path. The counter includes one toggle flip-flop for receiving the CE signal. The flip-flop has a first output and a second output. The first output and the second output are connected to an even counter and an odd counter, respectively. Both the output of the first counter and the output of the second counter are received by each of a plurality of multiplexers which are controlled by the first output of the toggle flip-flop. In this way, the high modulus counter outputs and increments the pointer signals of the odd counter and the even counter, alternatively. The even and odd internal counters are initially set at zero and one, respectively, and each increments by two. A second flip-flop may additionally receive the external CE signal for synchronization.

Abstract: Improved PLL frequency synthesizer circuits, including a novel swallow counter, may be operated at high speeds without experiencing internal delays or malfunctions. The swallow counter supplies a modulus signal to a prescaler which is capable of selectively changing a frequency-dividing ratio of a frequency signal. The swallow counter includes a shift register, a counter, a count-up detector, a modulus signal generator, and a control circuit. The swallow counter is connected to the prescaler and the program counter, and is capable of counting a frequency-divided signal based on a set value data and producing the modulus signal in response to a load signal after counting is completed. The swallow counter supplies the modulus signal to the prescaler and determines whether the set value data is data prepared to fix the frequency-dividing ratio.

Abstract: A high-speed predecoding address counter circuit comprising at least three tetrad counters connected in series, each for inputting an external 4-bit address decoding signal in response to a set signal and cyclically shifting a logic signal with a specific logic value at its four output terminals in response to a clock signal, a first clock switching unit responsive to a logical value of a most significant bit of an output signal from a lowest-order one of the at least three tetrad counters, for transferring the clock signal to a higher-order one of at least three tetrad counters, at least one logic unit for detecting whether both most significant bits of output signals from at least two lower-order ones of the at least three tetrad counters have the specific logic value, and at least one second clock switching unit connected between at least one logic unit and at least one of the at least three tetrad counters other than the at least two lower-order tetrad counters, for switching the clock signal to the at le

Abstract: A Gray Code counter includes first translator logic, binary incrementing/decrementing logic, second translator logic, and a clocked storage device. The first translator logic receives at an input a Gray Code number, I.sub.gray ?n:0! which the first translator translates into a binary number, I.sub.bin ?n:0!. The binary incrementing/decrementing logic either increments or decrements the binary number I.sub.bin ?n:0! to produce an incremented/decremented binary number, Z.sub.bin ?n:0!. The second translator logic translates the incremented/decremented binary number Z.sub.bin ?n:0! into an incremented/decremented Gray Code number, Z.sub.gray ?n:0!. The clocked storage device stores the incremented/decremented Gray Code number, Z.sub.gray ?n:0!. The clocked storage device also feeds the incremented/decremented Gray Code number, Z.sub.gray ?n:0!, to the input of the first translator logic.

Abstract: A synchronous counter performing a count operation in response to an input of a clock having a fixed frequency. The synchronous counter including a first transmission gate receiving a counter initialization signal and transferring the counter output signal to a carry output node when the counter initialization signal is received during a time period in which the external address signal is not received, and a second transmission gate receiving the counter initialization signal and transferring an address signal to the carry output node when said counter initialization signal is received during a time period in which the external address signal is received.

Abstract: A method and circuit for selectively scaling a binary counter having N serially connected stages in which an output count from the counter is 2.sup.M times the number of clock signals that have been input to the counter. The first M stages of the counter are selectively held so that clock signals by-pass (or pass through) the first M stages without change. The M+1 stage receives each clock signal and is thereby caused to indicate that 2.sup.M clock signals have been received, when only one clock signal has, in fact, been received. The output of each stage is provided to a decoder array that provides the scaled count signal. The method and circuit find application in systems in which normal unscaled operation of the binary counter may be selectively replaced with high speed operation, such as during tests or during special operating modes. The circuit and method obviate the need for a separate high speed clock, or for adaptive circuitry in the decoder array.

Abstract: A synchronous counter comprises one D flip-flop circuit for performing divide-by-2 frequency division of a clock signal CK, JK flip-flop circuits for, when input signals have HIGH levels (logical value 1), inverting the levels of the output signals in synchronization with the clock signal CK, logic circuits for inputting control signals to the JK flip-flop circuits, lower-stage signal assembling circuits for grouping the output signals from the JK flip-flop circuits into two-signal-unit groups to produce logical product signals of the signals in these two,signal-unit groups, and upper-stage signal assembling circuits for further handling the output signals from the lower-stage signal assembling circuits, thereby firstly simultaneously satisfying an increase in speed of the counting operation as well as simplification of the wiring pattern and reduction in the circuit area and secondly realizing further increase in the counting operation.

Abstract: A counter cell includes a latch circuit, control circuit, and a pull-up circuit. The latch circuit is formed of a first clocked half-latch, a second clocked half-latch and an inverter for storing a binary output signal. The first clocked half-latch is responsive to a first clock phase signal for transferring the binary output signal from its input to its output. The second clocked half-latch is responsive to a second clock phase signal for transferring a binary output signal from its input to its output. The control circuit is responsive to an input complement signal for selectively passing the first clock phase signal to the first clocked half-latch so as to permit toggling the state of the binary output signal. The control circuit requires only one transistor and two input signals to perform its required functions. When the input complement signal is High and the first phase input clock signal is High, an enable signal is sent to the first clocked half-latch, thereby enabling the count process.

Abstract: A printer controller employs a microprocessor together with an application-specific-integrated-circuit (ASIC) to manage the operation of the printer. Among its functions, the ASIC manages memory access for the microprocessor. Either fast- or slow-clock microprocessors may be installed in the controller, but the ASIC requires a slow clock. When a fast-clock microprocessor is installed, the ASIC must divide the clock frequency to provide its own (slow) clock. Likewise, the use of a fast-clock microprocessor requires the ASIC to insert memory-cycle WAIT times, whereas a slow-clock microprocessor needs no WAITs. In a preferred embodiment of the invention, provision is made, during initial power-on RESET, to inform the ASIC which clock speed is being used. This information is conveyed by the configuration of the WAIT interconnection between ASIC and microprocessor, thus eliminating the need for a dedicated ASIC pin for this purpose.

Abstract: A controller for a clock generator. The controller of the present invention enables a clock signal to the internal clocking mechanism of a device. The controller of the present invention includes a detector and a timer. The detector has two input sense levels, such that it is capable of detecting a clock signal at two separate levels, the first level being larger than the second. Initially, the detector only detects when the clock signal is at a level greater than or equal to the larger of the levels. When this occurs, the timer begins counting. When the clock signal has been at or above the greater level for a predetermined time as determined by the timer, the detector enables the clock signal to go to the internal clocking mechanism. Thereafter, the detector only senses when the clock signal falls below the second level. Thus, the detector enables the clock signal to go to the internal clocking mechanism while the level of the clock signal is above the second level.

Abstract: A semiconductor integrated circuit includes an input terminal provided for each of input terminals. The input circuit outputs either one of "HIGH" or "LOW" as a frequency dividing ratio setting signal when the corresponding input terminal is "HIGH" or "LOW" in level but outputs another one of "HIGH" and "LOW" as a frequency dividing ratio setting signal when the corresponding input terminal is in an open state. Thus, the frequency dividing ratio of the programmable divider is determined, by fixing the level of only required ones of the input terminals into "HIGH" or "LOW" through, for example, wire bonding in the package while leaving all the others in open state.

Abstract: An N-bit binary counter includes N 1-bit counters together producing an N-bit binary word, and a count enable signal generator for generating count enable signals for each of the N 1-bit counters. The count enable signal generator includes multiple logic group/carry ripple devices, different ones of which receive different numbers of bits of the binary word and generate count enable signals for the same number of bits. The logic group/carry ripple devices also receive a carry ripple output signal from an adjacent logic group/carry ripple device and generate a carry ripple output signal for another adjacent logic group/carry ripple device.

Abstract: A circuit having a delay circuit provided with a gate for converting the output signal of an SR flip-flop into a signal with a delay equal to or more than the clock pulse width enough for count operation and leading the logical addition between the signal and system clock and the logical multiplication between the signal and counter write signal to the direct reset input of a transparent latch 7 and for realizing read-on-the-fly or write-on-the-fly operation even if timer input does not synchronize with the system clock.

Abstract: A semiconductor integrated circuit of this invention includes an oscillation circuit formed on a semiconductor substrate, a frequency dividing circuit formed on the semiconductor substrate, for dividing a frequency of an oscillation output from the oscillation circuit, clocked inverters for selectively permitting one of an original oscillation frequency signal of the oscillation circuit and outputs of the frequency dividing circuit to pass therethrough, an output circuit for outputting a signal selected by the cocked inverters, and a frequency dividing circuit controlling NAND circuit for interrupting the operation of the frequency dividing circuit while the original oscillation frequency signal of the oscillation circuit is being output from the output circuit.

Abstract: A counter cell includes a latch circuit, control circuit, and a pull-up circuit. The laatch circuit is formed of a first clocked half-latch (32), a second clocked half-latch (34) and an inverter (INV1) for storing a binary output signal. The first clocked half-latch (32) is responsive to a first clockk phase signal for transferring the binary output signal from its input to its output. The second clocked half-latch (34) is responsive to a second clock phase signal for transferring binary output signal from its input to its output. The control circuit is responsive to an input complement signal for selectively passing the first clock phase signal to the first clocked half-latch so as to permit toggling the state of the binary output signal. The pull-up circuit is responsive to the binary output signal and the input complement signal for generating an output complement signal.

Abstract: An improved dynamic frequency divider circuit is disclosed. A DC voltage generating circuit (10) generates a DC voltage (Vcon) having a level the same as a threshold voltage of an inverter. A voltage application circuit (41) supplies a voltage (Vcon) to one electrode of a capacitor through a high frequency signal component cut-off coil (8), and a high frequency signal component is superimposed on the provided DC voltage. Accordingly, an input signal of an inverter (1a) swings around the threshold voltage level as a center, so that the inverter (1a) can provide a signal having the duty cycle of 50% as an output. As a result, the dynamic frequency divider circuit can be prevented from malfunctioning.

Abstract: A system for masking bits in a configuration. The system has a bus with first and second sets of bit lines. A line from the first set is paired with aline from the second set; the paried lines are coupled to each cell in the configuration register. A logic circuit is connected to each register cell and the corresponding paired lines. Depending upon the state of the bit signal of the second set bit line, the logic circuit passes the bit signal on the first set bit line for loading into the register cell or reloads the bit line signal already in the register cell. In this manner, masking operations in the configuration register can be performed very quickly.

Abstract: A frequency divider circuit having N flip-flops connected in series, includes a logic circuit for monitoring at least one of the outputs of the N flip-flops and halting the frequency division operation of a prior stage flip-flop when the value of the output which is monitored is equal to a predetermined value when a reset signal is input, and restarting frequency division operation when the reset signal is cancelled.

Abstract: A programmable frequency divider for dividing the frequency of a supplied high-frequency signal directly into a lower frequency includes a plurality of 2-scale-factor prescalers or programmable frequency divider units each capable of being switched between divide-by-2 and divide-by-3 modes. The 2-scale-factor prescalers are connected in cascade for producing an output signal which is frequency-divided at one of multiple division ratios at a time.

Abstract: A self-configuring clock interface circuit automatically configures itself according to the type of clock input signals applied to two input terminals interconnected with the interface circuit. The system includes a pair of counters connected to the input terminals and having their outputs connected to the two inputs of an Exclusive NOR gate which acts as a control device for the system. The output of the exclusive NOR gate is coupled to a 2:1 multiplex to control the interconnection of one or the other of two inputs to the multiplex circuit with a clock output for the interface circuit.

Abstract: An asynchronous ripple counter counts from a predetermined binary value to zero in response to an input clock signal. Zero detection logic is coupled to the ripple counter for detecting, from a most significant bit to a least significant bit of the ripple counter, when the counter has counted to zero. Both the counter and the zero detection logic receive and store the predetermined binary value. The monitoring of the ripple counter's digits from MSB to LSB prevents false detections of zero states in the ripple counter and allows the ripple counter to be extended to an arbitrarily large number of bits without sacrificing the maximum input clock frequency.

Abstract: A binary counter (60) provides for resolution doubling by producing a wavetrain (Q0) which represents the zero-order bit of the counter and has the same frequency as the clock input (REFCLOCK).

Abstract: An improved high speed two phase clock counter is disclosed. The counter includes a plurality of counter cells coupled to a transition pattern recognizer. Through the use of these elements a counter is provided that overcomes the power consumption and size limitation problems associated with known high speed counters.

Abstract: A frequency divider receives a first frequency signal and at least one clock signal of a sub-multiple of the first frequency. The first frequency signal charges a storage terminal once each first frequency cycle and the sub-multiple frequency signal discharges the storage temrinal once each sub-multiple frequency cycle. The discharged storage terminal sets the frequency divider output which is reset by the first frequency signal when the storage terminal is discharged. The sub-multiple frequency clock signal is employed to control the storage terminal instead of a feedback path from the output to increase the operating frequency of the divider.

Abstract: A universal shift register (200) utilizes a matrix (236-251) of high speed transmission gates to effect the various modes of register data manipulation in place of conventional operating mode selection logic gate elements. The shift register additionally includes apparatus allowing for the cascading of the register with units of similar design.

Abstract: The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flop has an exclusive OR gate input in which the T input is combined with the first output. The output of the exclusive OR is coupled to an internal node when the clock signal is at a first logic state, and isolated from the internal node when the clock signal is at a second logic state. The internal node is coupled to the first output when the clock signal is at the second logic sate and isolated from the internal node when the clock signal is at the first logic state. The first output signal is coupled to the second output signal when the clock signal is at the first logic state, and isolated from the second output terminal when the clock signal is at the second logic state.

Abstract: A circuit for generating clock and control signals from first and second asynchronous binary signals. The circuit generates first and second pulse signals responsive to the first and second asynchronous binary signals, a clock pulse signal responsive to the first or second pulse signal, and an identification control signal to indicate which of the two binary signals is responsible for the clock signal. The circuit is also responsive to the first and second pulse signals for generating an overlap control signal to indicate overlap in the first and second pulse signals.

Abstract: A frequency divider uses a single D flip-flop integrated circuit having an inverted output and an asynchronous clear input between which a feedback loop comprising a delay Tau is connected. The frequency divider receives a multi-GHz input frequency f.sub.1, and divides by any integer N to produce an output frequency f.sub.2 =f.sub.1 /N using the internal delay of the D flip-flop between input and output (CK-to-Q), and the internal delay between the asynchronous clear input to the output (CLR-to-Q). Solving for the amount of delay Tau in the feedback loop necessary to produce the desired integer, or divide ratio, N, according to a predetermined formula is also required. An integrated circuit D flip-flop manufactured by Gigabit Logic is preferably selected to provide the high input frequency capability, external to which is added the feedback loop for determining the divide ration desired. The divide ratio, or integer by which the input frequency is divided, includes the ability to divide by a non-2.sup.