Abstract: Embodiments relate to a clock counter, a method for clock counting, and a storage apparatus. The clock counter includes a clock frequency-dividing circuit, a plurality of counting circuits, and an adding circuit. The clock frequency-dividing circuit receives a clock signal and divide a frequency of the clock signal to output a plurality of frequency-divided clock signals, sum of number of pulses of the plurality of frequency-divided clock signals being equal to number of pulses of the clock signal. The plurality of counting circuits are connected to the clock frequency-dividing circuit, each of the plurality of counting circuits being configured to respectively count pulses for each of the plurality of frequency-divided clock signals and generate an initial count value. The adding circuit is connected to the plurality of counting circuits, and adds up the initial count values of the plurality of counting circuits to generate a target count value.

Abstract: The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates.

Abstract: A code generator includes an asynchronous counter that includes first to m-th flip-flops configured to asynchronously output first to m-th output signals in response to a first clock signal, the first to m-th output signals corresponding to first to m-th bits (m being an integer of 2 or more) of a code, respectively, and a synchronous counter that includes (m+1)-th to (m+n)-th flip-flops configured to synchronously output (m+1)-th to (m+n)-th output signals in response to the first clock signal, the (m+1)-th to (m+n)-th output signals corresponding to (m+1)-th to (m+n)-th bits (n being an integer of 2 or more) of the code. The asynchronous counter further includes first to m-th delay circuits configured to respectively delay the first to m-th output signals such that the first to m-th bits of the code are output together at the same time when the (m+1)-th to (m+n)-th bits are output.

Abstract: Methods and devices for transmitting a continuous bit stream in a digital network non-synchronous with the bit stream are disclosed. In one aspect, the method includes digitizing a continuous bit stream implemented by a transmitting apparatus and restoring the continuous bit stream implemented by a receiving apparatus. A processor of the transmitting apparatus digitizes the initial continuous bit stream into a binary data sequence to be transmitted at a nominal frequency corresponding to a set clock period, the binary data to be transmitted being encapsulated in at least one transport frame sent to the receiving apparatus. The digitization includes estimating a mean emission clock period value of the data sequence, and inserting, in a predetermined field of the transport frame, information making it possible to restore, in the receiving apparatus, the mean emission clock period value of the data sequence.

Abstract: A circuit includes a first power node configured to carry a voltage K·VDD, a second power node configured to carry a zero reference level, an output node, K P-type transistors serially coupled between the first power node and the output node, and K N-type transistors serially coupled between the second power node and the output node. Gates of the K P-type transistors are configured to receive biasing signals set at one or more voltage levels in a manner that one or more absolute values of source-gate voltages or absolute values of drain-gate voltages are equal to or less than VDD. Gates of the K N-type transistors are configured to receive biasing signals set at one or more voltage levels in a manner that one or more absolute values of gate-source voltages or gate-drain voltages are equal to or less than VDD.

Abstract: A counter circuit includes two pairs of registers configured to swap contents based on a timer overflow or underflow condition. The counter circuit also includes a waveform generator that generates a composite pulse width modulated signal with a period and duty cycle specified by values stored in the registers. A demultiplexing circuit generates first and second signals from the composite signal.

Abstract: A counter array and an image sensor including the same may be provided. The counter array may include a controller and a plurality of counter units. The controller may output an operation control signal and a direction indication signal. The counter units hold previous output values or may perform a counting operation in response to the operation control signal and may perform an up-count operation or a down-count operation in response to the direction indication signal when performing the counting operation.

Abstract: This invention provides a circuit and a method for programmable counters. It consists of a circuit and a method for unique programmable counters that provide half-integral as well as integral steps, such as 1.5, 2, 2.5, 3, 3.5, 4. This circuit and method are the first implementations of providing programmable counting with half-integral steps. The circuit and method of this invention can be extended via the cascading of toggle flip flops at the front end of the circuit of this invention. This provides the ability to enhance the speed of normal integral step counting applications. In addition, the cascading of the multiple copies of the circuit of this invention provides the ability to provide other fractional programmable counters. A key advantage of this invention is that the method of this invention is general enough to use any other type of counter sub-component beside the binary counter sub-component of this invention.

Abstract: Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.

Abstract: A high speed digital counter consists of a chain of asynchronous counter cells. Each cell includes a flip-flop with a master latch and a slave latch and a clock gating circuit. The clock gating circuit derives an enable input from an output of the master latch.

Abstract: A counter stage generally comprises a flip-flop and a reset circuit. The flip-flop may be configured to toggle a flip-flop signal between a first and a second state in response to a count signal applied to a clock input to effect a counting operation. The reset circuit may be configured to reset the counter stage to a predetermined state without changing the state of the flip-flop signal.

Abstract: A conventional up/down Gray code counter has both a logic circuit section for up counting and a logic circuit section for down counting, and thus has a large circuit scale. To overcome this inconvenience, an up/down Gray code counter of the invention has a one-way Gray code counter that can count only in one, up or down, direction and a highest bit selecting circuit that receives the highest bit of the data output from the one-way Gray code counter and that then outputs the bit selectively either intact or after inverting it.

Abstract: A system and a method are characterized in that the method of detection can be configured by varying a size and/or a position of a time slot to be taken into consideration for the detection and/or by varying relevant bits of the counts to be compared. This makes it possible to individually adapt the detection method to various or varying requirements at any time and with a minimum of expenditure required.

Abstract: A counter for synthesizing clock signals with minimal jitter. The inventive counter has a first counter stage; a look-ahead circuit input connected to said first counter stage; and a selection circuit for choosing between an output of said first counter stage and an output of said look-ahead circuit as an output of said counter. In the specific embodiment, the first counter stage is adapted to receive a first clock signal having a frequency of N cycles per second and output a second clock signal having a frequency of M cycles per second. The first counter stage includes an accumulator having a rollover point at which an instantaneous count thereof exceeds the value of N−M. The look-ahead circuit determines for a present clock cycle the rollover point for a preceding clock cycle. The look-ahead circuit is a second counter stage adapted to ascertain whether the rising edge or the trailing edge of the second clock signal is closer to the rollover point and output an indication with respect thereto.

Abstract: Structure and method for counting a predetermined number of counts is provided. A count end value is identified which is greater than or equal to (not less than) the predetermined number of counts. The count end value is chosen such that it is representable by n symbols (designated n-1, n-2, . . . , m, m-1, . . . , 1, 0) where the most significant n-1 through m symbols are a first binary symbol and the least significant m-1 through 0 symbols are a different second binary symbol, for example "1"0 and "0". An n-symbol current count value (also representable by n-1, n-2, . . . , m, m-1, . . . , 1, 0 symbols) is initialized to a count start value which is equal to the count end value minus the predetermined number of counts, then as the counter counts, the current count value is incremented by one (or some other count increment) for each count or cycle of the counter. After each iteration (or before the next iteration of the counter cycle) each of the n-1, . . .

Abstract: Counter circuits causing no noise at the time of operation are provided. Three stage of D-type flip-flops (FF1 to FF3) are connected in series. A delay element (11) delays a signal (S2) that is Q output of the flip-flop (FF1) by a delay time (d2) to output a delay signal (S2D), and a delay element (12) delays a signal (S3) that is Q output of the flip-flop (FF2) by a delay time (d3) to output a delay signal (S3D). Here, the relationship among the delay time (d2, d3) and a clock cycle (Tc) is set so as to satisfy the condition of {Tc>d2>d3}. NOR gate for three inputs (G1) receives delay signals (S2D, S3D) and a signal (S4) i.e., Q output of the flip-flop (FF3), and performs NOR operation on these signals (S2D, S3D and S4), thereby outputting a signal (S1) to D input of the flip-flop (FF1).

Abstract: A synchronous counter circuit having a plurality of bit counting stages, each corresponding to a bit position for representing counts, from a least significant bit to a most significant bit. Each bit counting stage includes a flip-flip circuit and a synchronization circuit and each includes circuitry for receiving a pulse train clock signal, synchronously counting said clock signal and outputting an output bit signal corresponding to said counters' stage bit position. The bit counting stages are arranged in two groups, a reset group and a counting group, such that the output bit signal of said flip-flop circuit of the reset group synchronizes data propagation between each bit counting stage of the counting group.

Abstract: The present invention is directed to a circuit for detecting the end of a burst count in a semiconductor memory device. The circuit is responsive to a plurality of burst counter output bits and a plurality of burst length selection bits. The circuit is comprised of an array of individual semiconductor devices responsive to the burst counter output bits and the burst length selection bits for producing a transition in an output signal when the burst counter output bits are at a logical combination determined by the burst length selection bits. A method for detecting the end of a burst count in a semiconductor memory device is also disclosed.

Abstract: A high modulus counter is provided for receiving a counter enable (CE) signal which switches between digital states. The counter is a single load conditional look ahead counter having a carry chain isolated from a timing critical path. The counter includes one toggle flip-flop for receiving the CE signal. The flip-flop has a first output and a second output. The first output and the second output are connected to an even counter and an odd counter, respectively. Both the output of the first counter and the output of the second counter are received by each of a plurality of multiplexers which are controlled by the first output of the toggle flip-flop. In this way, the high modulus counter outputs and increments the pointer signals of the odd counter and the even counter, alternatively. The even and odd internal counters are initially set at zero and one, respectively, and each increments by two. A second flip-flop may additionally receive the external CE signal for synchronization.

Abstract: Improved PLL frequency synthesizer circuits, including a novel swallow counter, may be operated at high speeds without experiencing internal delays or malfunctions. The swallow counter supplies a modulus signal to a prescaler which is capable of selectively changing a frequency-dividing ratio of a frequency signal. The swallow counter includes a shift register, a counter, a count-up detector, a modulus signal generator, and a control circuit. The swallow counter is connected to the prescaler and the program counter, and is capable of counting a frequency-divided signal based on a set value data and producing the modulus signal in response to a load signal after counting is completed. The swallow counter supplies the modulus signal to the prescaler and determines whether the set value data is data prepared to fix the frequency-dividing ratio.

Abstract: To implement a counter which can count clocks at high frequency exceeding the maximum operating frequency of the counter circuit, with a circuit with smaller circuit scale and lower power consumption, the present invention divides an externally set value HDB indicative of a count completion value into upper and lower bits, the upper bits being counted by using a counter circuit 12 with small circuit scale and power consumption, match being detected by a comparator 13. The clock signal is frequency divided to accommodate supply of high frequency clocks, and supplies it to the counter circuit 12. Then, the match detection signal of the upper bits is shifted in the number corresponding to the value of lower bits by a shift register 14 operating at a high frequency, and a count completion signal OUT is output.

Abstract: An asynchronous reading circuit improves reliability of data read from a binary counter. Count data generated by a binary counter 101 according to a counting clock is converted into a gray code by a gray encoder. The count data represented by the gray code is sampled by a sampling circuit according to a timing signal asynchronous with the counting clock. The sampled count data is decoded into binary count data by a gray decoder.

Abstract: A Gray Code counter includes first translator logic, binary incrementing/decrementing logic, second translator logic, and a clocked storage device. The first translator logic receives at an input a Gray Code number, I.sub.gray ?n:0! which the first translator translates into a binary number, I.sub.bin ?n:0!. The binary incrementing/decrementing logic either increments or decrements the binary number I.sub.bin ?n:0! to produce an incremented/decremented binary number, Z.sub.bin ?n:0!. The second translator logic translates the incremented/decremented binary number Z.sub.bin ?n:0! into an incremented/decremented Gray Code number, Z.sub.gray ?n:0!. The clocked storage device stores the incremented/decremented Gray Code number, Z.sub.gray ?n:0!. The clocked storage device also feeds the incremented/decremented Gray Code number, Z.sub.gray ?n:0!, to the input of the first translator logic.

Abstract: A synchronous counter performing a count operation in response to an input of a clock having a fixed frequency. The synchronous counter including a first transmission gate receiving a counter initialization signal and transferring the counter output signal to a carry output node when the counter initialization signal is received during a time period in which the external address signal is not received, and a second transmission gate receiving the counter initialization signal and transferring an address signal to the carry output node when said counter initialization signal is received during a time period in which the external address signal is received.

Abstract: A printer controller employs a microprocessor together with an application-specific-integrated-circuit (ASIC) to manage the operation of the printer. Among its functions, the ASIC manages memory access for the microprocessor. Either fast- or slow-clock microprocessors may be installed in the controller, but the ASIC requires a slow clock. When a fast-clock microprocessor is installed, the ASIC must divide the clock frequency to provide its own (slow) clock. Likewise, the use of a fast-clock microprocessor requires the ASIC to insert memory-cycle WAIT times, whereas a slow-clock microprocessor needs no WAITs. In a preferred embodiment of the invention, provision is made, during initial power-on RESET, to inform the ASIC which clock speed is being used. This information is conveyed by the configuration of the WAIT interconnection between ASIC and microprocessor, thus eliminating the need for a dedicated ASIC pin for this purpose.

Abstract: A clocking disable and enable circuit is provided having an input for receiving a clocking signal and another input for receiving a disable/enable signal. The disable and enable circuit provides a clocking disable/enable output from the circuit which is synchronized with the clocking signal during times in which the disable/enable signal is not activated. At times during which the disable/enable signal is activated, the clocking disable/enable signal transitions after at least a one half clocking period to a steady state value (either high or low voltage level). After the disable/enable signal becomes inactive again, clocking disable/enable signal automatically resynchronizes to the clocking signal. The clocking disable and enable circuit herein is well suited for providing glitch-free transition between a clocking state and a steady state to a synchronized digital or analog circuit which depends upon clocking synchronization for its operation.

Abstract: A data coincidence detecting circuit including a register for receiving n-bit data, a counter for counting up until 2.sup.n to compare the n-bit data with it, a comparator for comparing the outputs of the register and the outputs of the counter, respectively to generate a coincidence detecting signal, a mask portion connected to the output of the comparator for masking the period from a time point when the n-bit data is input to a time point when the input of data ends, and a logic circuit for logically adding the output of the mask portion and the output of the comparator to output the result.

Abstract: A controller for a clock generator. The controller of the present invention enables a clock signal to the internal clocking mechanism of a device. The controller of the present invention includes a detector and a timer. The detector has two input sense levels, such that it is capable of detecting a clock signal at two separate levels, the first level being larger than the second. Initially, the detector only detects when the clock signal is at a level greater than or equal to the larger of the levels. When this occurs, the timer begins counting. When the clock signal has been at or above the greater level for a predetermined time as determined by the timer, the detector enables the clock signal to go to the internal clocking mechanism. Thereafter, the detector only senses when the clock signal falls below the second level. Thus, the detector enables the clock signal to go to the internal clocking mechanism while the level of the clock signal is above the second level.

Abstract: A frequency divider state machine synchronously divides an input clock's frequency by 1.5. The clock divider circuit includes two storage elements which are clocked on different edges of the input clock signal. The outputs of the two storage elements are combined together using combinatorial logic, the results of which are provided back to the inputs of the two storage elements. Further, the two outputs of the memory storage elements are combined together to provide the desired output frequency. Preferably, the circuit is designed such that if either of the two memory storage elements powers up in an undesired state, the divide by 1.5 circuit will automatically transition to one of the desired states and continue to provide the output frequency at the desired divide by 1.5 clock frequency after the initial transition. The circuit can be implemented as a digital circuit in an ASIC, an LSI, or the like.

Abstract: A power-on reset circuit is used to initialize a system component upon power-on. The circuit comprises a digital circuit such as a shift register which exhibits a multiplicity of uncertain or random outputs upon power-on. These output are coupled to digital logic such as an AND gate which itself outputs a power-on reset signal when any of the outputs of the shift register is not a predetermined output level. Because the outputs of the shift register are uncertain or arbitrary upon power-on and there are a multiplicity of such outputs, it is not likely that all of the outputs of the shift register will coincidentally exhibit the predetermined levels upon power-on. Consequently, it is very likely that the AND gate will provide the power-on reset signal upon power-on to initialize the system component.

Abstract: A voltage to pulse-width conversion circuit includes a logarithmic clock generator for receiving a reference frequency signal and generating a logarithmic clock signal TCK; a counter for counting the number of clock pulses of the logarithmic clock signal TCK and outputting a digital value having a plurality of bits; a digital to analog converter for converting the digital value into an analog signal; and a voltage comparator for comparing the output signal of the digital to analog converter with a pulse width modulated control voltage and generating a pulse width modulated output signal with a predetermined duty ratio.

Abstract: A semiconductor integrated circuit of this invention includes an oscillation circuit formed on a semiconductor substrate, a frequency dividing circuit formed on the semiconductor substrate, for dividing a frequency of an oscillation output from the oscillation circuit, clocked inverters for selectively permitting one of an original oscillation frequency signal of the oscillation circuit and outputs of the frequency dividing circuit to pass therethrough, an output circuit for outputting a signal selected by the cocked inverters, and a frequency dividing circuit controlling NAND circuit for interrupting the operation of the frequency dividing circuit while the original oscillation frequency signal of the oscillation circuit is being output from the output circuit.

Abstract: A data detector comprises a counter having a plural-bit parallel output, compensation means for compensating a shift of output times of a low order bit and a high order bit of the counter caused by a carry signal from the low order bit to the high order bit, and detection means for detecting data of the low order bit and the high order bit of the counter compensated by the compensation means.

Abstract: A counter cell includes a latch circuit, control circuit, and a pull-up circuit. The laatch circuit is formed of a first clocked half-latch (32), a second clocked half-latch (34) and an inverter (INV1) for storing a binary output signal. The first clocked half-latch (32) is responsive to a first clockk phase signal for transferring the binary output signal from its input to its output. The second clocked half-latch (34) is responsive to a second clock phase signal for transferring binary output signal from its input to its output. The control circuit is responsive to an input complement signal for selectively passing the first clock phase signal to the first clocked half-latch so as to permit toggling the state of the binary output signal. The pull-up circuit is responsive to the binary output signal and the input complement signal for generating an output complement signal.

Abstract: A first frequency dividing circuit receives an input clock signal from an input terminal and divides the frequency of the input clock signal to produce a first signal which it supplies to an output terminal. A second frequency dividing circuit divides the frequency of the input clock signal to produce a second signal having the same frequency as the first signal but differing from the first signal in phase. The second signal controls a gating circuit. When switched on, the gating circuit connects the output terminal to the input terminal, or to an auxiliary power-supply or ground terminal, thereby deskewing the signal at the output terminal.

Abstract: A frequency divider includes at least three master-slave flip-flops which are connected to each other in stages, each stage including a master flip-flop and a slave flip-flop, to construct a 1/N frequency divider. At least two outputs whose periods are the same but phases are different are taken out from a master flip-flop and a slave flip-flop and combined to obtain a 1/(N/2) divided output signal. As a result, a divided output signal whose period does not vary with time is obtained and, when the N is an even number, an output signal with a duty ratio of 1/2 is obtained. A pulse signal former includes a differential amplifier to which two signals whose periods and pulse widths are the same but phases are shifted by a pulse width and an output obtained by comparing those two signals is output from the pulse signal former. As a result, an output signal whose duty ratio is 1/2 is obtained.

Abstract: Frequency division circuits in n stages sequentially 1/2-frequency-divide an input clock signal. Pattern generating circuit generates and issues a plurality of pattern data parallel to each other in synchronism with a frequency-divided clock from the final frequency division stage thereof. Multiplexing circuits in n stages are given a plurality of pattern data and multiplex input pattern data in each stage for each two data. Output clock signals of the n-th through first stage frequency division circuits are supplied to the first through n-th multiplexing circuits via respective delay circuits as multiplexing control clock signals. A retiming circuit is inserted in series to the input of at least one of the multiplexing circuits, and a multiplexing control clock signal applied to said one multiplexing circuit from the corresponding frequency division circuit is given to the retiming circuit as a retiming clock signal.

Abstract: In a non-impact printer apparatus, such as an LED printer, multiple bits of image data determining the on-time of each LED for generating a grey level pixel are latched into an appropriate data register from a data bus in accordance with a token bit that is passed along a shift register. The data register for each LED comprises a series of cascaded registers coupled as a ripple counter. Each of these registers stores a respective binary weighted data bit. In response to a clock signal at one of the clock inputs of one register the counter effectively counts down to a zero output condition and thereby directly controls LED enablement time.

Abstract: A frequency divider circuit having N flip-flops connected in series, includes a logic circuit for monitoring at least one of the outputs of the N flip-flops and halting the frequency division operation of a prior stage flip-flop when the value of the output which is monitored is equal to a predetermined value when a reset signal is input, and restarting frequency division operation when the reset signal is cancelled.

Abstract: A self-configuring clock interface circuit automatically configures itself according to the type of clock input signals applied to two input terminals interconnected with the interface circuit. The system includes a pair of counters connected to the input terminals and having their outputs connected to the two inputs of an Exclusive NOR gate which acts as a control device for the system. The output of the exclusive NOR gate is coupled to a 2:1 multiplex to control the interconnection of one or the other of two inputs to the multiplex circuit with a clock output for the interface circuit.

Abstract: An asynchronous ripple counter counts from a predetermined binary value to zero in response to an input clock signal. Zero detection logic is coupled to the ripple counter for detecting, from a most significant bit to a least significant bit of the ripple counter, when the counter has counted to zero. Both the counter and the zero detection logic receive and store the predetermined binary value. The monitoring of the ripple counter's digits from MSB to LSB prevents false detections of zero states in the ripple counter and allows the ripple counter to be extended to an arbitrarily large number of bits without sacrificing the maximum input clock frequency.

Abstract: An improved high speed two phase clock counter is disclosed. The counter includes a plurality of counter cells coupled to a transition pattern recognizer. Through the use of these elements a counter is provided that overcomes the power consumption and size limitation problems associated with known high speed counters.

Abstract: A universal shift register (200) utilizes a matrix (236-251) of high speed transmission gates to effect the various modes of register data manipulation in place of conventional operating mode selection logic gate elements. The shift register additionally includes apparatus allowing for the cascading of the register with units of similar design.

Abstract: Disclosed is a circuit which provides the controlled generation of tri-level digital signals utilizing Field Effect Transistors (FETs), as active elements. The stability of all three states is due to a unique feed-back technique, and utilization of the gate threshold characteristics of FETs. This circuit is controllable with either bi-level or tri-level digital signals, and is externally configurable as: a ternary up counter, providing the count sequence of 0,1,2,0 . . . ; a ternary down counter, providing the count sequence of 2,1,0,2 . . . ; a ternary shift left/right register; or as a ternary memory.

Abstract: Semiconductor components electrically connected in parallel are divided into a plurality of groups, with the control terminals of the semiconductor components constituting each group being connected in common to form a control terminal of the group, wherein the control terminals of the groups are mutually independent. A load current is limited by allowing specified ones of said semiconductor components to become conductive. Control of the load current is made possible without accompanying wasteful power dissipation.

Abstract: The level of a noise removed signal which is currently delivered is compared against the level of an input signal to be detected. If the non-coincidence therebetween continues over a given time interval, the level of the noise removed signal is inverted. In this manner, noises having stable levels which do not last over the given time interval are removed, thus deriving a favorable noise removed signal. In an alternative form, the level of a noise removed signal which is currently delivered is compared against the level of an input signal to be detected. When there is a non-coincidence therebetween which lasts over a first given time interval, when there is a coincidence which lasts over a second given time interval and when a third given time interval or more has passed, a noise removed signal is inverted.

Abstract: A voltage to pulse-width conversion circuit includes a counter which counts a reference frequency signal and produces a multi-bit digital value; a digital/analog converter which converts the digital value into an analog signal; and a voltage comparator which compares an output of the digital/analog converter with a control signal and produces a pulse width modulated output signal which has a predetermined duty cycle ratio.

Abstract: A pipeline binary updown counter is comprised of simple stages that may be readily replicated. Each stage is defined by the Boolean logic equationA.sub.n (t)=A.sub.n (t-1).sym.[(U.multidot.P.sub.n)+(D.multidot.Q.sub.n)]where A.sub.n (t) denotes the value of the nth bit at time t. The input to the counter has three values represented by two binary signals U and D such that if both are zero, the input is zero, if U=0 and D=1, the input is -1 and if U=1 and D=0, the input is +1. P.sub.n represents a product of A.sub.k 's for 1.ltoreq.k.ltoreq.-1, while Q.sub.n represents the product of A's for 1.ltoreq.k.ltoreq.n-1, where A.sub.k is the complement of A.sub.k and P.sub.n and Q.sub.n are expressed as the following two equationsP.sub.n =A.sub.n-1 A.sub.n-2 . . . A.sub.1Q.sub.n =A.sub.n-1 A.sub.n-2 . . . A.sub.1which can be written in recursion form asP.sub.n =P.sub.n-1 .multidot.A.sub.n-1Q.sub.n =Q.sub.n-1 .multidot.A.sub.n-1with the initial values P.sub.1 =1 and Q.sub.1 =1.

Abstract: A multi-sensor buffer interface that couples a multi-sensor inertial measment unit to a missile flight computer. The buffer converts input serial data into 16 bit parallel data and outputs messages of either 6 or 16 words. The buffer will provide computer requested data until the computer changes state of the controlling input signal or until communication between the buffer and the computer fails.

Abstract: A frequency divider uses a single D flip-flop integrated circuit having an inverted output and an asynchronous clear input between which a feedback loop comprising a delay Tau is connected. The frequency divider receives a multi-GHz input frequency f.sub.1, and divides by any integer N to produce an output frequency f.sub.2 =f.sub.1 /N using the internal delay of the D flip-flop between input and output (CK-to-Q), and the internal delay between the asynchronous clear input to the output (CLR-to-Q). Solving for the amount of delay Tau in the feedback loop necessary to produce the desired integer, or divide ratio, N, according to a predetermined formula is also required. An integrated circuit D flip-flop manufactured by Gigabit Logic is preferably selected to provide the high input frequency capability, external to which is added the feedback loop for determining the divide ration desired. The divide ratio, or integer by which the input frequency is divided, includes the ability to divide by a non-2.sup.