Abstract: The present disclosure provides a multi modulus frequency divider and an electronic device. The duty cycle adjusting circuit in the multi modulus frequency divider is configured to generate a second output clock signal according to a first output clock signal and an input modulus signal received by one or more frequency division units, the frequency of the second output clock signal is the same as that of the first output clock signal, and the duty cycle of the second output clock signal is different from that of the first output clock signal. The duty cycle of the clock signal output by the multi modulus frequency divider provided in the present disclosure is generally closer to 50%.

Abstract: A circuit for a ternary Domino reversible counting unit. The circuit includes a ternary adiabatic Domino D flip-flop, a ternary adiabatic Domino positive and negative circulation port, and a ternary adiabatic Domino T-operation circuit. The ternary adiabatic Domino T-operation circuit includes a first signal input end, a second signal input end, and a third signal input end, a selection signal input end, a signal output end, a first clock signal input end, and a second clock signal input end. The positive and negative circulation port includes a signal input end, a borrow terminal, a carry terminal, a first output end, a second output end, a first clock signal input end, a second clock signal input end, and a third clock signal input end. The D flip-flop includes a signal input end, a reset terminal, a set terminal, a reverse-phase set terminal, a signal output end.

Abstract: A data logging device tracks the operation of a vehicle or driver actions. The device includes a storage device, which may be removable or portable, having a first memory portion that may be read from and may be written to in a vehicle and a second memory portion that may be read from and may be written to in the vehicle. The second memory portion may retain data attributes associated with the data stored in the first removable storage device. A processor reads data from an automotive bus that transfers data from vehicle sensors to other automotive components. The processor writes data to the first memory portion and the second memory portion that reflect a level of risk or safety. A communication device links the storage device to a network of computers. The communication device may be accessible through software that allows a user to access files.

Abstract: A counter circuit is provided that can switch delay times by use of a simple circuit configuration. A counter circuit includes plural stages of flip flops connected in cascade, in which a flip flop in a first stage receives a clock from an oscillator as an input signal, and a flip flop in a given stage after the first stage receives a Q output of a preceding stage as an input signal, wherein all or part of the plural stages of flip flops receive a mode signal, and wherein each of the plural stages of flip flops divides by 2 a frequency of the received input signal for output as a Q output when the mode signal indicates a normal delay mode, and each stage of the flip flops that receives the mode signal allows through passage of the received input signal for output as a Q output when the mode signal indicates a delay shortened mode.

Abstract: A device for counting oscillations of an oscillating temporal signal. The device comprises means for counting all the alternate crossings of a positive threshold value and of a negative threshold value by a monitored time signal.

Abstract: A problem is to be solved that there is to be provided a plasma display device capable of generating driving signals with less variation in delay time and without carrying out any phase adjustment. There is provided a plasma display device including; a first display electrode; a second display electrode adapted to cause a discharge to occur between the first display electrode and the second display electrode; a first display electrode drive circuit for applying a discharge voltage to the first display electrode; and a second display electrode drive circuit for applying a discharge voltage to the second display electrode. The first display electrode drive circuit has a first output element for supplying a first electric potential to the first display electrode in accordance with a first input signal which is inputted by using a transformer.

Abstract: 1.

Abstract: A high speed digital counter consists of a chain of asynchronous counter cells. Each cell includes a flip-flop with a master latch and a slave latch and a clock gating circuit. The clock gating circuit derives an enable input from an output of the master latch.

Abstract: A bus bandwidth consumption profiler for measuring and reporting bus cycle utilization in a system having multiple bus masters, including master counters paired with the masters to count cycles of bus ownership, and a realtime counter to count elapsed cycles between profile events generated by either a realtime counter roll-over, or a system read signal. Upon a profile event, the counts of the master counters are simultaneously output to the system and the realtime count is determined. Alternatively, the profiler includes a total counter for counting the combined bus cycles owned by all masters, and fewer master counters than masters, each configurable to count a selected master. Upon a profile event, the counts of the master counters, the total counter, and the realtime counter are simultaneously output to the system. Accordingly, the bandwidth consumption of the selected masters and the combined, non-selected masters, can be calculated using fewer counters.

Abstract: A counter stage generally comprises a flip-flop and a reset circuit. The flip-flop may be configured to toggle a flip-flop signal between a first and a second state in response to a count signal applied to a clock input to effect a counting operation. The reset circuit may be configured to reset the counter stage to a predetermined state without changing the state of the flip-flop signal.

Abstract: A high speed digital counter consists of a chain of asynchronous counter cells. Each cell includes a flip-flop with a master latch and a slave latch and a clock gating circuit. The clock gating circuit derives an enable input from an output of the master latch.

Abstract: An N-bit binary synchronous counter includes K counter stages, with each stage including N/K flip-flops or other suitable storage elements. A given one of the counter stages receives a carry-in signal generated by another counter stage or by a carry logic circuit. The given counter stage includes a selection circuit for selecting one of two precomputed values for application to an input of a storage element in that stage based on a value of the carry-in signal. The selection circuit may include a two-input multiplexer for each of the N/K storage elements of the given counter stage. The jth multiplexer includes a first input coupled to an output of the jth storage element, and a second input coupled to an output of a logic circuit. The logic circuit generates a logic function based on the output of the jth storage element and other lower significant storage elements in the stage.

Abstract: A counter operated on the 2-phase clock which divides a lag time occurring in shift circuits into two parts, one being on the basis of a first clock and the other being on the basis of a second clock, the lag time in each part being independently accumulated so as to diverge the lag time, thereby speeding up the operation of the counter.

Abstract: A method for initializing a network having a plurality of network subscribers being capable of acting as masters, includes assigning the master function to the network subscriber being capable of acting as a master that is turned on first. In the event of a collision when the master function is assigned substantially simultaneously to a plurality of substantially simultaneously turned-on network subscribers, a random value that differs in magnitude is generated in all of these network subscribers. Finally, the network subscriber that has generated the highest or the lowest value is assigned the master function.

Abstract: A circuit having a delay circuit provided with a gate for converting the output signal of an SR flip-flop into a signal with a delay equal to or more than the clock pulse width enough for count operation and leading the logical addition between the signal and system clock and the logical multiplication between the signal and counter write signal to the direct reset input of a transparent latch 7 and for realizing read-on-the-fly or write-on-the-fly operation even if timer input does not synchronize with the system clock.

Abstract: A shift count confirmation shift register capable of receiving and storing logic values and sequentially providing representations thereof at the storage register output, as well as providing a shift complete signal at a confirmation signal output upon the completion of the shifting of these logic states stored therein.

Abstract: A frequency divider includes at least three master-slave flip-flops which are connected to each other in stages, each stage including a master flip-flop and a slave flip-flop, to construct a 1/N frequency divider. At least two outputs whose periods are the same but phases are different are taken out from a master flip-flop and a slave flip-flop and combined to obtain a 1/(N/2) divided output signal. As a result, a divided output signal whose period does not vary with time is obtained and, when the N is an even number, an output signal with a duty ratio of 1/2 is obtained. A pulse signal former includes a differential amplifier to which two signals whose periods and pulse widths are the same but phases are shifted by a pulse width and an output obtained by comparing those two signals is output from the pulse signal former. As a result, an output signal whose duty ratio is 1/2 is obtained.

Abstract: A pair of control transistors and a pair of storage transistors have their collectors coupled to a current source. The emitters of the storage transistors are grounded and the emitters of the control transistors are coupled to the bases of the storage transistors. The control transistor collector and base electrodes are cross-coupled, and the storage transistor collector and base electrodes are also cross-coupled. The emitter of each control transistor is connected to the collector of the associative storage transistor through a respective resistor. Two diodes in series connect the collectors of the control transistor, and a command transistor having a grounded emitter electrode, drives the common node of the diodes.

Abstract: A universal shift register (200) utilizes a matrix (236-251) of high speed transmission gates to effect the various modes of register data manipulation in place of conventional operating mode selection logic gate elements. The shift register additionally includes apparatus allowing for the cascading of the register with units of similar design.

Abstract: A data conversion circuit is constructed in such a manner that a plurality of flip-flop series, each including tandem connected master/slave flip-flops, are provided and driven by plural phase numbers of clock signals which have no overlap therebetween, so that a parallel data is obtained with a serial data supplied to the flip-flop series, or a serial data is obtained with a parallel data supplied to the flip-flop series. The clock signals employed here have no overlap between each of the corresponding phases of the signals.

Abstract: A drive circuit for producing scanning pulses to successively select row or column conductors of a matrix display device of the type having an active element provided for each display element in the matrix, the drive circuit comprising a shift register made up of a set of cascade-connected master-slave flip-flops, with both the master outputs and the "slave" outputs being utilized to form the scanning pulses. The number of flip-flop stages required is reduced by 1/2, by comparison with prior art drive circuits using master-slave flip-flops, and the frequency of the clock pulse signal required to drive the shift register is 1/2 of that required in the case of a prior art circuit.

Abstract: A drive circuit for sequentially driving electrodes of a matrix display device such as a liquid crystal display panel comprises a shift register divided into a plurality of groups of shift register stages and means for selectively applying a first clock signal and a second signal to the groups of stages, so that the groups become successively operative and so that power consumption of the currently inoperative groups is minimized. The second signal can comprise a low-frequency refresh clock signal, in the case of a dynamic type of shift register, or a DC potential in the case of static-type shift registers. During changeover between adjacent groups of shift register stages, the first clock signal is applied simultaneously to both groups, in order to ensure stable operation.

Abstract: An up/down counter device includes a D-type flip-flop circuit for producing a count signal of the 0th bit in synchronism with a clock signal, and 1st to n-th flip-flop circuits for producing count signals of the 1st to the n-th bits in synchronism with a clock signal. The first logic circuit is connected between the output of the D-type flip-flop circuit and the JK terminals of the first flip-flop circuit. The first stage logic circuit includes a first logic circuit section supplied with an up/down mode signal and the output signal of the D-type flip-flop circuit, and a second logic circuit connected in series with with the first logic circuit. Each of the 2nd to the n-th stage logic circuits includes a first logic circuit which is connected between the output terminal of the prestage flip-flop circuit and the JK terminals of the post stage flip-flop circuit, and a second logic circuit section connected to the first logic circuit.

Abstract: A multistage counter circuit comprising a plurality of counters connected in cascade, each providing a carry signal and having signal logic levels at an output of each stage inverted by main clock pulses and sub clock pulses, and means including a flip-flop connected at the output of each stage for synchronizing the carry signal of each stage with the main clock pulses to generate a carry signal to a succeeding stage unafffected by delays in the carry signal of a preceding stage.

Abstract: An electronic frequency divider circuit, particularly well-adapted to implement odd-number counters, comprising a multiplicity of switched-latch stages, and in the case of an odd-number counter, further including a bypass circuit stage. Each switched-latch stage comprises a first transmission gate and two inverters configured as a latch circuit, and a second transmission gate for coupling the latch circuit to a previous stage. Even-number divider circuits may be implemented using only pairs of switched-latch stages without the bypass circuit.

Abstract: An integrable semiconductor circuit for a multi-stage frequency divider having a number of master-slave flip-flop cells constructed in current mode logic forming the individual divider stages which are connected in series to a supply voltage and which are accordingly at different levels of the supply voltage has an input stage to which an input signal at an input frequency, and the inverse thereof, are supplied. The input stage is in the form of a differential amplifier having two identical transistors which are connected to a constant current source. The differential amplifier forms the first divider stage, that is, the first master-slave flip-flop, in combination with a first network including a number of transistors and load resistors. The further divided stages do not require an input circuit, therefore each subsequent stage includes only a network corresponding to the network of the first stage.

Abstract: A master and a slave counter have their outputs coupled to an exclusive OR gate which in turn, supplies the D input of a flip-flop. Clock pulses are coupled to the slave counter through an AND gate which is enabled by the Q output of the flip-flop. Clock pulses to the slave counter are inhibited upon occurrence of an output therefrom and until a succeeding output of the master counter occurs, at which time clock pulses are again supplied to both the slave counter and the master counter to synchronize the operation thereof.

Abstract: An improved counter wherein consecutively cascaded flip-flops of the prior art are divided into two groups. A first detector produces a first signal in response to a predetermined set of flip-flop states of the first group. A second detector produces a second signal in response to a predetermined set of flip-flop states of the second group. A third detector produces a count output in response to simultaneous existence of the first and second signals. The output from the first group is arranged in phase so that the second signal may be produced before the count output is produced, by applying an inverted output of the first group to the input of the second group.

Abstract: There is shown and described a new and unique counter mechanism or circuit which includes feedback latches, in cascade, and which monitors a "carry-in" signal which selectively causes the latch to toggle. When the contents of the latch is a binary 1, the carry-in signal propagates through the counter as a "carry-out" signal. Counting by the circuit occurs when the count input and carry-in signals are active.

Abstract: Signal level control for an amplifier or the like is provided by a binary counter which counts upward when first operated, and which thereafter counts up and down if continually operated. If the operated counter is stopped after counting up, it counts up when operated again. If the operated counter is stopped after counting down, it counts up when operated again. A digital to analog converter can provide a single control signal from the counter. The user is always assured that the single control signal will increase when the counter is operated again following a prior operation in either direction.

Abstract: A coaxial high voltage, high current switch having a solid cylindrical cold cathode coaxially surrounded by a thin hollow cylindrical inner electrode and a larger hollow cylindrical outer electrode. A high voltage trigger between the cathode and the inner electrode causes electrons to be emitted from the cathode and flow to the inner electrode preferably through a vacuum. Some of the electrons penetrate the inner electrode and cause a volumetric discharge in the gas (which may be merely air) between the inner and outer electrodes. The discharge provides a low impedance path between a high voltage charge placed on the outer electrode and a load (which may be a high power laser) coupled to the inner electrode. For high repetition rate the gas between the inner and outer electrodes may be continuously exchanged or refreshed under pressure.