Abstract: A shift frequency demultiplier includes: an inverter; N-2 registers; and N-4 OR gates; wherein an output terminal of the No. N-2 register is connected to an input terminal of the inverter, an output terminal of the inverter is connected to an input terminal of the No. 1 register and input terminals of the OR gates; the output terminal of the No. 1 register is connected to another input terminal of the No. 1 OR gate, the output terminal of the No. N-4 register is connected to another input terminal of the No. N-4 OR gate; an output terminal of the No. 1 OR gate is connected to the input terminal of the No. 2 register, an output terminal of the No. N-4 OR gate is connected to the input terminal of the No. N-3 register whose the output terminal is connected to an input terminal of the No. N-2 register.

Abstract: Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.

Abstract: An A/D conversion apparatus includes an N-stage pulse circulating circuit including N (N is a natural number, N?3) inverting circuits connected in a ring shape, the inverting circuits delaying an input pulse signal by a delay time corresponding to an amplitude of a separately input analog input signal, and outputting inverted pulse signals obtained by inverting the pulse signal, a counter unit that counts a number of circulations by which the pulse signal has circulated in the pulse circulating circuit within a predetermined time based on the inverted pulse signal output from one of the N inverting circuits, and a switching unit that switches an output destination of the inverted pulse signal, which is output from an inverting circuit of an Mth (M is an odd natural number, 1?M?N?1) stage of the pulse circulating circuit, according to a change in an operation environment.

Abstract: A shift frequency demultiplier with automatic reset function is N-frequency demultiplication (N>2) and includes N-1 registers connected with each other and defined from a first register to an (N-1)th register. Each of the registers has an input end, an output end, a reset end and a clock end. For the registers from the first register to the (N-2)th register, the output end of every register is connected with the input end of a next register adjacent thereto, the output end of the (N-1)th register is connected with the input end of the first register by a reverser. The reset end of the (N-1)th register is connected with a system reset signal end. The system reset signal end logically multiplied by the output end of the (N-1)th register is connected with the reset ends of the registers from the first register to the (N-2)th register.

Abstract: A technique includes driving a node of a stage of a ring counter to a predetermined signal state; and clocking the ring counter to cause the signal state to propagate to at least one additional stage of the ring counter to initialize the ring counter with a reset sequence.

Abstract: A system includes a memory and a counter circuit associated with the memory and configured to receive a clock signal and a plurality of input bits, and configured to output a plurality of output bits to the memory. The counter circuit includes a first counter configured to receive a part of the plurality of input bits and to output a part of the plurality of output bits and a first signal, a control circuit configured to receive the clock signal and the first signal, and to output a second signal, and a second counter configured to receive another part of the plurality of input bits and the second signal, and to output another part of the plurality of output bits.

Abstract: A shift frequency demultiplier with automatic reset function is N-frequency demultiplication (N>2) and includes N-1 registers connected with each other and defined from a first register to an (N-1)th register. Each of the registers has an input end, an output end, a reset end and a clock end. For the registers from the first register to the (N-2)th register, the output end of every register is connected with the input end of a next register adjacent thereto, the output end of the (N-1)th register is connected with the input end of the first register by a reverser. The reset end of the (N-1)th register is connected with a system reset signal end. The system reset signal end logically multiplied by the output end of the (N-1)th register is connected with the reset ends of the registers from the first register to the (N-2)th register.

Abstract: A counter circuit adding a first value indicated by a plurality of bits and a second value in response to a clock signal, a first part of the plurality of bits being lower order than a second part of the plurality of bits, the counter circuit including a first counter configured to add the first part of the plurality of bits and the second value in response to the clock signal to output a third value regarding a result of adding the first and the second values, a second counter configured to add the second part of the plurality of bits and a fourth value in response to the clock signal, and a clock transmission control circuit coupled to the first and second counters to receive the clock signal and the third value, and to control whether or not to supply the clock signal to the second counter in accordance with the received third value.

Abstract: A frequency divider comprises a cascade of at least two triggered delay elements (FF1, FF2, . . . ), a reference frequency input (FIN) and a clock output (FOUT). The triggered delay elements (FF1, FF2) are configured to forward a state of an input signal at a respective data input (D1, D2) to a respective data output (Q1, Q2) either for a rising clock edge of a clock signal at a respective clock input (C1, C2) or for a falling clock edge of the clock signal, depending on a control signal at a respective trigger control input (PH1, PH2). Clock inputs (C1, C2) of the delay elements (FF1, FF2) are coupled to the reference frequency input (FIN). The data input (D1) and the trigger control input (PH1) of the first delay element (FF1) of the cascade are coupled to the data output (Q2, QN) of the last delay element (FF2, FFN) of the cascade. The data input (D2, . . . ) and the trigger control input (PH2, . . . ) of further delay elements (FF2, . . . ) of the cascade are coupled to the data output (Q1, . . .

Abstract: Reduction in power consumption of a counter circuit for continuous operation is demanded. Therefore, provided is a counter circuit including: a first counter of m bits for counting and storing a value of a predetermined bit width according to an input clock; a clock transmission control circuit for controlling whether to transmit the input clock based on a value output according to a counting result of the first counter; and a second counter of n bits for counting and storing another value of the predetermined bit width according to the input clock transmitted from the clock transmission control circuit.

Abstract: A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal and outputs a signal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals.

Abstract: A multi-bit counter is provided. The multi-bit counter includes a plurality of asynchronous base counter cells coupled in series, the asynchronous base counter cells having a plurality of input terminals. The multi-bit counter also includes at least one logic gate coupled to at least one of the input terminals of at least one of the plurality of asynchronous base counter cells, a reload signal being input into the asynchronous base counter cells, a clock signal being input into the asynchronous base counter cells, and an input voltage being input into the asynchronous base counter cells, wherein the multi-bit counter is synchronous with the clock signal.

Abstract: A high performance, low power up/down counter is set forth. The counter presented is controlled by two clock pulses, an up pulse and a down pulse, and updates all bits of the counter in parallel. These bits are then latched using a scannable pulsed limited output switching dynamic logic latch. By using a limited switch dynamic logic latch, the counter is able to utilize the speed of dynamic logic without requiring the traditional dynamic logic power. The area saved and speed gained by using a dynamic latch is significant compared to a typical edge-triggered flip-flop. Additionally, by computing all the next count state bits in parallel, the counter reduces an overall count computation delay by eliminating the counter ripple.

Abstract: A latency counter of a semiconductor device comprises a single cyclic signal generator and a command delay circuit. The single cyclic signal generator cyclically produces 0-th to n-th base signals based on an internal clock signal. The command delay circuit comprises 0-th to n-th latch elements and latches an internal command by means of a p-th latch element (p is an integer; 0?p?n) in response to a q-th base signal (q is an integer; 0?q?n) and to output the latched internal command corresponding to the latency timeout signal therefrom in response to a r-th base signal (r is an integer; 0?r?n), where r=q+s if q+s?n, while r=q+s?(n+1) if q+s>n, s being a natural number equal to or less than n.

Abstract: A glitchless T length pulse is generated by coupling a trigger signal and the latched output of a counter. The trigger signal initiates the start of the T length pulse, and the latched output of the counter initiates the end of the T length pulse after counting up a duration of T from a number of clock cycles of a clock signal. Latching the output of the counter prior to terminating the T length pulse eliminates glitches. Accuracy of the count determining the length of the T length pulse may be increased by latching the trigger signal with the clock signal to generated a synchronized trigger signal, and using the synchronized trigger signal to initiate the T length pulse.

Abstract: Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.

Abstract: A counter circuit is provided which is particularly suitable for controlling cyclical events. The counter consists of a chain of logic elements 160, 167, 164 which sequentially pass a ‘1’ along the chain in response to a clock signal. Each element is also responsive to a respective select signal and, if selected, behaves like a latch, whereas if unselected it behaves as if it were not there.

Abstract: An initial value generation circuit generates an initial value taking into consideration the a time delay when a signal is transmitted through the signal wires between a pilot device and other devices, and a processing delay caused in respective devices. When a device receives a system synchronizing signal form another device, the device sets an initial value in a counter. Thereby, the counter value of a counter in a pilot device and counter values of counters in the other devices are made to coincide with each other.

Abstract: A pulse phase difference encoding circuit includes a ring delay pulse generating circuit which is formed by a NAND circuit and inverters. Signal lines connecting the NAND circuit and the inverters have uniform load capacity to obtain even time resolutions. The NAND circuit is formed by component transistors one of which is larger in size to have the same delay time as the other inverters. A dedicated latch buffer for applying steeply changing drive pulse to a pulse selector is provided to prevent difference in the measurements. A specific value is outputted in the event of the overflow or underflow of the measurement time to obtain a constant digital output.

Abstract: A ring counter includes a plurality of latches forming a shift register. A single bit is sequentially clocked through the shift register, so that only one output is active at any time. A logic circuit is connected to the outputs, and monitors the number of outputs which are active. If more than one output should somehow become active at one time, such as during power up, a reset signal is immediately generated to reset a single bit of the counter active. An external reset signal can also be applied to the logic circuit to force a reset of the counter.

Abstract: A digital sequencing apparatus produces a series of contiguous enable gates or strobe signals. The apparatus includes an even number, and at least two alternating stages of cross-coupling NOR gates alternating with cross-coupled NAND gates where one of the cross-coupled NOR gates in each stage has a merged AND gate at one input and one of the NAND gates in each stage has a cross-coupled OR gate at one input. This apparatus produces contiguous enable gates in response to complementary clock inputs to each of the stages upon the input of a start signal to the first two stages of the apparatus.

Abstract: A multiple phase clock generator includes a ring of an even number of phase cells, each phase cell generating a separate phased clock signal. Each phase cell supplies its phased clock signal and a prebias output signal in response to concurrent assertion of an enable signal and a prebias output signal from a preceding phase cell on the ring. Enable signals supplied to each phase cell around the ring are asserted and deasserted in response to state changes in a master clock signal, enable signals supplied to non-adjacent phase cells being provided concurrently. When initialized with one phase cell asserting its phased clock signal and prebias output signal, each transition of the master clock signal causes a next phase cell on the ring to supply its phased clock output signal.

Abstract: A twisted ring counter has a NOR gate with inputs from outputs of the last two stages thereof to detect and be activated by a combination of outputs which is found in all modes of operation of the counter. When activated by the combination, the gate provides an output to reset the counter to an all-ZEROs condition.

Abstract: Valve packing system comprising a compacted body of expanded graphite material having an apparent bulk density 1.6 to 2.0 times its apparent bulk density prior to compaction and positioned in stuffing box with zero clearance between each of valve stem and said stuffing box, and a pair of flat carbon guide rings retaining said compacted body and machined to close internal clearance with said valve stem and close external clearance with the internal walls of said stuffing box.