Abstract: The present invention relates to a SET/RESET latch circuit a Schmitt trigger circuit, and a MOBILE based D-type flip flop circuit and frequency divider circuit using the SET/RESET latch circuit and Schmitt trigger circuit. The SET/RESET latch circuit is configured with CML-type transistors and negative differential resistance diodes. The SET/RESET latch circuit can be applied to very high speed digital circuits.

Abstract: CMOS semiconductor pass-transistor logic circuitry (200) is disclosed, comprising pass transistor circuitry (204, 212, 218), and tunneling structure circuitry (228) coupled to the pass transistor circuitry; where the tunneling structure circuitry is adapted to hold a node (222) voltage stable by compensating a leakage current (302) originating from said pass transistor circuitry.

Abstract: A high-speed, compact, edge-triggered flip-flop circuit is provided which includes an input circuit section, a latch circuit section and an output circuit section. The input circuit section includes at least one transistor such as a field-effect transistor (FET) which determines the logic function of the flip-flop such as D, S-R, or T, and provides a first stage of latching. The input circuit section receives the logic control signals such as D, S-R, or T, and a clock signal. In one embodiment of the invention, the latch circuit section includes two series-connected negative differential resistance (NDR) diodes. In this embodiment, a common terminal of the two NDR diodes is connected to the data output of the input circuit section and to the data input of the output circuit section.

Abstract: A system for storing digital data includes an input circuit, a clock circuit, and a bridge. The input circuit is coupled to receive an input signal. The clock circuit receives and transmits a clock signal. The bridge stores the digital data and includes a plurality of negative differential resistance devices. The bridge connects to the input circuit and the clock circuit.

Abstract: A high speed digital static shift register includes a series-connected pair of resonant tunneling diodes (RTDs) 22, 24 to achieve a bistable operating state. A clocked switch 20 provides the means of setting the binary state of this bistable pair. In order for one bistable pair to drive a following pair, a method of providing isolation and gain using a buffer amplifier 26 between the two pairs of RTDs is also provided. In one embodiment, the buffer amplifier comprises enhancement FET 30 and depletion load FET 28.

Abstract: A shift register having a first bistable latching circuit operable for switching between a low voltage state and a high voltage state in response to receiving an input current and a first clock voltage pulse. A second bistable latching circuit operable for switching from said low voltage state to the high voltage state in response to receiving a switching current induced from the first bistable latching circuit and a second clock voltage pulse. A clock voltage pulse source operable for successively providing clock voltage pulses in phase sequence to the first and second bistable latching circuits.

Abstract: A sequential logic circuit includes N state hold circuit where N is an integer. Each of the state hold circuits has a first input terminal, a second input terminal and an output terminal. The state hold circuits are cascaded via the respective first input terminals. The second input terminals of the state hold circuits receive a first clock signal. The first input terminal of one of the state hold circuits in a first stage receives a data signal. The output signal is obtained via the output terminal of one of the state hold circuits in a final stage.

Abstract: A power-on reset circuit includes a differentiator circuit, a sample-hold circuit and a reset signal generating circuit. The differentiator circuit differentiates a clock signal from an oscillator after a power supply is applied to a power supply terminal. The sample-hold circuit samples a power component only from the output of the differentiator circuit. When the power component exceeds a threshold voltage of the reset signal generating circuit, the reset signal generating circuit generates and provides a reset signal for a logic circuit during a certain period.

Abstract: A stepping counter using resonant tunneling diodes (RTDs). The stepping counter utilizes the periodic hysteresis characteristic of a device with folding characteristics such as a RTD connected in series with a resistance. The series circuit is biased in the upper portion of the hysteresis loop through a current source in the case of a step-up counter. When a positive-going pulse is applied through a capacitor across the series RTD-resistor circuit, the operating point jumps to the next highest stable operating point in the hysteresis loop responsive to the leading edge of the pulse, but is prevented from returning to the original operating point at the trailing edge of the pulse because of the hysteresis.