Abstract: Presented herein are systems, methods, and nonvolatile computer-readable storage devices for informing a particle event processor of a particle detector of events arising within a sensor period. The systems, methods, and nonvolatile computer-readable storage devices involve the generation of a sensor data set detected by a particle event sensor and representing the events arising within the particle detector during the sensor period. The systems, methods, and nonvolatile computer-readable storage devices also involve the compression of the sensor data set with a waveform compression technique to generate a compressed sensor data set, and the transmission of the compressed sensor data set to the particle event processor.

Abstract: The time base includes an oscillator generating a periodic signal, a frequency divider circuit formed by a division chain defining several division stages and a circuit for adjusting the divided frequency by inhibiting, in each inhibition period of a plurality of successive inhibition periods, an integer number of clocking pulses at the input of a given stage of the division chain. The time base is arranged to produce, in each inhibition period, a first real number corresponding to the real number of clocking pulses that must be removed to be precise and the adjustment circuit is arranged to calculate, in each inhibition period, a second real number equal to the addition of the first real number and the fractional part of the second real number obtained in the preceding inhibition period, the integer part of this second real number defining the number of clocking pulses to be inhibited in each inhibition period.

Abstract: A system and method for slack determination in a logic integrated circuit. A launch pulse is input to a circular delay loop circuit. The leading edge of the launch pulse causes a pulse to circulate around the circular delay loop. The number of passes made through the loop by the circulating pulse is counted by a latch/counter circuit. A sample pulse is input to the latch/counter circuit to latch the number of pulse circulations at the leading edge of the sample pulse. The pulse circulation count provides delay information in the circuit that may subsequently be used to adjust a supply voltage in the integrated circuit.

Abstract: An N-bit binary counter includes N 1-bit counters together producing an N-bit binary word, and a count enable signal generator for generating count enable signals for each of the N 1-bit counters. The count enable signal generator includes multiple logic group/carry ripple devices, different ones of which receive different numbers of bits of the binary word and generate count enable signals for the same number of bits. The logic group/carry ripple devices also receive a carry ripple output signal from an adjacent logic group/carry ripple device and generate a carry ripple output signal for another adjacent logic group/carry ripple device.

Abstract: A multiple phase clock generator includes a ring of an even number of phase cells, each phase cell generating a separate phased clock signal. Each phase cell supplies its phased clock signal and a prebias output signal in response to concurrent assertion of an enable signal and a prebias output signal from a preceding phase cell on the ring. Enable signals supplied to each phase cell around the ring are asserted and deasserted in response to state changes in a master clock signal, enable signals supplied to non-adjacent phase cells being provided concurrently. When initialized with one phase cell asserting its phased clock signal and prebias output signal, each transition of the master clock signal causes a next phase cell on the ring to supply its phased clock output signal.

Abstract: A programmable logic array (PLA) is described, having an integral decoder for selecting individual product lines. The integral decoder receives an input address by way of a set of buffers, which can be disabled so as to disable the integral decoder in normal operation. The buffers can be tested in their disabled state by means of an extra product line and extra output line. The extra product line is coupled to all the bit lines and to the extra output line, but not to any of the other output lines; the extra output line is coupled to the extra product line, but not to any of the other product lines. The buffers are tested by applying a sequence of addresses to the buffers in their disabled state, and observing the extra output line.

Abstract: A programmable logic array (PLA) is tested by applying a sliding-ones pattern to the bit lines from a circular shift register, and individual product lines are selected by applying a sequence of addresses from a linear feedback shift register (LFSR) to an integral decoder. Both the circular shift register and the LFSR are controlled by a common clock signal, avoiding the need for special synchronizing logic between them. The sequence lengths of the circular shift register and the LFSR are chosen to be coprime numbers. Thus, after a predetermined number of clock beats, all the crosspoints in the AND plane will have been individually tested.

Abstract: The invention pertains to programmable fast logic.The logic gate of the invention comprises two parallel-mounted inverters comprising one transistor and one saturable load. The second inverter is powered through a transistor, the electrode gate of which, linked to the drain, is joined to the drain of the first inverter which may have additional inputs (OR function). A triplet of three series-mounted logic gates comprises a programming input at the third gate, a re-looping output and, in the case of a sequence of triplets, re-looping inputs at the first gate of the first triplet. A programmable logic circuit is obtained by a sequence of series-mounted triplets which are all looped back to the first gate of the sequence. The programming is obtained by placing one or two programming inputs at the logic 0 level.Application: Programmable frequency divider circuits in which the ratios follow one another, one by one.

Abstract: A drive circuit for sequentially driving electrodes of a matrix display device such as a liquid crystal display panel comprises a shift register divided into a plurality of groups of shift register stages and means for selectively applying a first clock signal and a second signal to the groups of stages, so that the groups become successively operative and so that power consumption of the currently inoperative groups is minimized. The second signal can comprise a low-frequency refresh clock signal, in the case of a dynamic type of shift register, or a DC potential in the case of static-type shift registers. During changeover between adjacent groups of shift register stages, the first clock signal is applied simultaneously to both groups, in order to ensure stable operation.

Abstract: Basic block shift registers are cascaded to form a fully programmable linear feedback shift register. Each of the basic block shift registers comprises a plurality of flip-flops, each of which includes control logic circuits. A polynomial equation is first fed into the linear feedback shift register for setting the respective flip-flops into predetermined logic states, which are used to encode messages to be shifted by the programmable linear feedback shift register. The number of flip-flops in the programmable linear feedback shift register can be varied, in accordance to the polynomial equation. Likewise, the polynomial equation also determines the number of times the programmable linear feedback shift register is to circulate the encoded messages.

Abstract: A CMOS dynamic circulating-one shift register (10) is disclosed. One stage of a conventional N-stage circulating-one shift register is modified to become a control cell (14) which performs two additional functions, referred to as AUTOSET and AUTOCLEAR, to guarantee the existence of a single circulating logic one, after power up or during long-term use. To perform the AUTOCLEAR function, the output (Q3) of the control cell is connected to the CLR inputs of each of the remaining stages (12.sub.1 -12.sub.N-1) comprising the shift register. Therefore, when Q3 becomes a logic one, the remaining Q outputs are automatically cleared. The Q output from the control cell is also fed back as the D input to the first stage of the shift register (12.sub.1) to continue the circulation process.

Abstract: A high-speed programmable timing generator in which a continuously cycling binary count is compared with an input data word. Predetermined bits, starting from the highest-order end of the counter, can be selectively inhibited to effectively vary the cycle period of the counter. The digital word with which the output of the counter is compared can be varied to set the reference phase of the output timing pulse stream. Further, fine delay adjustment of the phase of the output timing pulse stream is effected by a controllable phase-locked loop.

Abstract: Apparatus for storing a periodic signal and for recycling complete cycles of such stored periodic signal. Samples of a periodic signal are stored in a memory at a time commencing at the start of a cycle of the periodic signal. A first control signal is produced at the start of each cycle of the periodic signal. A second control signal is produced when a predetermined portion of the storage means is full. In response to the second control signal and one of the first control signals produced after the second control signal, a signal is produced indicating the portion of the memory having samples of complete cycles of the periodic signal stored therein, such indicating signal being related to the amount of samples stored in the predetermined portion of the memory plus the amount of samples stored in such memory between the time of the second control signal and the time of the one of the first control signals produced after the second control signal.