Abstract: There is provided an image recording apparatus having a housing having a front wall and a rear wall, and a right wall and a left wall defining an internal space of the housing, a sheet roll holder configured to hold a sheet roll, a supporting member configured to support the sheet roll, the supporting member extending in an axial direction of the sheet roll and being supported by the sheet roll holder, a sheet conveyer arranged in an internal space of the housing, the sheet conveyer being configured to convey a sheet unwound from the sheet roll, and a recording device configured to record an image on the sheet unwound from the sheet roll and conveyed by the sheet conveyer. The sheet roll holder is configured to be slidable with respect to the housing so as to be detachable from and attachable to the housing.

Abstract: Methods, systems, and computer readable media described herein can be operable to facilitate transitioning a device from a first state to a second state. A switch described herein allows for the use of an electronic circuit to perform the toggle and persistence functions while simultaneously giving more flexibility to the industrial design and physical switch implementation. The switch allows this preserving of the state using only a toggle on a voltage and thus allowing for a hardware only solution. The switch described herein allows for the use of smaller and less complicated mechanical switches allowing for more compact industrial designs. The switch uses a programmable voltage reference as a 1 bit non-volatile memory cell that is programmed by means of a logic pulse to the device. This allows a software independent setting of the state of the privacy switch. This state will remain through power cycles.

Abstract: A device for controlling a transfer of information from a plurality of electronic components through a communication bus to a host device, comprising a chain of processing blocks connected to the electronic components, each of the processing blocks associated with one, or a set, of the electronic components, which processing blocks are arranged such that during the transfer of information an authorization signal propagates through the chain of processing blocks and, when the authorization signal encounters a processing block associated with one of the electronic components or one of the sets of electronic components which contains an information value to be transferred, effecting the transfer of the information value through the communication bus to the host device. The processing blocks are arranged to coordinate their processing in accordance with a clock signal generated independent of a propagation status of the authorization signal within the chain of processing blocks.

Abstract: A design technique is disclosed that divides up a cellular power switch into different size segments. Each segment is driven by a different driver circuit. The selection of the combination of segments is made to minimize the combined conduction and switching losses of the power switch. For example, for very light loads, switching losses dominate so only a small segment is activated for driving the load. For medium and high load currents, conduction losses become more significant, so additional segments are activated to minimize the total losses. In one embodiment, the number of cells in the segments is binary weighted, such as 1×, 2×, and 4×, so that there are seven different combinations of segments. The drivers may be configured to achieve the same or different slew rates of the segments, such as to reduce transients. The segments may all be in the same die or a plurality of dies.

Abstract: A near field communication (NFC) device includes a resonator including an antenna and a matching circuit, a transmitter and a frequency detector. The transmitter generates a sensing voltage signal at the resonator. With respect to a plurality of measurement periods where each measurement period includes a turn-on period and a turn-off period, the transmitter is enabled to output a radio frequency (RF) signal to the resonator during the turn-on period and disabled during the turn-off period. The frequency detector detects a resonance frequency of the resonator based on the sensing voltage signal. The resonance frequency is accurately detected by measuring the resonance frequency during the plurality of measurement periods. In addition, the resonance frequency is efficiently detected by generating the sensing voltage signal using the transmitter established in the NFC device.

Abstract: Due to rapid advancement in computing technology of both hardware and software, the labor intensive sewing process has been transformed into a technology-intensive automated process. During an automated process, product materials may become wrinkled or folded, which can slow down the automated process or result in human intervention. Various examples are provided related to the automation of sewing robots, and removal of wrinkles from products. Images of material on a work table can be captured and analyzed to determine if there are wrinkles or folds in the product. The robot can remove the wrinkle or fold by manipulating the material through the use of end effectors such as, e.g., budgers.

Abstract: Systems and techniques are provided for presence and directional motion detection. Signals may be received from a sensor positioned in a structure. An indication of directional motion may be generated based on the signals from the sensor. The indication of directional motion may be generated without using signals from additional sensors. A control signal for a device in the structure may be generated in response to the indication of directional motion. The control signal may be sent to the device in the structure to be implemented by the device.

Abstract: Due to rapid advancement in computing technology of both hardware and software, the labor intensive sewing process has been transformed into a technology-intensive automated process. During an automated process, product materials may become wrinkled or folded, which can slow down the automated process or result in human intervention. Various examples are provided related to the automation of sewing robots, and removal of wrinkles from products. Images of material on a work table can be captured and analyzed to determine if there are wrinkles or folds in the product. The robot can remove the wrinkle or fold by manipulating the material through the use of end effectors such as, e.g., budgers.

Abstract: Method and device to manage a coiler apparatus associated with a distributor, in which there is at least an exit of the feeder of hot or cold semi-worked metal products, and with a reel, both being respectively moved with suitable controlled movement and rotation means, able to manage the coiling obtaining coils with desired characteristics.

Abstract: The present invention provides a CMOS GOA circuit. The first NOR gate (Y1) and the second NOR gate (Y2) are located in the input control module (1). The two input ends of the first NOR gate (Y1) respectively receives the stage transfer signal (Q(N?1)) of the GOA unit circuit of the former stage and the global signal (Gas), and the two input ends of the second NOR gate (Y2) respectively receives the first clock signal (CK1) and the global signal (Gas). When the global signal (Gas) is high voltage level, the all the scan driving signals (G(N)) of the respective stages are controlled to be raised up to high voltage levels at the same time, and meanwhile, both the first NOR gate (Y1) and the second NOR gate (Y2) are controlled to output low voltage levels to control the inverted stage transfer signal (XQ(N)) to be high voltage level.

Abstract: A device for recovering electric energy in a DC motor-driven electric vehicle. The device includes a battery; a first inverter; an inductor; a first rectifier bridge or a second inverter; a DC motor; a second rectifier bridge or a third inverter; and a charger. The anode and the cathode of the battery are connected to input ends of the first inverter, respectively. One output end of the first inverter is connected to one end of a primary coil of the inductor. Another output end of the first inverter is connected to one input end of the first rectifier bridge or the second inverter. Another end of the primary coil of the inductor is connected to another input end of the first rectifier bridge. The charger is connected to the anode and the cathode of the battery for supplying power from an external power supply.

Abstract: A device for recovering electric energy in an AC motor-driven electric vehicle. The device includes a battery, a single-phase or three-phase inverter, a single-phase or three-phase inductor, an AC motor, a rectifier bridge or a second inverter, and a charger. The anode and the cathode of the battery are connected to input ends of the inverter, respectively. An output end of the inverter is connected to the AC motor via a primary coil of the inductor. An output end of a secondary coil of the single-phase or three-phase inductor is connected to an input end of the rectifier bridge or the second inverter. Output ends of the rectifier bridge are connected to the anode and the cathode of the battery, respectively. The charger is connected to the anode and the cathode of the battery for supplying power from an external power supply.

Abstract: A fragment counting and control system, consisting of mechanical and electronic components such as a fragment counting execution mechanism, a sensor platform, various sensors, a signal counting and processing instrument, a timer, a motor driver and the like.

Abstract: A shift register is configured so that each of first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor, the second intermediate stage includes a control circuit which is (i) connected to the setting circuit of the second intermediate stage and (ii) supplied with a control signal, an operation period (i) starts at a time when a shift start signal supplied to an initial stage is activated and (ii) ends at a time when an output of a final stage changes from activation to inactivation, and when the clock signal supplied to the first input terminal of the second int

Abstract: A first calculation unit subtracts third digital data which indicates the minimum value of the duty ratio from first digital data which indicates the duty ratio of the PWM driving operation. A slope calculation unit generates slope data which is dependent on the temperature based upon second digital data which indicates the temperature. A second calculation unit multiplies the slope data by the output data of the first calculation unit. A third calculation unit sums the output data of the second calculation unit and the third digital data. A selector receives the output data of the third calculation unit and the third digital data, selects one data that corresponds to the sign of the output data of the first calculation unit, and outputs the data thus selected as a duty ratio control signal.

Abstract: A calibrated gate biasing circuit according to one embodiment includes a switched capacitor precision resistor; and a voltage reference. An electronic circuit for initiating a change in state of a host device, according to another embodiment, includes a counter coupled to a host device, the counter counting at a fixed interval, wherein the counter is reset to zero upon receiving a command from a remote device, wherein the count is compared to a reference value, wherein the host device changes states if the count matches the reference value, wherein operation of the counter continues in spite of an interruption in power supply from a power source.

Abstract: A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters.

Abstract: A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters.

Abstract: An output timing control circuit of a semiconductor apparatus includes a delay amount counter block configured to count a delay amount of an output reset pulse signal based on an external clock signal and output a first counting code, wherein the delay amount counter block is configured to control the delay amount of the output reset pulse signal depending upon a frequency of the external clock signal; an operation block configured to subtract a code value of the first counting code from a code value of a data output delay code, and output a delay control code; and a phase control block configured to control a phase of a read command signal by the number of clocks of a DLL clock signal corresponding to a code value of the delay control code, and output an output enable flag signal.

Abstract: A start-up circuit receives a start-up signal instructing start-up of an equipment mounted with the circuit, and executes a predetermined sequence when start-up is instructed by the start-up signal. An oscillator generates a clock signal. A sequence circuit receives the start-up signal and a clock signal output from the oscillator, measures time by counting the clock signal when the start-up signal transits to a predetermined level, and executes a predetermined event at a predetermined timing. The oscillator operates for a period where the start-up signal is at the predetermined level if the start-up signal is at the predetermined level during the period the power key of the equipment mounted with the circuit is being pushed.

Abstract: An object of the present invention is to provide a driver circuit including a normally-on thin film transistor, which driver circuit ensures a small malfunction and highly reliable operation. The driver circuit includes a static shift register including an inverter circuit having a first transistor and a second transistor, and a switch including a third transistor. The first to third transistors each include a semiconductor layer of an oxide semiconductor and are depletion-mode transistors. An amplitude voltage of clock signals for driving the third transistor is higher than a power supply voltage for driving the inverter circuit.

Abstract: A rotation speed detection circuit includes an internal clock generation portion which receives an input of a period signal whose period varies in accordance with rotation speed of a motor and generates an internal clock signal having a predetermined number of pulses in one period of the period signal, and an internal clock counter portion which counts the number of pulses of the internal clock signal for a predetermined period every one period of the period signal and delivers a count value thereof as a digital data signal.

Abstract: A radiation detection and counting system (2) includes a radiation detector element (5) for outputting a signal related to an energy of a radiation event received thereby and an amplifier (8) for amplifying the signal output by the detector element (5). A gain equalization circuit (10) adjusts the gain of the amplified output signal and a plurality of comparators (12) compare the gain adjusted amplified output signal to a like plurality of different valued threshold signals that are independently adjustable of each other A plurality of counters (20) is operative whereupon only the counter associated with the one comparator (12) that changes state in response to the peak of the gain adjusted amplified output signal exceeding the value of the trigger threshold signal thereof is incremented. A storage (24) stores the incremented value of each counter (20) accumulated over a sample time interval and data output logic circuit (26) transfers the stored accumulated counts out of the storage.

Abstract: In a counter circuit of a control signal generating circuit, a selector circuit selects under control which is in accordance with a selector circuit control signal (CTR) a predetermined one in a signal VSYNC and a signal HSYNC, which are pulse signals, so as to input a pulse signal thus selected to a counter. The counter outputs a counted result of pulses of the inputted pulse signal. By use of the counted result, a VSYNC synchronization signal generating circuit or an HSYNC synchronization signal generating circuit generates a control signal to control the driving of image display.

Abstract: Measurement apparatus is described that comprises a measurement portion for acquiring object measurements and an output portion (for outputting measurement data relating to the acquired object measurements. A deactivation portion is provided for inhibiting normal operation of the measurement apparatus such that output of the measurement data is prevented. The deactivation portion, in use, reads apparatus usage information from an apparatus usage module and inhibits normal operation of the measurement apparatus if said apparatus usage information fails to meet one or more predetermined criteria. The apparatus usage module may be provided as an integral part of the measurement apparatus or as a separate activation button. The measurement apparatus may comprise a measurement probe such as a touch trigger measurement probe.

Abstract: One disclosed circuit comprises a clock cycle counter circuit, a memory, and a clock cycle count comparison circuit. The clock cycle counter circuit may be configured to produce an output count. The memory may be configured to store at least first and second count values. The cycle count comparison circuit may be configured to compare the output count with each of the first and second stored count values and to generate a particular type of output event at a node if the output count corresponds to either of the first and second stored count values. Another disclosed circuit comprises a digital pattern generator, a general purpose output controller, at least one memory element, and a selection circuit. The digital pattern generator may be configured to generate a pattern of digital signals at M nodes. The general purpose output controller may be configured to generate general purpose digital signals at N nodes.

Abstract: According to one embodiment, a backlight control apparatus includes a setting section which sets a count value according to a cycle of a PWM pulse signal, a counter section which counts to the count value set by the setting section, a comparing/changing section which compares an actually measured count value of the counter section at a timing of a given vertical synchronous signal with a set count value set according to the cycle of the PWM pulse signal so as to change the count value according to the compared result, a determining section which generates a histogram of a given video signal so as to determine a duty ratio based on the histogram, and a PWM pulse signal generating section which generates a PWM pulse signal based on the counted result from the counter section and the duty ratio determined by the determining section.

Abstract: The semiconductor device according to the present invention generates pulse width modulation signals for controlling inverter circuits that drive a motor. The semiconductor device includes: a first register which holds values for determining a period in which each pulse width modulation signal becomes active; a correction buffer which holds a correction value; a first counter; a second counter which counts a value obtained by temporally advancing or delaying a count value of the first counter; a selector which selects the count value of the first counter or the count value of the second counter; and a pulse width modulation control unit which generates each pulse width modulation signal, logical values of which are switched in a timing when the selected count value matches the value held by the first register.

Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.

Abstract: A method for the failsafe monitoring of the rotational movement of a shaft comprises a first step of picking up a characteristic pulse train with a number of pulses following one another at successive times, the time interval between the pulses is dependent on the rotational movement. A second step determines a monitoring time period and a third step monitors whether an expected pulse of the pulse train occurs within the monitoring time period. Finally, there is a fourth step of generating a control signal when the expected pulse does not occur within the monitoring time period. The mounting time period is repeatedly adapted to the time interval of the pulses during monitoring.

Abstract: An improved technique of interfacing a computer lighting device to a control computer is disclosed, wherein a hardware device is interposed between the control computer and the lighting device. The hardware device handles certain functions in hardware, thereby permitting the microprocessor at the lighting device to incur substantially less processing load.

Abstract: An increasing monotonous counter over n bits formed as an integrated circuit, comprising: an assembly of 2n+1−(n+2) irreversible counting cells distributed in at least n groups of 2p−1 counting cells, where p designates the group rank; and at least n−1 parity calculators, each calculator providing a bit of rank p, increasing from the most significant bit of the result count, taking into account the states of the cells of the group of same rank.

Abstract: In a data processing system a method and apparatus is provided for discriminating between digital signals of a plurality of different rates by monitoring the pulse width and repetition rate of such signals. The digital signals are continuously monitored to determine whether a single pulse or multiple pulses have been detected within a preselected time period. If only a single pulse or a portion thereof has been detected within the preselected time period a first type of control signal is generated. If multiple pulses or portions of multiple pulses have been detected within the preselected time period a second type of control signal is generated.

Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.

Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.

Abstract: A clock pulse with a smaller amplitude voltage than the power supply voltage of the shift register is inputted to the shift register. The gate width of a TFT that constitutes a second clocked inverter of the shift register is set wide so as to reduce fluctuation in output electric potential due to leak current of a first clocked inverter. Further, a TFT is added to a first clocked inverter. A signal with an amplitude voltage of the same level as the power supply voltage is inputted to a gate electrode of the added TFT to switch between ON and OFF. The leak current of the first clocked inverter is thus cut off.

Abstract: A PLL system (200) includes a clock sequence generator (190). Clock sequence generator (190) provides a clock that steps down from a fast frequency through several steps to a frequency of zero. This step-down non-linear digression of frequencies causes a counter (110) driving a tank circuit of a self-calibrating VCO to achieve lock at an extremely rapid rate. The PFD (150) generates an analog signal based on the phase and frequency relationship of the reference and feedback clock signals. The analog signal is compared against an upper and lower reference voltage in a threshold detect circuit (120) and the signals UP and DOWN are supplied to the counter (110). The counter (110) provides a count value that controls the resonant frequency generated by the tank circuit. The convergence speed of the PLL system (200) is accelerated by the effects of the step-down clock provided by the clock sequence generator (190).

Abstract: A leakage current compensation system and method is disclosed that reduces frequency spurs and phase offset in a frequency synthesizer. The leakage current is determined based on the phase offset of the frequency synthesizer relative to a reference clock. A leakage current compensation circuit provides a leakage current compensation signal to the frequency synthesizer at the loop filter terminals to minimize the phase offset.

Abstract: Method and device to update a data count in a data transfer operation in which a data counter generates an intermediate count value in accordance with a first amount of data to be transferred to a storage media; and an augmenter augments the intermediate count value by a specified count value in accordance with data to be transferred to the storage media in addition to the first amount of data, wherein the updated count value is loaded into the data counter such that the intermediate count value becomes equal to the updated count value during the data transfer operation.

Abstract: The present invention relates to a detecting device of rotational position deviation, which detects deviation of the rotational position of machine axes driven by electric motors with pulse signals outputted from pulse generators, which are attached to at least two electric motors. One or more deceleration mechanisms are provided between an electric motor and a machine axis connected to the electric motor. A pulse transducer transforms two pulse trains outputted from the pulse generators to one pulse train, and an integrating counter counts the pulse train which is outputted from the pulse transducer, thus corresponding to the rotation angle. A zero phase pulse is outputted by each rotation of the pulse generator. The invention further comprises a count transducer transforming the count output from the integrating counter, and a calculator of rotational position counter calculating the output of the integrating counter and the count transducer and outputting rotational position errors.

Abstract: A vertical pillow type form-fill-seal packaging machine with transverse sealers incorporates a timing controller for adjusting the timing for clamping a tubularly formed film with the sealers such that articles being dropping in to be packaged will not be caught in between. A display device displays a time axis or parallel axes along which markers indicate the times of arrival of the falling articles to be packaged and the sealers at the clamping position for the sealers. As the user moves the marker for indicating the arrival time of the sealers, the timing controller adjusts the operating mode of the sealers such that the sealers will clamp the film at the time specified by the user according to the displayed time of arrival of the articles.

Abstract: The present invention is an efficient system and method for flexible masking of output bits from a counter. The maskable counter system and method of the present invention modify the chain carry fed into a counter so that any bit (or bits) of the counter may be masked. A masked bit of a maskable counter system and method is utilized to facilitate user programmable control of multiple configurations in a memory. A maskable counter system comprises a mask register (e.g., a D flip flop), a counter (e.g., a D flip flop), and a masking coordination circuit. The masking coordination circuit permits a carry in signal, a carry out signal, and a counter output bit signal to operate in a normal incrementation manner if a mask bit is not asserted and prevents the counter output bit signal from changing if the mask bit is asserted.

Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.

Abstract: Certain events occurring throughout a microprocessor chip are monitored by a counter system (1) containing a number of digital electronic counters (3, 5, 7 & 9) consolidated at a single location on the processor chip. Those events are communicated to the counter system via electrical leads extending to those functional units in the processor responsible for signaling an event occurrence. Under program control, each counter can be selectively connected (11, 13, 15 & 17) to a selected one of the various functional event producing units. By means of selection logic (19, 21, 23 & 25) separate events originating from multiple functional units may be logically combined, whereby the event counted is a Boolean logic combination of multiple underlying events.

Abstract: A reset device is disclosed which is part of a micro-controller formed on an integrated circuit. The reset device has a counter which outputs a count enable signal after counting a predetermined number of counts. In response to an input reset signal, an input device of the reset device provides a start signal to the counter for initiating count-down thereof. An output device outputs an output reset signal in response to the start signal and the count enable signal. The start signal is inhibited by a control signal, which is provided from a control device in response to an external reset signal received at an input pin of the micro-controller. The input device includes an AND gate which receives the input reset signal, an inverted delayed version of the input reset signal, and the disable signal. The reset device further includes an OR gate which receives the start signal and the count enable signal to provide an input signal to the output device for generation of the output reset signal.

Abstract: The pulse counter counts high speed pulses and detects an absolute phase difference among a plurality of electric motors. Pulse outputs 5 and 6 from pulse generators 3 and 4 are inputted into integrating counters 15 and 16 through pulse converters 9 and 11 and rotation direction detectors 10 and 12. Integrating counters 15 and 16 count up/dow the pulses in response to the rotation direction. Integrating counters 15 and 16 are cleared with a zero phase pulse output 7, outputted per revolution from the pulse generators 3 and 4. Multipliers 19 and 20 multiply outputs from the integrating counters 15 and 16 by a ratio set by a coefficient unit, and output a signal corresponding to the rotation angle of each electric motor. Adder/subtractor 21 estimates a deviation between the outputs of the multipliers 19 and 20 such that the phase difference between the pulse generators 3 and 4 is estimated.

Abstract: A seed counter of the present invention is used to accurately count seeds at a high speed. The invention includes a line vac connected to a linear array laser. The line vac is connected to a supply of seeds which are drawn through the line vac by a source of pressurized air and past the photoelectric sensor. The photoelectric sensor is connected to a control circuit which counts the seeds as they pass the photoelectric sensor. The control circuit also controls the flow rate of the counter by means of a variable pressure regulator connected to the line vac. As a result, the flow rate of the counter can be precisely controlled and a precise number of seeds can be counted and conveyed by the invention.

Abstract: The present invention has been made in view of the above mentioned problem, and the present invention provides a sticky signal generator for rapidly generating a sticky signal with a small layout area which uses a shift register of which the size is equal to the size of the inputted operand data.

Abstract: A system for electronically measuring the distance that a wheel has traveled can be used on a tractor-trailer combination vehicle to independently monitor mileages for the tractor and the trailer. An axle on the tractor and an axle on the trailer each has a hub odometer system which can electronically measure and store mileages for its respective axle. The system is mounted on a wheel and includes a signal generating device and a semiconductor unit. The signal generating device generates an electrical signal proportional to the number of wheel revolutions and the semiconductor unit receives, counts, and stores the electrical signals. The electrical signals are relayed to an output device. The system can also be used on other types of vehicle.

Abstract: Improved PLL frequency synthesizer circuits, including a novel swallow counter, may be operated at high speeds without experiencing internal delays or malfunctions. The swallow counter supplies a modulus signal to a prescaler which is capable of selectively changing a frequency-dividing ratio of a frequency signal. The swallow counter includes a shift register, a counter, a count-up detector, a modulus signal generator, and a control circuit. The swallow counter is connected to the prescaler and the program counter, and is capable of counting a frequency-divided signal based on a set value data and producing the modulus signal in response to a load signal after counting is completed. The swallow counter supplies the modulus signal to the prescaler and determines whether the set value data is data prepared to fix the frequency-dividing ratio.