Abstract: The present invention provides a transceiver. The transistor is coupled to a transmission line. The transceiver includes a variable resistor set, a transmitter module, a receiver module, and a digital signal processor. The transmitter module has an output terminal coupled to the variable resistor set and the transmission line. The transmitter module includes a first digital-to-analog converter configured to output an emission current. The receiver module has an input terminal coupled to the transmitter module and the transmission line. When the emission current is fed into the transmission line, a far-end echo is fed into the receiver module. An amplitude of the far-end echo is associated with a resistance value of the transmission line. The digital signal processor adjusts a current value of the emission current from a first default current value to a second default current value based on the amplitude of the far-end echo.

Abstract: A signal receiving circuit having an equalizer calibration function. The signal receiving circuit includes a sampling circuit, output driver and clock signal generator. The sampling circuit captures samples of a data signal in response to a sampling clock signal. The output driver outputs an equalizing signal to an input of the sampling circuit in response to a first clock signal. The clock signal generator adjusts a phase of the first clock signal to achieve phase alignment between transitions of the equalizing signal and transitions of the data signal.

Abstract: Various embodiments described herein are directed to methods and systems for blind mode adaptive equalizer system to recover complex valued data symbols from the signal transmitted over time-varying dispersive wireless channels. For example, various embodiments may utilize an architecture comprised of a channel gain normalizer, a blind mode equalizer with hierarchical structure (BMAEHS) comprised of a level 1 adaptive system and a level 2 adaptive system, and an initial data recovery subsystem. The BMAEHS may additionally be comprised of an orthogonalizer for providing a faster convergence speed. In various architectures of the invention, the BMAEHS may be replaced by a cascade of multiple equalizer stages for providing computational and other advantages. Various embodiments may employ either linear or decision feedback configurations. In the communication receiver architectures, differential encoders and decoders are presented to resolve possible ambiguities.

Abstract: Distortions of both amplitude and phase along a transmission line are compensated for by a trace canceller inserted between a transmitter and a receiver. The trace canceller has an equalizer that compensates for a trace length between the transmitter and the trace canceller. A variable gain amplifier between the equalizer and an output buffer has its gain controlled by an automatic gain control circuit that compares low-frequency swings of the input and output of the trace canceller. The gain of the variable gain amplifier is reduced to prevent the output buffer from saturating and clipping peak voltages on its output. Thus both the variable gain amplifier and the output buffer remain in the linear region. Training pulses from the transmitter are passed through the trace canceller without clipping of peak voltages, allowing the transmitter and receiver to adjust transmission parameters to best match the transmission line.

Abstract: The invention is directed to a system and method of regulating a slicer for a communication receiver. A zero-crossing accumulator receives a slicer output from the slicer and accordingly determines a zero-crossing length of the slicer output. A threshold decision unit regulates at least one threshold value of the slicer according to the zero-crossing length.

Abstract: Decision feedback equalization (DFE) circuitry and method for equalizing data signals over a wide range of data rates. By using delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via the DFE taps, correct feedback signal timing is maintained and jitter tolerance is increased at high data rates.

Abstract: A XDSL line card including an allocator for allocating power to the multi-tone modulated communications on each of the subscriber lines, and for selecting control parameters sufficient to effect communications on each of the subscriber lines at a power level proximate to an allocated power level therefore. The line card also includes configurable components coupled to one another to form a transmit path and a receive path to couple to the digital subscriber lines. The configurable components are responsive to the control parameters selected by the allocator to initialize multi-tone communications over each of the plurality of subscriber lines at a power level proximate the allocated power level.

Abstract: An efficient baseband predistortion linearization method for reducing the spectral regrowth and compensating memory effects in wideband communication systems using effective multiplexing modulation technique such as wideband code division multiple access and orthogonal frequency division multiplexing is disclosed. The present invention is based on the method of piecewise pre-equalized lookup table based predistortion, which is a cascade of a lookup table predistortion and piecewise pre-equalizers, to reduce the computational complexity and numerical instability for desired linearity performance with memory effects compensation for wideband transmitter systems.

Abstract: A radio receiver including a reception processing system that uses discrete-time frequency conversion to acquire a signal having a sampling rate corresponding to a local frequency, wherein the reception characteristic is improved when the reception processing system is applied to a system having a wide reception channel band. The radio receiver comprises an A/D converting part that quantizes a discrete-time analog signal to a digital value to output a received digital signal; a channel selection filtering part that uses a tap coefficient value to perform a digital filtering process of the received digital signal; and a frequency response characteristic correcting part that generates the tap coefficient in accordance with the sampling rate.

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The limiting amplifier applies respective gains to the RX path and to the TX path that are based upon respective dynamic ranges of the incoming signals.

Abstract: A DSL line conditioner achieves high performance sufficient to simultaneously support video, voice and data signals on standard telephone twisted pair lines over substantially greater distances than are currently available. The line conditioner automatically adjusts and sets the upstream and downstream preamplifier gains and attenuations according to the actual degradation imposed upon the upstream and downstream signals by the twisted pair line in which the line conditioner is used. The line conditioner achieves high performance by optimizing the signal-to-noise ratio and signal quality of DSL signals, and has a low power budget that enables it to operate by deriving power from the twisted pair lines over which it is used.

Abstract: Disclosed are a system, method and device for generating an equalized signal from an input signal. Symbols in the equalized signal may be detected on each of a sequence of symbol intervals to recover a symbol value in the symbol interval. A feedback coefficient may be applied to a symbol value recovered in a previous symbol interval to generate the equalized signal in a current symbol interval. The feedback coefficient may be generated based, at least in part, on an estimated error associated with the equalized signal. The estimated error associated with the equalized output signal from among a plurality of candidate estimated error values.

Abstract: The present invention relates to a system and method for selecting one of plurality of PRBS generators for use with a modem. The modem includes a measuring device adapted to measure an operating environment of the modem; and a storage device adapted to store a list of PRBS generator definitions. The modem selects one of a plurality of PRBS generators based on the measurement of the operating environment.

Abstract: In accordance with the present invention, a loop extender for improving the transmission of digital subscriber line (DSL) signals over a local loop is disclosed. The loop extender includes selectable line termination and equalization (SLTE) DSL amplification circuitry capacitively coupled to the local loop via bypass relay switches, a plain old telephone service (POTS) loading coil adapted to be coupled to the local loop for improving transmission of POTS band signals over the local loop, and a diagnostic/control unit (DCU) coupled to the local loop for receiving and processing control signals from a central office, coupled to the bypass relay switches via a bypass relay for controlling the bypass relay switches, and coupled to the SLTE DSL amplification circuitry via a plurality of switch control lines for controlling the SLTE DSL amplification circuitry.

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream.

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The limiting amplifier applies respective gains to the RX path and to the TX path that are based upon respective dynamic ranges of the incoming signals.

Abstract: A digital communication system for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line comprises an open-loop equalizer circuit and a DDC extension circuit. The open-loop equalizer circuit is operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals. The DDC extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and clamp the receive end of the transmission line during a negative transition of the DDC communication signal.

Abstract: Systems and methods are disclosed for improving DSL performance, including ADSL and VDSL performance, over a local loop between a telephone company central office and a customer premises. In particular, a loop extender is coupled to the local loop and differentially amplifies downstream and upstream DSL signals to at least partially compensate for DSL signal attenuation that occurs as DSL signals pass over the local loop. Pursuant to one embodiment, the loop extender includes an upstream filter/amplifying equalizer, a downstream filter/amplifying equalizer, a differential amplifier pair, an inverting amplifier, and a pair of electromagnetic hybrids, which couple the loop extender to the loop and provide upstream and downstream signal amplification. In another embodiment, the loop extender includes POTS loading coils to improve the POTS or voice band transmission over the local loop. According to this embodiment, the loop extender provides both improved POTS band signal transmission and DSL service.

Abstract: The present invention relates to a system and method for selecting one of plurality of PRBS generators for use with a modem. The modem includes a measuring device adapted to measure an operating environment of the modem; and a storage device adapted to store a list of PRBS generator definitions. The modem selects one of a plurality of PRBS generators based on the measurement of the operating environment.

Abstract: An apparatus, system, and method for providing an audio interface between multiple deskset phones and a single radio antenna unit (RAU). The audio interface includes a transmit path and a receive path. The transmit path carries transmit signals from the multiple deskset phones to the RAU. The receive path carries a receive signal from the RAU to the deskset phones. The transmit path and receive path are electrically isolated from each other.

Abstract: Systems and methods are described for asymmetric digital subscriber loops.

Abstract: An ADSL modem provides compensation for a nonlinear telephone impedance by predistorting transmit signals such that the voltage across the nonlinear impedance is correct independent of the impedance. Correcting the voltage across the nonlinear impedance reduces noise in the telephone due to intermodulation products generated in the voice band. The modem comprises a transmitter that includes (a) a signal source providing a source data signal and (b) a predistortion circuit for predistorting the source data signal to provide a modem transmit signal for coupling to a transmission loop having a nonlinear impedance coupled thereto. The modem device further includes a receiver for receiving a modem receive signal from the transmission loop. The source data signal comprises source digital words, each source digital word corresponding to a particular voltage level.

Abstract: An apparatus compensates for an attenuation of a signal on a telephone line in a communication system connected to the telephone line via a transformer. A photo coupler detects a loop current at a primary winding of the transformer. A controller generates switching control signals corresponding to an output of the photo coupler based on a predetermined switching table, and controls an overall operation of the communication system by receiving coding data. A level amplifier having different gains amplifies a signal at a secondary winding of the transformer by the gain corresponding to the switching control signal. A coder codes an output from the level amplifier to generate the coding data.

Abstract: An automatic line equalizer for use with a T1 or an E1 repeater in a telecommunications system is disclosed. The equalizer includes a first equalizing means for equalizing an input line having a line length falling within a first range and a second equalizing means for equalizing an input line having a line length falling within a second range. The equalizer includes a line condition/length detector. The equalizer includes switch means for selectively coupling one of the first and second equalizers to the selected input line as a function of a line condition indication. The switching means prevents hunting between said first and said second equalizers.

Abstract: The present invention relates to a BON built-in type balanced line driver circuit which reduces the size and cost of the unit by excluding duplication of impedance circuits, excluding duplication of an unbalanced/balanced converting transformer, converting a unipolar signal to a bipolar signal, and sending out the signal to the balanced line. The BON built-in type balanced line driver circuit has a U/B converting transformer including a primary winding having an intermediate tap and a secondary winding connected to a balanced line. The U/B converting transformer further includes first and second switch circuits connected between both terminals of the primary winding, and an impedance circuit inserted between the intermediate tap and a connecting point of the first and second switch circuits.

Abstract: An automatic loss compensation for use in a two to four wire hybrid converter in a telephone system. Many hybrid converters provide a substantially fixed gain for receive signals that are provided to the customer loop telephone line and for transmit signals that are provided to the digital carrier transmission line. The compensation circuit includes a measurement circuit, controller, and receive and transmit amplifier. The measurement circuit determines the length of the customer loop telephone line and provides a length signal. The controller receives the length signal and categorizes the length as being within one of a plurality of segments. The controller appropriately varies the amplification and phase of the receive signal, which is then combined with an inverted transmit signal, in order to substantially reduce reflected signals from the transmission line and transmission line termination.

Abstract: A system of impedance matching is provided to match the total impedance of the cable system to the total impedance of the powered elements such as the repeaters. The source impedance of the power supplies may be considered as part of the cable impedance. By matching impedances, the source voltage for driving the electronics is advantageously minimized.

Abstract: A two-wire telephone line interface circuit comprises a driver circuit for supplying direct current on the line, a controlled voltage generator, a sensing circuit for monitoring the line current, a control circuit for controlling an output voltage of the voltage generator, and a switching circuit. The control circuit controls the switching circuit to supply, as a supply voltage for the driver circuit, a battery voltage in an on-hook state of the line or the controlled output voltage of the voltage generator in an off-hook state of the line, this output voltage being controlled to provide off-hook current limiting. The control circuit also controls the switching circuit to selectively supply the controlled output voltage of the voltage generator as a signalling voltage to at least one wire of the line for high voltage signalling, e.g. ringing, on the line. Desirable forms of the switching circuit are described.

Abstract: Measuring the programming resistor in a data jack by placing the resistor in an AC voltage divider circuit via a transformer. An AC voltage (preferably generated by the modem's own transmitter circuitry) is applied to the voltage divider circuit, and an AC voltage measurement (preferably made by the modem's A/D converter) provides the resistance of the programming resistor. Matching the low-pass filter impedance characteristic of a local loop with a network having a matching low-pass filter characteristic, while also compensating the received signal with a compensation network having a high-pass filter characteristic, to reduce the frequency dependent gain effects caused by the matching network and/or the local loop.

Abstract: A reciprocal impedance conversion network is disclosed. Such conversion network preferably is used in a reciprocal negative impedance repeater for the nonloaded cable facilities of a telephone system. Two independent voltage sources for generating reciprocal negative impedance are connected between a first port and a second port. The first port is operably connected to the first voltage source such that a series negative impedance appears at that port. This port is specifically connected to the switching equipment of the telephone system. The second port is operably connected to the second voltage source such that a shunt negative impedance appears at that port. The second port is specifically connected to the nonloaded cable facilities of the telephone system. The network further provides a frequency dependent gain circuit which is useful for equalizing the losses along the nonloaded cable facilities.

Abstract: A terminal repeater placed in at least one communication line connecting an exchange and at least one terminal device, comprising a DC cut-off circuit providing continuous paths for AC signals flowing through the lines while providing discontinuous paths for DC signals flowing through the communication line, a DC power supply circuit generating a DC power used in place of a DC power supplied through communication line from the exchange, and supplying the generated DC power to terminal device, a DC loop signal detecting circuit comparing a threshold level with a level of a DC loop signal as is transmitted from the terminal device to the exchange, and generating a signal corresponding to the DC loop signal, and a pseudo-DC loop signal transmitting circuit, when the DC loop signal detecting circuit generates a signal, the pseudo-DC loop signal transmitting circuit controlling a C state of the communication line in accordance with the signal generated by the DC loop signal detecting circuit, thereby to transmit a

Abstract: A circuit for synthesizing an impedance across the tip and ring leads of a telephone line circuit is disclosed. The circuit includes tip drive and ring drive amplifiers connected to the tip and ring leads respectively, of a subscriber loop. The tip drive and ring drive amplifier circuits are arranged to convert feed voltage from a central office battery to feed current to drive the subscriber loop. A common-mode amplifier circuit connected between the tip and the ring leads senses the voltage dropped across the subscriber loop and outputs a control voltage to the tip and ring drive amplifiers, offsetting the feed currents applied to the subscriber loop. A differential amplifier circuit also connected to the tip and ring leads of the subscriber loop, detects a voltage difference between the tip lead and the ring lead and converts the detected differential voltage into a single ended output voltage of a specific gain.

Abstract: A key telephone system comprised of a key service unit connected to a plurality of local sets via four-wire conductors for providing full duplex signal communication between the key service unit and sets. Signals are carried by a first pair of each of the conductors for unidirectional transmission of signals from each set to the key service unit, and the remaining pair of conductors carries signals transmitted by the key service unit for reception by one or more of the sets. Four-to-two wire signal conversion and line impedance balancing is effected by one or more trunk circuits of the key service unit in the event one or more of the local sets are connected via the key service unit for communication between the sets and the outside telephone lines.

Abstract: In addition to an information signal subjected to a frequency dependent and a frequency independent loss component and delivered to an automatic equalizer through a transmission path which is typically a subscriber's communication path between a subscriber's terminal equipment and an exchange, an equalizer input signal comprises a pilot signal subjected to the frequency independent loss component alone. The equalizer comprises a first equalizer (26, 27, 36) responsive to a pilot signal component derived from the pilot signal for compensating for the frequency independent loss component. A second equalizer (31, 32, 37) compensates for the frequency dependent loss component in response to an information signal component derived from the information signal. The first and the second equalizers are cooperative in various manners in equalizing the input signal into an equalizer output signal. The pilot and the information signal components are extracted either directly or indirectly from the input signal.

Abstract: A wide band high voltage and high power amplifier is particularly useful for telephony applications. The amplifier employs a flyback converter with the capacitor storage element coupled across the line. The subscriber line is characterized in having a definite load impedance which impedance is in parallel with the storage capacitor of the flyback converter. The subscriber lines are monitored by a differential amplifier which provides a single-ended output indicative of the levels across the lines. This output is summed with the input signal to develop an error signal. The input signal to the line circuit is the particular signal of concern such as ringing, the voice signal and so on. The error signal is supplied as one input to a comparator having another input coupled to a triangular reference waveform. The output of the comparator provides a pulse width modulated waveform where the width of the pulses are indicative of the error signal.

Abstract: The invention refers to a circuit for telephone systems for the transmission of alternating current signals such as voice signals from a subscriber telephone system to a central office, wherein a signal transformer is provided with a by-pass for the direct current running in both wires to the central office. According to the invention a current path is provided by an amplifier inserted between the two wires to the central office. The amplifier is controlled by the dc current from the central office and alternating current provided by the transformer. The resistance of the amplifier changes according to control signals in the form of current supplied. The application of an amplifier as a current path between the two wires of the central office enables maintenance of direct and alternating current in the central office and simultaneous transmission and amplification of voice signals. The transformer need only supply a small part of the analog transmission signal energy.

Abstract: A digital communication system for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line comprises an open-loop equalizer circuit and a DDC extension circuit. The open-loop equalizer circuit is operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals. The DDC extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and clamp the receive end of the transmission line during a negative transition of the DDC communication signal.