Abstract: A method and a circuit for generating a secret quantity based on an identifier of an integrated circuit, in which a first digital word is generated from a physical parameter network, and this first word is submitted to at least one retroaction shift register, the output of the shift register forming the secret quantity.

Abstract: A method and a circuit of generation of several secret quantities by an integrated circuit according to the destination of these secret quantities, consisting of taking into account a first digital word forming a single identifier of the integrated circuit chip and coming from a physical parameter network, and of individualizing this identifier according to the application.

Abstract: A data scrambler is capable of scrambling N bits of data in parallel using a 2B−1 bit scrambling sequence. The scrambler may store scrambling values of an m-sequence in a table. The table may be formed into at least two overlapping swaths of N columns, wherein each swath may store the m-sequence arid the m-sequence of one swath is shifted from the m-sequence of a second swath. The scrambler may read a current swath N bits at a time and then may scramble N bits of input data in parallel using the N bits of the swath. When the swath is finished, the scrambler may shift to another swath.

Abstract: A quantum cryptographic communication channel having: a light source; a reflector; first and second sources each capable of generating a pair of photons emitted in the form of signal and idler light beams when energized by the light source, the first and second sources being arranged relative to each other such that the idler beam from the first source is incident upon the second source and aligned into the idler beam of the second source and the signal beams are directed by the reflector to converge upon a common point; a light modulator for changing the phase of the idler beam from the first source between first and second phase settings before being incident upon the second source; a controller for controlling the timing of the phase change from the first phase setting to the second phase setting; first and second detectors for detecting the incidence of the signal beams from the first and second sources; and a beam splitter disposed at the common point for directing the signal beams to the first detector

Abstract: A method and apparatus for software implementations of input independent LFSR-based algorithms are provided. In one embodiment, an initial location is identified in a cyclic sequence of entries representing a set of possible output values of a Linear Feedback Shift Register. Based on the initial location and a predefined group size, an initial group of entries is identified in the cyclic sequence of entries. Further, a predefined operation is performed on the initial group of entries in the cyclic sequence and an initial portion of input data. The predefined operation is repeated for each remaining portion of input data and a corresponding group of entries in the cyclic sequence.

Abstract: To encrypt another piece of data during encrypting process of a certain piece of data, a memory 55 is provided in parallel with a feedback line 65 which feeds back data from an encrypting module 51using an encryption key K to a selector 54. When an interrupt IT for processing plaintext block data Ni is generated while plaintext block data Mi is processed, ciphertext block data Ci at timing of generation of the interrupt IT is made to be stored in a register 56. The ciphertext block data Ci stored in the memory 55 is made to be selected by the selector 54 at timing of completion of processing the plaintext block data Ni, and processing the plaintext block data Mi+1 is started.

Abstract: A method and an apparatus for generating encryption stream ciphers are based on a recurrence relation designed to operate over finite fields larger than GF(2). A non-linear output can be obtained by using one or a combination of non-linear processes to form an output function. The recurrence relation and the output function can be selected to have distinct pair distances such that, as the shift register is shifted, no identical pair of elements of the shift register are used twice in either the recurrence relation or the output function. Under these conditions, the recurrence relation and the output function also can be chosen to optimize cryptographic security or computational efficiency.

Abstract: A system is provided for generating information for secure transmission from a first device to a second device. The system comprising a key scheduler for generating a dynamic secret key, a synchronization generator for generating a synchronization sequence and controlling the frequency of the dynamic secret key, a padding generator for generating a padding sequence, and a DEK generator for generating encrypted text. The system generating a stream of encrypted information that includes the synchronization sequence prior to and adjacent the encrypted text which is prior to and adjacent the padding sequence.

Abstract: The output bits that are shifted in order in the direction from stage R0 to R13 of a 14-stage shift register select Maximum-length sequences, which are generated by a specific primitive polynomial that correspond to a scramble number, from a selection table based on disk position data. Moreover, three selection bits are output according to the connection relationship with the selected Maximum-length sequences, and after the exclusive OR has been taken in order by the EXOR circuit, they are fed back to the initial stage R0. The recording data are scrambled by using the Maximum-length sequences that are generated in this way, making it possible to perform scrambling with little correlation and high reliability regardless of the recording position.

Abstract: To transmit encoded information such as for example voice messages between remote transceivers, a transmitter digitizes and encodes an audio signal and then transmits the resulting digital coded signal to the receiver. The receiver decodes the signal and converts it back to an audio signal. The received encoded digital signal is used to reset the timing clock in the receiver so that the timing is synchronized in the receiver and transmitter by the transmitted encoded information. The encoder transmits digital information to a shift register. Encoding switches select certain stages of the shift register and the transmitter transmits the exclusive-OR of the digitized message and the output of the selected stages. This signal is also the input to the shift register. The information transmitted to the receiver is a scrambled digital signal.

Abstract: A volatile field programmable gate array (FPGA) having a configurable logical structure portion that is configurable with encrypted configuration data stored external to the FPGA in configuration data memory. On FPGA reconfiguration, for example on power-up, the encrypted configuration data is supplied to an input of the FPGA. In the FPGA, the configuration data is first decrypted by a decryption algorithm embedded in logic, the algorithm using as an operand a decryption key stored in the FPGA in a non-volatile memory, for example EEPROM. The decrypted configuration data is then distributed to the volatile functional portion of the FPGA in a conventional manner. The functional portion may be SRAM. With this design, unauthorized reading of the configuration data of the FPGA by observation of the stream of configuration data transmitted to the FPGA from the external memory, for example during power-up, will only result in encrypted configuration data being obtained.

Abstract: Methods and systems are provided for processing information.

Abstract: A cipher system having a cipher core to encrypt plaintext data into ciphertext data, and a bus interface coupled to the cipher core to transfer the ciphertext data to a bus. In one embodiment, the cipher core comprises a block assembler to receive words of data and to assemble the words into a block, an encryption function to encrypt the block based on an encryption function key, a block transmitter to receive the encrypted block and to disassemble the encrypted block into encrypted data words, and a controller to control multiple rounds of encryption by the encryption function for the block. In another embodiment, the encryption function is duplicated and the controller is replaced by two controllers, the first controller controlling the first five rounds of encryption of the block and the second controller controlling the second five rounds of encryption of the block.

Abstract: A pseudorandom number generation circuit 2 whose generation timings of pseudorandom numbers vary randomly is disclosed. The pseudorandom number generation circuit 2 includes a clock generation circuit 4 which generates four kinds of clocks, a selection signal generation circuit 8 which generates selection signals randomly, a selection circuit 6 which selects either one of the four kinds of clocks based on the selection signals, and a linear feedback shift register (LFSR) 10 which carries out shift operation based on the clock selected by the selection circuit 6. The LFSR 10 generates a pseudorandom number in response to the selected clocks. Since the selection of the clock is carried out randomly by the selection signal generation circuit 8, the generation timings of the pseudorandom numbers generated by the LFSR 10 are also random.

Abstract: An output bit sequences is derived from an initial bit sequence and this output bit sequence is used to encrypt an input bit sequence in a first mode of operation or not to so encrypt the input bit sequence in a second mode of operation. The mode of operation is switched automatically whenever the output bit sequence contains a predetermined trap bit sequence. As a result of this automatic switching between such encryption and no such encryption, unauthorized determination of secret codes is thwarted.

Abstract: A method, and associated apparatus, for generating a pseudo-random number sequence. Determinations are made of compatible configurations of windmill generators for a selected windmill polynomial. Implementation of a windmill generator is made through use of word-oriented memory elements. Words stored in the memory elements are selectively outputted to form portions of a pseudo-random number sequence.

Abstract: A pseudorandom number generation circuit 2 whose generation timings of pseudorandom numbers vary randomly is disclosed. The pseudorandom number generation circuit 2 includes a clock generation circuit 4 which generates four kinds of clocks, a selection signal generation circuit 8 which generates selection signals randomly, a selection circuit 6 which selects either one of the four kinds of clocks based on the selection signals, and a linear feedback shift register (LFSR) 10 which carries out shift operation based on the clock selected by the selection circuit 6. The LFSR 10 generates a pseudorandom number in response to the selected clocks. Since the selection of the clock is carried out randomly by the selection signal generation circuit 8, the generation timings of the pseudorandom numbers generated by the LFSR 10 are also random.

Abstract: A pseudorandom sequence generator including a first feedback shift register having at least one input and at least one output and a first controller having an output in communication with the at least one input of the first feedback shift register; the first feedback shift register operating at a first speed S1 and the first controller operating at a second speed S2. In one embodiment the first speed S1 of the first feedback shift register is an integer multiple of the second speed S2 of the first controller. In another embodiment the first feedback shift register includes a shift register having an input, an output, and at least one tap; and a feedback function generator having a first input in communication with the at least one tap of the shift register, a second input in communication with the output of the first controller, and an output in communication with the input of the shift register; the feedback function generator includes at least one feedback function.

Abstract: A method and apparatus are disclosed for performing modular multiplication. Modular multiplication in accordance with the present invention includes precalculating a 2's complement of a given modulus and multiples of the 2's complement and calculating a total magnitude of end-around carries during the modular multiplication. The calculated multiples are selected depending on the total magnitude of the end-around carries, and the selected multiples are added. The disclosure includes array structures in accordance with the present invention. The invention includes an algorithm designed for Rivest-Shamir-Adelman (RSA) cryptography and based on the familiar iterative Homer's rule, but uses precalculated complements of the modulus. The problem of deciding which multiples of the modulus to subtract in intermediate iteration stages has been simplified using simple look-up of precalculated complement numbers, thus allowing a finer-grain pipeline.

Abstract: A method of encrypting and decrypting digital data such as text, numeric, images, pictures, especially tailored for optical compact discs; said method comprising of ciphering/deciphering and error detection and correction using algebraic method, namely Reed-Solomon code.

Abstract: To provide an apparatus for generating pseudo-random numbers at a high speed with sufficient cryptographical security, the apparatus comprises: a T-ary counter (101) for generating a count number from 0 to T-1 cyclically by incrementing the count number in synchronization with a clock signal; a modulus memory (103) for outputting a prime number read out from T prime numbers prepared therein according to a value of the count number; an n-bit register (102) for registering and outputting an n-bit value in synchronization with the clock signal; an expanded affine transformation circuit (104) for outputting an intermediate number, by performing expanded affine transformation of the n-bit value registered in the n-bit register (102) according to the prime number, the n-bit value being revised with the intermediate number in synchronization with the clock signal; and a demagnification circuit (105) for outputting certain s bits of the intermediate number as one of the pseudo-random numbers in synchronization with t

Abstract: Circuitry which performs modular mathematics to solve the equation C=M.sup.k mod n and n is performed in a manner to mask the exponent k's signature from timing or power monitoring attacks. The modular exponentation function is performed in a normalized manner such that binary ones and zeros in the exponent are calculated by being modulo-squared and modulo-multiplied.

Abstract: A new class of variable length, nonlinear feedback shift registers (NLFSR's) is disclosed that uses data-dependent dynamically allocated taps to filter digital information reversibly, flexibly, and rapidly. This class of NLFSR's has been succinctly realized in terms of a multi-parameter family of nonlinear, discrete difference equations that operate on digital data of variable length. Each individual NLFSR is characterized by a collection of integer `parameter functions` and `boundary condition functions` denoted .PI..sub.T for an integer T.gtoreq.1. A concrete description of an exemplary set .PI..sub.T is given in the text. Given an input sequence to the NLFSR, the final output sequence is another sequence defined by the values of the parameter and boundary condition functions, and a new reversible (or invertible) nonlinear mathematical rule that transforms a sequence of integers into a different sequence of integers.