Abstract: For the purpose of suppressing DC components and high energy components at different frequencies, digital signals are frequently transmitted in scrambled form. The realization of corresponding scramblers and descramblers is involved and difficult at high transmission rates. A self-synchronizing descrambler is provided which, due to parallel processing of the digital signals to be descrambled, has a relatively low working speed and is easy to manufacture in integrated technology. The descrambler employs a plurality of descrambler stages each including first and second modulo-2 adders and a shift register stage.

Abstract: A cryptographic system comprises a modulo-2 adder having a first input receptive of a sequence of binary digits to be scrambled and a second input receptive of a sequence of scrambling binary digits for generating a sequence of scrambled binary digits. A function generator having a memory is provided for storing a predeterminable sequence of binary digits in addressible storage locations and reading the stored binary digits in response to an address code represented by combined first and second patterns of binary digits which are generated respectively by a random pattern generator and a shift register which is connected to the output of the modulo-2 adder. The output of the function generator is the scrambling binary digits applied to the modulo-2 adder.