Abstract: A device and method to determine the stopping rotor position of a washing machine motor includes an inverter, a permanent magnet synchronous motor, and an electronic motor controller. The controller determines the stopped rotor position of the motor by measuring induced currents in the stator field coils of the motor. While the motor is de-energized and slowly rotating, the controller directs the inverter to connect all of the stator field coils of the motor together. The stator field coils may be connected to a common D.C. rail, output from an A.C.-D.C. converter of the washing machine. In an embodiment, the controller determines the rotor position based on the polarities of current induced in the stator field coils. In another embodiment, the controller determines the rotor position based on the phase angle and angular frequency of the three phase currents, transformed into a stationary reference frame.

Abstract: Methods, systems and computer program products for compensating repeatable timing variations associated with a spindle motor are described. Specifically, a repetitive error correction factor may be determined using a computational model which predicts timing variations. The correction factor can then be used to cancel the effect of the actual timing variations upon the spindle motor.

Abstract: A method and an apparatus for the failsafe monitoring of an electromotive drive without additional sensors, including a drive having a three-phase control of an electric motor, detection of the current and voltage profiles of each of the three phases, as they are forwarded to the motor by drive electronics, determination of the load speed while using the detected current and voltage values, where the determination of the load speed takes place by calculating an observer model with reference to the detected current, to the detected voltage, to the frequency preset by the control and to the characteristic data of the motor and generation of a failsafe switch signal for the motor when the calculated load speed does not correspond to a preset desired speed within the framework of preset tolerances. The load torque can also be determined and monitored with reference to the observer model.

Abstract: A clock and data recovery circuit including a phase synchronization loop including an oscillator, the oscillation frequency of which is variably controlled, the phase synchronization loop performing phase-synchronization of a clock signal output from the oscillator with an input data signal. The circuit also includes a discriminator circuit, responsive to a clock signal for discrimination, for discriminating the input data signal and outputting the discriminated signal. The circuit further includes a phase detector circuit for detecting the phase difference between an output data signal, discriminated and output by the discriminator circuit, and the input data signal. The circuit also includes a phase shift circuit for shifting the phase of the clock signal, output from the oscillator, based on a comparison result output from the phase detector circuit. The clock signal, which is output from the phase shift circuit, is supplied as the clock signal for discrimination to the discriminator circuit.

Abstract: A system for cancelling or attenuating noise in at least two positive displacement compressors proximately located from each other for use with a heating or cooling system. A lead compressor and a lag compressor have a controllable rotational speed and phase of operation. A controller selectably controls the rotational speed and the phase of operation of each of the compressors. The controller controls the rotational speed of the compressors at substantially the same speed for each compressor, with a phase-lock loop and a comparator circuit for each compressor. The controller controls the phase of operation of the compressors through an oscillator so that the lead and lag compressor pressure pulses are spaced between successive outlet pressure pulses to effectively double the combined pulsation frequency for noise attenuation.

Abstract: A phase/frequency detector module allows operation as either a phase locked loop or a frequency locked loop. As a phased locked loop (PLL), the phase detector module is configured to decode phase differences between a reference signal and a voltage controlled oscillator (VCO) signal into phase correction signals that are updated at the rate of the VCO signal. An accumulation of the phase correction signals is implemented to form an accumulated phase error signal, which is then sampled at a lower rate than the VCO signal to accommodate slower components of the PLL, such as a digital to analog converter (DAC). As a frequency locked loop (FLL), the phase detector module is configured with frequency counters, so that frequency error may instead be detected. Any reduction of gain caused by the frequency counters is inherently equalized by the phase detector module.

Abstract: A method and system for synchronizing an input signal for a power system. The method comprises: extracting from the input signal, three substantially equidistant samples from a fundamental component of the input signal; determining a frequency (f1), an amplitude (A1), and a phase-difference (?Diff) of the input signal from the three equidistant samples and a tracking signal corresponding to a steady-state of the fundamental component of the input signal characterized by a frequency (fTS) and an amplitude (ATS) with a phase-difference that is the phase angle between the tracking signal and the input signal; and generating and outputting a frequency, amplitude, and phase-difference signals corresponding to the determined frequency (f1), amplitude (A1), and phase-difference (?Diff) of the input signal to one or more components of the power system.

Abstract: A phase tracking system includes a source of an input signal representing a received symbol. A phase rotator has a first input terminal which is responsive to the input signal, a second input terminal which is responsive to a phase correction signal, and an output terminal which produces a phase adjusted output signal. A decision element generates an ideal signal representing the received symbol in response to the phase adjusted output signal. A phase adjuster, which has full phase wrap-around capability, generates the phase correction signal in response to the phase difference between the phase adjusted output signal and the ideal signal.

Abstract: A method for the no-transmitter speed determination of an asynchronous machine, comprising the steps which follow: a module for field-oriented regulation calculates the voltages to be applied to the asynchronous machine on the basis of a setpoint for the speed, at least two values measured for the conductor current, and a speed calculated by an observer module, the observer module has applied thereto the voltage values obtained from the field-oriented regulation or the voltage values measured, and calculates a value of the moment-forming current îsq(t) and an inner moment Mi(t) of the asynchronous machine from the values applied, a moment module calculates a load moment Ml(t) acting upon the asynchronous machine from the difference of the moment-forming currents from the field-oriented regulation and the observer module, a speed module calculates the actual speed of the asynchronous machine via the load moment of the moment module and the inner moment of the observer module.

Abstract: A method and apparatus perform control. A control method according to one embodiment accesses a Hall effect signal; obtains an error signal relating to a system parameter using the Hall effect signal and a reference signal for the system parameter; obtains a calculated signal for the system parameter using the error signal; and utilizes the calculated signal as a new reference signal for the system parameter, for a next iteration of the obtaining steps.

Abstract: There is provided a flexible transmission device capable of automatically setting an optimal point for a signal decision making with high accuracy, so that highly reliable high-quality signal regeneration control is achieved. A clock timing extraction circuit dynamically sets a frequency-dividing ratio based on the transmission rate of an input signal to perform a phase synchronization control so that there is a fixed phase difference between the input signal and an oscillation output, whereby clock timing based on the transmission rate can be extracted. A regeneration control circuit sequentially sweeps a voltage threshold level and the phase of the extracted cock with respect to the input signal and determines whether the levels of adjacent monitor points match, whereby a decision point within the valid zone of the eye pattern can be automatically measured and used as the optimal point for regeneration control.

Abstract: A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring a pulse length of the binarized playback signal using the N-phase clocks to output pulse-length data, and a run-length-data extracting device for counting the pulse-length data based on a virtual channel clock to extract run-length data. Pulse-length data is generated using the N-phase clocks (e.g., 16-phase clocks). The pulse-length data is counted based on the virtual channel clock to extract run-length data. Thus, it is not needed to generate a high-frequency clock, and the operating frequency is maintained sufficiently low.

Abstract: A method for reducing commutation-related acoustic noise in a fan system is provided. A constant frequency periodic signal is generated and a fan commutation event is synchronized with a zero level value of the constant frequency periodic signal. A system for controlling a direct current fan is provided. The system comprises a signal generator adapted to produce a periodic signal of a constant frequency and a phase-locked loop. A zero level value of the periodic signal is synchronized with a commutation event of the fan.

Abstract: A method of correcting the determination of extended rotor flux using a lag function and a correction algorithm that closely approximates a pure integrator function to correct for lag function errors that can extend the EFS control down to dynamoelectric machine speeds corresponding to as low as 10 Hz electrical frequency.

Abstract: The speed control apparatus comprises a plurality of Hall sensors, a plurality of switches, a turn-on control circuit, and a gate drive logic. The Hall sensors are configured to detect magnetic rotor sections of a poly-phase brushless DC motor at different positions. The switches apply voltages on a plurality of windings to respectively produce magnetic north or south on stator poles of the poly-phase BLDC motor. The turn-on control circuit generates a conduction time reduction after each output transition of the Hall sensors. The gate drive logic separately turns on or turns off the switches according to different output transitions of the Hall sensors to respectively apply voltages on the windings with the conduction time reduction.

Abstract: A method and apparatus for controlling a fan is disclosed. In one embodiment, a method for controlling a fan includes applying power to the fan at startup. The fan may be supplied a predetermined amount of current, which may break the inertia of the fan propeller and begin its rotation. As the propeller begins rotating, the speed at which it rotates may be monitored. The fan startup routine may continue until the fan reaches or exceeds a minimum fan speed threshold. Once the fan has at least reached the minimum speed, the amount of current supplied to the fan may be reduced such that the fan rotates at minimum speed, and an automatic fan control algorithm may begin executing. By reducing the current such that the fan operates at a minimum speed, the amount of audible noise generated by the fan during startup may be kept to a minimum level.

Abstract: Method and apparatus for accelerating a motor from an intermediate velocity to a final operational velocity. The motor is accelerated from rest to the intermediate velocity through application of fixed duration drive pulses to the spindle motor. Once the motor reaches the intermediate velocity, commutation circuitry and back electromotive force (bemf) detection circuitry use detected bemf from the motor to electronically commutate the motor to accelerate to the final operational speed. A phase lock oscillator (PLO) attempts to acquire frequency lock for the motor. A control circuit measures the current in the motor to evaluate the effectiveness of the phase lock. If the measured current is found to be above a threshold value, the motor is restarted.

Abstract: A sensorless motor control algorithm that single-handedly permits operation over the entire speed range from low speed to high speed. This “fusion” algorithm seamlessly fuses the position data generated respectively by high speed and low speed sensorless algorithms. The resulting sensorless drive permits effective position sensorless operation over the entire speed range of a PM motor.

Abstract: A disk drive is disclosed comprising a spindle motor comprising a plurality of windings for rotating a disk. The spindle motor is rotated by commutating the windings over a plurality of commutation states, wherein audible noise generated by the disk drive is reduced by phase modulating the commutation interval. Further audible noise reduction is achieved by modulating a current applied to the windings which substantially reduces discontinuities in the torque output of the spindle motor caused by phase modulation of the commutation intervals.

Abstract: A drive control system, with PLL control, drives a rotatable multi-phase sensor-less motor by switching a current of a field coil of each phase depending on the rotating phase of the motor. When the moto is driven, a desired phase is selected as a datection phase, and a voltage induced on the coil of the detection phase is detected when power is fed for a predetermined time to the field coils other than the detection phase. A magnetic pole position is detected from the amplitude condition of the detected induced voltage. Based on this detection, the power-feeding phase of the motor drive is determined. Power feeding and pole position detection are performed alternately.

Abstract: The present invention is a drive control device for controlling an electric rotational actuator which moves the driver, including: a reference comparison signal generation circuit; a detection circuit for detecting the speed of the actuator and outputting this as a detection signal; a speed designation circuit of the actuator; a rotation control circuit of the actuator; and a phase comparison circuit for comparing the phase of the reference comparison signal and the phase of the detection signal and outputting the comparison result to the rotation control circuit; wherein the rotation control circuit controls the speed of the actuator to conform with the speed designation based on the phase comparison result.

Abstract: A drive control system, with PLL control, drives a rotatable multi-phase sensor-less motor by switching a current of a field coil of each phase depending on the rotating phase of the motor. When the motor is driven, a desired phase is selected as a detection phase, and a voltage induced on the coil of the detection phase is detected when power is fed for a predetermined time to the field coils other than the detection phase. A magnetic pole position is detected from the amplitude condition of the detected induced voltage. Based on this detection, the power-feeding phase of the motor drive is determined. Power feeding and pole position detection are performed alternately.

Abstract: A motor rotational pulse generating circuit for a motor is provided which generates a correct pulse signal even at an initial turning-on stage of the motor, by adjusting a filter cutoff frequency in response to motor rotational condition. The motor rotational pulse generating circuit includes a rotational pulse generation circuit 20 which generates ripple pulses based on a signal being inputted from the DC motor 1, in which a ripple is superposed whose frequency is in proportion to a rotation number of the DC motor 1. A filter 3 makes a cutoff frequency variable on the basis of a clock signal issued from a PLL circuit 6. An oscillation frequency at an oscillator VCO10 is determined by the ripple pulses and a motor rotation condition signal inputted by way of circuits 12 to 16 inclusive. A microcomputer 20 operates, when the motor is turned on, to cause the oscillator VCO10 to issue a preliminary clock signal.

Abstract: The invention relates to a method for regulating an electric-motor-driven adjusting device, in particular for vehicles, having a safety circuit (5) for reversing or stopping a drive motor, and to an apparatus for performing this method. To enable fast, safe detection in the event of something becoming caught or pinched, it is provided that an actual value is regulated via a closed-loop control circuit to a set-point value, the actual value or set-point value is a signal having a frequency proportional to the rpm or load on the drive motor, and the phase difference detected with a comparison member of the control circuit is utilized to activate the safety circuit.

Abstract: An adaptive motion controller for driving a servo motor. The adaptive motion controller has an amplifier including a voltage command which can be set at a voltage at which the amplifier will be operated, a frequency selector which can be set at a frequency at which the amplifier will be operated, a power supply having a current feedback, and a control for driving the servo motor in a test mode wherein the voltage command is set at a selected voltage, and the frequency selector is sequentially set with a series of different frequencies. The servo motor is operated at each frequency, and the frequency of the series of frequencies that has the lowest current feedback is determined and the frequency selector is set at that frequency when the amplifier is operated to drive the servo motor.

Abstract: A motor controlling semiconductor integrated circuit for controlling a motor by a PLL control is provided comprising output transistors for driving a motor, a position detecting means detecting a rotational position of a rotor in said motor, for generating a position detection signal, a phase comparing means comparing said position detection signal with a reference clock, for generating a phase difference detection signal, and means receiving said phase difference detection signal, for controlling an on-duty of said output transistors on the basis of a duty of said phase difference detection signal.

Abstract: A method and apparatus for controlling the speed of a voltage-controlled fan by locking the pulse-width modulated speed control voltage to a tachometer signal of the fan is presented. By triggering the off time of the PWM pulse to the detection of the tachometer signal and ensuring the off time is less than one tachometer period, no phase and frequency information is lost.

Abstract: A method and system for detecting a change in the position of an electric drive motor in a vehicle power window system includes a current sensor for sensing a current of the motor, and generating an input signal having a phase associated therewith. A signal generator generates a reference signal having a predetermined phase and a frequency. A comparator is in communication with the current sensor and the signal generator for comparing the phase of the input signal with the phase of the reference signal. A control circuit, in communication with the signal generator, determines movement of motor based on the comparison. If the motor does not move while being commanded to close, an obstruction may be assumed to be present between the window and its respective frame.

Abstract: A method and system for compensating for voltage notches in phase locked loop (PLL) control devices. A bridge firing controller receives signals representative of two of the line to line voltages received by the bridge. The controller includes a PLL synchronizing tool which receives the line to line voltage signals and generates a synchronizing phase error signal for aligning the phases of the two input signals. The controller, for a predetermined period following bridge firing, determines whether a voltage notch has occurred. If so, the controller substitutes model control signals for actual control signals so as to reduce the effect of the notch on the generated phase error signal used for synchronization. If not, the controller continues to use the actual control signals to generate the phase error signal. Once the predetermined period has expired, the controller utilizes the actual control signals to generate the phase error signal.

Abstract: A method and circuit for operating a polyphase dc motor in which discontinuous sinusoidal drive voltages are applied to the windings of the motor in predetermined phases. The discontinuous portion of the sinusoid is timed with the bemf zero crossings. Bemf zero crossings are detected, and phases of the drive voltages are adjusted to have zero crossings substantially in the discontinuities of the drive voltages. The method and circuit result in motor operation with significantly reduced acoustic motor noise.

Abstract: A device for determining a rotational number of an electric dc motor which drives a moving body of an automobile accessory such a sunroof, or a glass pane of a power window includes a switched capacitance filter for eliminating noise from the motor, a cutoff frequency of the switched capacitance filter being dependent on a clock input thereof; a pulse shaping circuit for generating a ripple pulse signal indicative of the rotational number of the motor by wave-shaping an output of the switched capacitance filter; and a pulse generating circuit providing an output pulse signal so as to establish a condition wherein the frequency of the ripple pulse signal is equalized to the cutoff frequency of the a switched capacitance filter.

Abstract: A controller for an electric motor, includes a reference circuit and control circuitry. The reference circuit generates a reference signal having a phase and frequency determined in accordance with a set of motion parameters input to the circuit. The control circuitry receives the reference signal and receives a feedback signal from a rotation detector coupled to the motor, the detector having a predetermined rotational resolution, and compares the reference signal and the feedback signal to generate a drive signal used to drive the motor at a speed and phase of rotation determined by the frequency and phase of the reference signal. The phase of rotation of the motor is locked to the phase of the reference signal such that deviation of the phase of rotation relative to the phase of the reference signal at steady state is substantially smaller than the rotational resolution of the rotation detector.

Abstract: A method of controlling motor speed. The motor speed control apparatus includes an encoder in mechanical association with the motor. The encoder has one channel providing an encoder signal having a rising and falling state transition for each period of the encoder signal. The periodic frequency of the state transitions are used to precisely measure instantaneous motor speed. A comparitor then compares the periodic frequency with a predetermined motor speed to provide an error signal, representative of the difference. A feedback control system affects the motor speed dependent on the error signals. In a further embodiment, the encoder includes two channels and four state transitions.

Abstract: A time-discrete phase-locked loop includes a discrete time oscillator (DTO) which supplies a periodical oscillator signal (OS) representing oscillator values (OV) at corresponding clock instants (TC) of a clock signal (CLK). A position-determining circuit (P) generates a time-discrete synchronization instant (SI) representing a position of an analog synchronizing pulse (SP) of a video signal with sub-clock period accuracy. A phase detector (PD) determines a phase error (PE) between the discrete time oscillator signal (OS) and the synchronization instant (SI) by using the synchronization instant (SI), a value (OV1) of the discrete time oscillator signal (OS) at a clock instant (TC1) related to the synchronization instant (SI), and the slope of the oscillator signal (OS). A period of the oscillator signal (OS) depends on the phase error (PE). By using the slope of the oscillator signal (OS), the phase error (PE) is independent of this slope.

Abstract: In a method of starting rotation of a magnetic disk medium of a large-capacity flexible disk by a spindle motor for use in a high-density type flexible disk drive for carrying out data recording and reproducing operation to and from the magnetic disk medium of the large-capacity flexible disk which requires to rotate at a high rotation speed on recording and reproducing, the method includes: a first step of rotating the spindle motor at a low rotation speed lower than the high rotation speed on rotation starting of the magnetic disk medium; a second step of rotating the spindle motor at the high rotation speed subsequently to rotating of the spindle motor at the low rotation speed; a third step of rotating the spindle motor at the low rotation speed subsequently to rotating of the spindle motor at the high rotation speed; and a fourth step of rotating the spindle motor at the high rotation speed subsequently to rotating of the spindle motor at the low rotation speed at the third step.

Abstract: A frequency detector for a PLL controller, the controller being for generating an output signal to control a motor driver electrically connected to a motor having multiple phase windings arranged as a stator and a rotor having a permanent magnet or a DC current excitation winding for rotating the rotor, the motor driver selectively establishing current paths through selected windings in response to said output signal, to provide maximum torque to the rotor based on the rotational position of the rotor relative to the windings, the frequency detector comprising a monitor for detecting a number of pulses in said output signal during a time period between a first and a second rotational position of the rotor relative to the windings and a governor for generating a frequency control signal as a function of said number of pulses, wherein the PLL controller generates said output signal at output frequencies selectively as a function of said frequency control signal, whereby the frequency detector minimizes a differ

Abstract: A frequency-locked stepping position control servo (FLSPS) system for driving a stepping motor. It essentially comprises a means for driving the stepping motor to move an object toward a target according to a driving signal, a means for detecting position of the object, a position-to-frequency converter to feedback the position information and a microprocessor-based slope-varied frequency-controlled oscillator (.mu.P-SVFCO) to generate the driving frequency. The .mu.P-SVFCO includes a microprocessor to ease the implementation of the control law and utilizes the slope-varied technique to adaptively pump the pulse train frequency of the driving signal. In addition, a one-bit clock is provided to dynamically maintain the position of the object when the target position is reached. The FLSPS system is capable of achieving similar system acquisition times for different target commands among a wide-range of positioning control commands.

Abstract: A phase-locked loop (or frequency-locked loop) based circuit for controlling the drive applied to a DC polyphase motor is disclosed. The disclosed circuit includes a clamp circuit, connected to the input of the motor drive amplifier, for limiting the current applied to the drive amplifier, in order to ensure that the power supply is not overloaded. According to one embodiment of the invention, the clamp circuit includes a buffer amplifier having a source leg and a sink leg. During a current control mode, both the source leg and sink leg of the buffer amplifier are enabled to drive the input of the motor drive amplifier; the buffer amplifier is a differential amplifier and applies a feedback signal from the drive amplifier input to control the current applied thereto according to an input limit signal.

Abstract: Provided is a brushless DC motor speed controller in which the speed feedback signal needed for speed control is obtained from the commutation signals generated by the magnetic-pole sensor in the brushless DC motor. The-brushless DC motor speed controller includes an edge detector, which generates a pulse each time a rising or falling edge is detected in the signal from the magnetic-pole sensor of the brushless DC motor. A frequency multiplier is used to multiply the frequency of the pulse train from said edge detector. A frequency-to-voltage converter is used to convert the output pulse train from said frequency multiplier into a positive analog voltage, with the level of the positive analog voltage being in proportion to the speed of the brushless DC motor. A motor rotating direction detecting circuit receives the output signal from said magnetic-pole sensor and thereby detects in which direction the brushless DC motor currently rotates.

Abstract: A PLL system has a phase comparator for converting the phase difference between a reference clock signal and a feedback clock signal corresponding to a PWM signal Into a binary value, a frequency comparator for converting the frequency difference between the reference and feedback clock signals into a binary value, an automatic gain controller for adjusting the loop gain of the PLL system to a given value whenever the output of the frequency comparator reaches a change point, and a PWM signal generator for generating the PWM signal according to the outputs of the phase comparator, frequency comparator, and automatic gain controller. These components of the PLL system process digital signals, to simplify the structure of the PLL system, expand the range of loop gains to be set, and speedily synchronize the feedback clock signal with the reference clock signal.

Abstract: A control system for energizing a direct current (DC) motor with alternating current (AC) power includes a first voltage sensor for a peak voltage of AC power; a second voltage sensor for a counter electromotive force (EMF) of the motor; a current sensor for an armature current of the motor; a digital processor having a first current controller responding to sensed armature current and a current reference, a cooperating second current controller responding to sensed peak voltage, sensed counter EMF and the current reference signal, and a gating circuit responding to the controllers; and a thyristor converter circuit sequentially gating portions of half cycles of AC power to the motor in response to firing signals from the gating circuit. The controllers may control a gate angle of the firing signals, the control system may include a third voltage sensor for a terminal voltage of the motor, and the armature current may have discontinuous and continuous waveforms.

Abstract: An apparatus for stabilizing the speed of a motor has a phase comparator that identifies a phase difference between a reference signal and a speed signal. The apparatus acquires the speed of the motor and generates an output signal proportional to the identified phase difference. A controller receives the output signal. A control circuit for the motor is connected to the controller. The phase comparator comprises a sample-and-hold element, a sampling pulse shaper that is connected thereto and is input with the speed signal, a pulse shaper input with the reference signal, and a signal generator connected to the output of the pulse shaper and to the input of the sample-and-hold element.

Abstract: A circuit automatically changes the gain in a PLL for driving a motor of the type having a motor speed signal that indicates the speed of motor rotation. The circuit includes a phase detector for sensing a phase difference between the motor speed signal and a reference frequency and for producing an output signal of duration proportional to the sensed phase difference. A counter counts clock pulses throughout the duration of the output signal, and a motor driving circuit drives the motor in response to the count reached by the counter. A source of clock pulses provides clock signals at first and second frequencies, the second frequency being lower than the first frequency, and a lock range sense circuit produces a sense signal output that indicates when the PLL is within a predetermined phase difference range.

Abstract: Synchronization of the output of an internally-driven VCO to an exterior clock signal is obtained by using the exterior clock signal to re-start the VCO at every exterior clock pulse, until the pre-set VCO frequency is reached. At that point, the restarting of the VCO ceases, and the VCO locks onto the internal signal it is designed to track. One application of this circuit is for enabling a smooth transition between open-loop, ramp-up of a polyphase DC motor to closed loop operation. Implementation of the circuit described phase-synchronizes the output of a phase-switching PLL loop, which is tracking the back emf of the motor, to the external clock used for motor ramp-up, so that there is no "jolt" in the motor at the transition from open-loop to closed-loop operation of the motor.

Abstract: A speed controller is equipped to a step motor for controlling the rotation of the step motor with a desired angular velocity. The step motor speed controller utilizes a phase-locked stepping servomechanism (PLSS) in which a phase-controlled oscillator (PCO) comprised of an adaptive digital-pumped controller (ADPC) and a voltage-controller oscillator (VCO) is employed. The step motor speed controller utilizes a tachometer comprised of an optical encoder for detecting the angular speed of the step motor. The tachometer sends out a first pulse train with the frequency thereof indicating the angular velocity of the step motor as a feedback signal to the ADPC. A reference signal source is employed for sending a second pulse train to the ADPC. The ADPC compares the phase difference between the first pulse train and the second pulse train and whereby a signal corresponding the phase difference is sent to the VCO, causing the VCO to output a third pulse train to the step motor.

Abstract: The invention concerns a phase locked loop speed control circuit for controlling the speeds of two or more objects. It includes pulse generators for generating reference pulses, first counters for counting each of these reference pulses, encoders for detecting relative travelling distances of the objects, second counters for counting encoder pulses from the encoders, first subtracters for subtracting the outputs of the second counters from those of the first counters, second subtractors for subtracting the encoder pulses from the reference pulses, corrector sections for correcting the differences output by the first and the second subtractors, and adjusting sections for adjusting the movements of the objects based on the corrected differences.

Abstract: A motor speed control device for use in an image forming apparatus with a differential phase detection circuit for outputting differential phase data between the clock pulse and a frequency proportional signal representative of the motor speed and a differential speed detecting circuit for outputting differential speed data between the length of the clock signal and the length of the speed signal. A pulse width modulated signal obtained from the two signals controls the speed of the motor.

Abstract: A phase control circuit in which a first phase comparator compares an input frequency with a reference frequency. The output of the first phase comparator is connected to a controlled oscillator through a control stage. A second control stage is also connected to the input of the controlled oscillator which has an output connected to a second phase comparator which receives also the reference frequency at an input. The output of the second phase comparator is connected to an input of the second control stage. The first control stage is separated from the controlled oscillator to compensate the circuit automatically. The second control stage varies its output until the frequency at the controlled oscillator output equals the reference frequency. The second control stage maintains this level subsequent to compensation independent of the output from the second phase comparator, and the first control stage is reconnected to the input terminal of the controlled oscillator.

Abstract: A system for driving a brushless motor comprises motor drive coils belonging to a plurality of phases respectively, a plurality of pairs of drive transistors connected to the drive coils respectively, a distribution circuit for sequentially distributing drive-coil energization switching signals to the plural drive transistors respectively, a slope synthesizer for smoothing leading and trailing slope portions of the drive-coil energization switching signals so as to apply the smoothed energization switching signals to the drive transistors respectively through the distribution circuit, a voltage-controlled oscillator for supplying a signal having a suitable frequency as an input to the slope synthesizer, a phase error detector for detecting the phase difference between counter-electromotive voltages induced in the drive coils and the drive-coil energization switching signals in a driver-coil energization pause period, and an error amplifier for amplifying the output signal of the phase error detector and apply

Abstract: A motor control system and related method are provided for phase and frequency locked operation of multiple spindle motors in a computer disk drive environment or the like, for coupling two or more disk drive units together to provide expanded data storage capability. The control system comprises a hybrid digital and analog network for producing a pulse width modulated control signal to control a disk drive spindle motor in a manner achieving frequency and phase locked relation with a reference signal. Multiple spindle motors are similarly driven in relation with the same reference signal, whereby the spindle motors are frequency and phase locked with respect to each other to permit, for example, parallel data transfer among the multiple disk drive units.