Abstract: In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered clocks based on the first and second input streams, respectively. The method includes retiming and demultiplexing the first and second input data bits to generate n first recovered streams and n second recovered streams, respectively, each comprising first and second recovered data bits, respectively. The method further includes determining a phase difference between the first and second recovered clocks; aligning the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference; combining the first and second recovered data bits to generate an output stream; and retiming the first and second recovered data bits in the output stream based on either the first or second recovered clock.

Abstract: In one embodiment, a processor comprises at least one processor time stamp counter (TSC) and a control unit coupled to the processor TSC. The processor TSC corresponds to a TSC that is defined to increment at a TSC clock frequency even though the processor is configurable to operate at one of a plurality of clock frequencies. The control unit is configured to maintain the processor TSC, and is configured to update the processor TSC when the processor is operating at a current clock frequency of the plurality of clock frequencies, wherein the update comprises adding a value to the processor TSC, and wherein the value is based on the ratio of the TSC clock frequency and the current clock frequency.