Front And Back Of Substrate Coated (excluding Processes Where All Coating Is By Immersion) Patents (Class 427/96.9)
  • Patent number: 9093736
    Abstract: Disclosed herein are a common mode filter and a method for manufacturing the same. The common mode filter includes a first insulator sheet; a first circuit layer having a first-layered first coil and a first-layered second coil alternately and separately arranged; a second insulator sheet laminated on the first circuit layer; and a second circuit layer having a second-layered first coil and a second-layered second coil alternately and separately arranged, the second-layered first coil being connected to the first-layered first coil and the second-layered second coil being connected to the first-layered second coil through the plurality of penetration holes.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: July 28, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jin Gu Kim, Jong Yun Lee, Young Do Kweon, Chang Bae Lee, Young Seuck Yoo
  • Patent number: 9054097
    Abstract: An integrated circuit (IC) package for an IC device, and a method of making the same. The IC package includes an interconnect assembly with at least one printed compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of printed conductive traces electrically coupling a plurality of the first and second contact members. The compliant layer is positioned to bias at least the first contact members against terminals on the IC device. Packaging substantially surrounds the IC device and the interconnect assembly. The second contact members are accessible from outside the packaging.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: June 9, 2015
    Assignee: HSIO TECHNOLOGIES, LLC
    Inventor: James Rathburn
  • Publication number: 20150075845
    Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. According to a preferred embodiment of the present invention, the printed circuit board includes: a base substrate; an inner layer build-up layer formed on the base substrate and including a first inner layer circuit layer, a second inner layer circuit layer, an inner layer insulating layer, and an inner layer via having a tapered section; and an outer layer build-up layer formed on the inner layer build-up layer and including an outer layer circuit layer, an outer layer insulating layer, and an outer layer via having a rectangular section.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 19, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Ki Young Yoo
  • Publication number: 20150010694
    Abstract: The method of manufacturing a substrate includes: forming a penetrating hole in a base layer; inserting a metal dummy part in the penetrating hole; forming an insulating portion made of synthetic resin to fill a ring-shaped gap between the penetrating hole and the dummy part; forming lower insulating layers, covering the bottom surface of the dummy part, that are made of synthetic resin on the bottom surface of the base layer to be continuous with the insulating portion; forming upper insulating layers, covering the top surface of the dummy part, that are made of synthetic resin on the top surface of the base layer to be continuous with the insulating portion; forming an exposing hole by routing in the upper insulating layers to expose the top surface of the dummy part; and forming a cavity by removing the dummy part exposed through the exposing hole by etching.
    Type: Application
    Filed: June 26, 2014
    Publication date: January 8, 2015
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Masashi MIYAZAKI, Yuichi SUGIYAMA, Tatsuro SAWATARI, Hideki YOKOTA, Yutaka HATA
  • Publication number: 20140267945
    Abstract: The present disclosure relates to a touch panel, and more particularly, to a touch panel having no or a reduced number of frames. The touch panel includes a substrate, a plurality of first electrodes, and second electrodes, wherein the first electrodes and the second electrodes are disposed on two opposite sides of the substrate, respectively. The first electrodes extend along an initial direction from initial positions and divert from the initial direction to terminate in first termination positions. The second electrodes extend from second initial positions and terminate in second termination positions along a second direction.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: TPK TOUCH SOLUTIONS (XIAMEN) INC.
    Inventors: Yuh-Wen Lee, Keming Ruan, Fengming Lin
  • Patent number: 8662008
    Abstract: A non-contact edge coating apparatus applies coating material to an edge of a non-circular solar cell substrate without physical contact. The apparatus may include a rotatable substrate support configured to hold the substrate. The apparatus may further include an applicator configured to receive a coating material and apply the coating material to an edge of the substrate while the substrate is rotated without any portion of the applicator physically touching the edge of the substrate. The substrate support may be mechanically coupled to a cam, which contacts a follower mechanically coupled to the applicator. A variety of coating materials may be employed with the apparatus including hot melt ink and UV curable plating resist.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: March 4, 2014
    Assignee: SunPower Corporation
    Inventors: Emmanuel Abas, Luca Pavani
  • Publication number: 20130334694
    Abstract: A packaging substrate is provided, including: a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant formed in the first openings; a second encapsulant formed in the second openings; and a surface circuit layer formed on the first encapsulant and the first core circuit layer. The present invention effectively reduces the fabrication cost and increases the product reliability.
    Type: Application
    Filed: October 4, 2012
    Publication date: December 19, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Yu-Chih Yu, Ying-Chou Tsai
  • Publication number: 20130299220
    Abstract: Provided is a touch panel. The touch panel includes a substrate and an electrode member disposed on the substrate. The electrode member includes a base material for electrode having first and second surfaces opposite to each other, a first electrode disposed on the first surface, and a second electrode disposed on the second surface.
    Type: Application
    Filed: December 20, 2011
    Publication date: November 14, 2013
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Dong Youl Lee, Young Jin Noh, Young Sun You, Sun Young Lee, Yong Jin Lee, Kyoung Hoon Chai
  • Publication number: 20130186679
    Abstract: The multilayer wiring structure includes: a substrate; a connection hole formed to pass through one surface and another surface of the substrate; and electrode wirings formed on the substrate, wherein the electrode wirings includes: a plurality of first wirings formed on one surface of the substrate; a plurality of second wirings formed on another surface of the substrate; and a plurality of connection wirings formed on an inner surface of the connection hole and electrically connecting the plurality of first wirings and the plurality of second wirings, respectively.
    Type: Application
    Filed: January 7, 2013
    Publication date: July 25, 2013
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: SAMSUNG ELECTRO-MECHANICS CO., LTD.
  • Patent number: 8377506
    Abstract: A substrate structure is provided. The substrate structure includes a substrate, a first insulation layer, a conductive part, a second insulation layer, a seed layer and a conductive layer. The substrate has a first circuit pattern layer and a second circuit pattern layer, which are located on two opposite surfaces of the substrate respectively. The first insulation layer formed on the first circuit pattern layer has a first insulation hole, which exposes a first opening in the outer surface of the first insulation layer. The conductive part formed on the first insulation hole for electrically connecting with a chip is enclosed by the edge of the first opening. The second insulation layer formed on the second circuit pattern layer has a second insulation hole in which the seed layer is formed. The conductive layer is formed on the seed layer for electrically connecting with a circuit board.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: February 19, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Chih-Cheng Lee
  • Patent number: 8334452
    Abstract: Certain example embodiments of this invention relate to an electrode (e.g., front electrode) for use in a photovoltaic device or the like. In certain example embodiments, a transparent conductive oxide (TCO) based front electrode for use in a photovoltaic device is of or includes zinc oxide, or zinc aluminum oxide, doped with yttrium (Y). In certain example embodiments, the addition of the yttrium (Y) to the conductive zinc oxide or zinc aluminum oxide is advantageous in that potential conductivity loss of the electrode can be reduced or prevented. In other example embodiments, a low-E coating may include a layer of or including zinc oxide, or zinc aluminum oxide, doped with yttrium (Y).
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: December 18, 2012
    Assignee: Guardian Industries Corp.
    Inventor: Alexey Krasnov
  • Patent number: 8322300
    Abstract: A non-contact edge coating apparatus includes an applicator for applying a coating material on an edge of a solar cell substrate and a control system configured to drive the applicator. The control system may drive the applicator along an axis to maintain a distance with an edge of the substrate as the substrate is rotated to have the edge coated with a coating material. The applicator may include a recessed portion into which the edge of the substrate is received for edge coating. For example, the applicator may be a roller with a groove. Coating material may be introduced into the groove for application onto the edge of the substrate. A variety of coating materials may be employed with the apparatus including hot melt ink and UV curable plating resist.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: December 4, 2012
    Assignee: SunPower Corporation
    Inventors: Luca Pavani, Emmanuel Abas
  • Publication number: 20120301630
    Abstract: A method for forming a flexible printed circuit board is provided. First, an insulating substrate with a first side and a second side is provided. Second, a through hole connecting the first side and the second side is formed in the insulating substrate. Then, a printing step is carried out to print a conductive precursor which is on the first side and cover and fill the through hole. Later, the conductive precursor is cured to form a conductive composition and to simultaneously form a circuit to obtain a flexible printed circuit board. The conductive composition includes at least one of carbon and silver.
    Type: Application
    Filed: September 22, 2011
    Publication date: November 29, 2012
    Inventor: Chin-Chun Huang
  • Publication number: 20120229990
    Abstract: A printed wiring board has a metal layer, a resin structure having a first resin layer portion formed on a first surface of the metal layer, a second resin layer portion formed on a second surface of the metal layer, and a filler resin portion filling an opening portion of the metal layer, a first circuit formed on the first resin portion, a second circuit formed on the second resin portion, and a through-hole conductor formed through the first resin, filler resin and second resin portions and connecting the first and second circuits. The through-hole conductor has a first portion narrowing from the first circuit toward the second resin portion and a second portion narrowing from the second circuit toward the first resin portion, and the first portion is connected to the second portion at a connected position shifted from the middle point of the thickness of the metal layer.
    Type: Application
    Filed: February 24, 2012
    Publication date: September 13, 2012
    Applicant: IBIDEN CO., LTD.
    Inventors: Takema ADACHI, Liyi Chen
  • Publication number: 20120199386
    Abstract: A printed wiring board including a core substrate having a metal layer, a first resin insulation layer on a surface of the metal layer and a second resin insulation layer on the opposite surface of the metal layer, a first conductive circuit formed on the first layer, a second conductive circuit formed on the second layer, and a through-hole conductor formed in a penetrating hole through the substrate and connecting the first and second circuits. The metal layer has an opening filled with a filler resin, the penetrating hole has a first opening in the first layer, a second opening in the second layer and a third opening in the filler resin, the first opening tapers toward the filler resin, the second opening tapers toward the filler resin, and the third opening is connecting the first and second openings.
    Type: Application
    Filed: December 14, 2011
    Publication date: August 9, 2012
    Applicant: IBIDEN CO., LTD.
    Inventors: Takema Adachi, Liyi Chen
  • Publication number: 20120064230
    Abstract: The steps of the present invention are as follows: (a) a detachable film is formed on both sides of a substrate, respectively; (b) a number of vias running through both sides of the detachable films are formed in the substrate; (c) the vias are filled with a conductive paste; (d) the detachable films are peeled off; (e) a metallic conductive layer is deposited on both sides of the substrate, respectively; (f) a specific mold pattern is formed on the metallic conductive layers, respectively, by a photolithographic process; (g) a metallic circuit layout layer is formed on the patterns, respectively, by an electrochemical process; and (h) the mold patterns and the metallic conductive layers are removed. As such, the substrate is not contaminated by the conductive paste. Further, by using deposition, metallic conductive layers are directly adhered to the substrate and, by using photolithography, layouts with small linewidth could be formed.
    Type: Application
    Filed: September 13, 2010
    Publication date: March 15, 2012
    Inventors: Shih-Long Wei, Sheng-Li Hsiao, Chien-Hung Ho, Hsiao-Chun Liu
  • Patent number: 8058189
    Abstract: A method and apparatus for resisting ballistic impact including an outer energy absorbing assembly having a plurality of interconnected fibers, and a barrier positioned behind the outer energy absorbing assembly. A movement restraint is positioned behind the barrier and a dampener is positioned intermediate the barrier and the restraint.
    Type: Grant
    Filed: February 9, 2008
    Date of Patent: November 15, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Khosrow Nematollahi, Robert L. Hager
  • Publication number: 20110183144
    Abstract: A varnish includes an epoxy resin, a curing agent, an accelerator agent and fillers. The fillers include inorganic mineral powders. The inorganic mineral powders have composition of SiO2 in weight ratio of 55±5% and a composition of aluminum compound in weight above 35%. Glass fabric cloth is dipped into the varnish so as to form a prepreg with better machined-work capability.
    Type: Application
    Filed: January 27, 2010
    Publication date: July 28, 2011
    Inventor: LAI TU LIU
  • Publication number: 20110147059
    Abstract: Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Inventors: Qing Ma, Chuan Hu, Patrick Morrow
  • Publication number: 20110079421
    Abstract: Disclosed herein is a printed circuit board, including: a base substrate; insulation layers which are formed on both sides of the base substrate and in which trenches are formed; and circuit layers including circuit patterns and vias formed in the trenches using a plating process. The printed circuit board is advantageous in that trenches are formed in both sides of a base substrate, so that a fine circuit pattern can be simultaneously formed on both sides thereof, thereby simplifying the manufacturing process thereof.
    Type: Application
    Filed: December 9, 2009
    Publication date: April 7, 2011
    Inventors: Young Gwan KO, Ryoichi Watanabe, Sang Soo Lee, Se Won Park
  • Publication number: 20110061906
    Abstract: A printed circuit board (PCB) and a fabrication method thereof are disclosed. The PCB includes: a dual-layered circuit pattern formed with a desired pattern on at least one of upper and lower surfaces of an insulation base member (i.e., an insulation substrate) and having metal layers each having a different thermal expansion coefficient; and an insulating layer formed on the insulation base member to cover the circuit pattern. Because the PCB includes an anti-warping unit, a processing rate and productivity can be improved.
    Type: Application
    Filed: December 18, 2009
    Publication date: March 17, 2011
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Min Jung Cho, Mi Sun Hwang, Jae Joon Lee, Myung Sam Kang
  • Publication number: 20110061917
    Abstract: A laminated substrate for an integrated circuit package, including a core layer and at least one build-up layer located above only one side of said core layer. An integrated circuit package, including a laminated substrate and including an integrated circuit die placed above the side build-up layer.
    Type: Application
    Filed: September 11, 2009
    Publication date: March 17, 2011
    Applicant: ST-ERICSSON SA
    Inventors: Nedyalko Slavov, Heinz-Peter Wirtz, Kwei-Kuan Kuo
  • Publication number: 20100314755
    Abstract: Disclosed is a printed circuit board, which includes a first circuit layer embedded in one surface an insulating layer and including a bump pad and a wire bonding pad, thus realizing a high-density wire bonding pad. A semiconductor device including the printed circuit board and a method of manufacturing the printed circuit board are also provided.
    Type: Application
    Filed: July 29, 2009
    Publication date: December 16, 2010
    Inventors: Myung Sam KANG, Mi Sun Hwang, Ok Tae Kim, Seon Ha Kang, Gil Yong Shin, Kil Yong Yun, Min Jung Cho
  • Patent number: 7811626
    Abstract: Provided is a method of manufacturing a printed circuit board. In an embodiment, the method includes forming a prepreg layer via a reel method, forming a conductive film for forming a circuit pattern on at least one surface of the prepreg layer; and forming a predetermined circuit pattern on the conductive film. In an embodiment, the prepreg layer has a thickness of at most about 0.15 mm and contains a fiber material and a resin material. In an embodiment, the content of the resin material in the prepreg layer is about 70% or less by volume. In an embodiment, the prepreg layer is composed of at least one prepreg layer.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: October 12, 2010
    Assignee: Samsung Techwin Co., Ltd.
    Inventors: Chang-soo Jang, Dong-kwan Won, Hyoung-ho Roh, Jae-chul Ryu
  • Publication number: 20100200540
    Abstract: An electronic package and methods by which the package reduces thermal fatigue failure of conductors in the electronic package. The electronic package includes a carrier substrate having first and second surfaces and a plurality of anchor vias having a via material extending from the first surface toward the second surface. The electronic package includes a first conducting layer having a length and a width extending laterally in two dimensions across a major part of the first surface of the carrier substrate. The anchor vias have plural attachments along the length and the width of the first conducting layer to secure the first conducting layer to the carrier substrate.
    Type: Application
    Filed: April 12, 2010
    Publication date: August 12, 2010
    Inventor: Robert O. Conn
  • Patent number: 7740768
    Abstract: A method and apparatus for cleaning a wafer. The wafer is heated and moved to a processing station within the apparatus that has a platen either permanently in a platen down position or is transferable from a platen up position to the platen down position. The wafer is positioned over the platen so as not to contact the platen and provide a gap between the platen and wafer. The gap may be generated by positioning the platen in a platen down position. A plasma flows into the gap to enable the simultaneous removal of material from the wafer front side, backside and edges. The apparatus may include a single processing station having the gap residing therein, or the apparatus may include a plurality of processing stations, each capable of forming the gap therein for simultaneously removing additional material from the wafer front side, backside and edges.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: June 22, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Haruhiro H Goto, David Cheung
  • Patent number: 7723152
    Abstract: In the condition where a nozzle for applying a coating liquid is disposed on the lower side of a substrate and a substrate surface controlled in wettability is faced down, the nozzle and the substrate are moved relative to each other, whereby the coating liquid is applied to a desired region of the substrate, and then the coating liquid is dried, to obtain a pattern included a dried coating layer.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: May 25, 2010
    Assignee: Sony Corporation
    Inventor: Akihiro Nomoto
  • Publication number: 20100116540
    Abstract: An end of a first line and an end of a second line of a first write wiring pattern are arranged on both sides of a third line of a second write wiring pattern. Circular connection portions are provided at the ends of the first line and the second line. In addition, through holes are formed in respective portions of a base insulating layer below the connection portions. Each connection portion comes in contact with a connecting region of a suspension body within the through hole.
    Type: Application
    Filed: November 3, 2009
    Publication date: May 13, 2010
    Applicant: NITTO DENKO CORPORATION
    Inventors: Jun ISHII, Toshiki NAITOU, Mitsuru HONJO
  • Patent number: 7704548
    Abstract: A method for manufacturing a wiring board which can simplify a manufacturing step. In a preparation step, a core board and an electronic component are prepared. In an insulating layer formation and fixing step, after accommodating the electronic component in an accommodation hole, a lowermost resin insulating layer is formed, and a gap between the electronic component and the core board is filled with a part of the lowermost resin insulating layer so as to fix the electronic component to the core board. In an opening portion formation step, a portion of the lowermost resin insulating layer located directly above the gap between the electronic component and the core board is removed so as to form an opening portion exposing a part of a core board main surface side conductor and a component main surface side electrode.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: April 27, 2010
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Tadahiko Kawabe, Masao Kuroda, Yasuhiro Sugimoto, Hajime Saiki, Shinji Yuri, Makoto Origuchi
  • Publication number: 20100021687
    Abstract: The invention relates to a composite material, a high-frequency circuit substrate made from the composite material and a making method of the high-frequency circuit substrate. The composite material includes: a thermosetting composition including a more than 60 percent of vinyl containing Butadiene styrene copolymer resin with molecular weight less than 11,000, a more than 60 percent of vinyl containing polybutadiene resin with polarity groups, and a maleic anhydride grafted polybutadiene styrene copolymer with molecular weight more than 50,000; a fiberglass cloth; a powder filler; and a cure initiator. The composite material of the prevent invention realizes easy manufacture of the prepreg and high bonding of the copper foil. The high-frequency circuit substrate made from the composite material has low dielectric constant, low dielectric loss tangent, and excellent heat resistance, and is convenient for process operation. Therefore, the composite material is suitable for making the circuit substrate.
    Type: Application
    Filed: November 7, 2008
    Publication date: January 28, 2010
    Inventor: MIN SHE SU
  • Publication number: 20080121183
    Abstract: A clamping jig for mounting semiconductor laser bars includes: multiple supporting bars for holding laser bars therebetween; a pair of supporting plates each of which has a mounting face for mounting the supporting bars in a row; a pressing member for pressing the supporting bars for holding the laser bar; pressing cover members for covering both ends of each supporting bar to prevent supporting bars from falling from the supporting plate; and a supporting frame for detachably supporting the supporting plates and pressing cover members. Each supporting bar is formed with a longitudinal length greater than the laser bar, within a predetermined length so as to be mounted within the supporting frame. Both of the pair of supporting plates may be mounted so as to face one another, or just one may be mounted with the pressing cover members being mounted on the supporting frame instead of the other supporting plate.
    Type: Application
    Filed: November 15, 2007
    Publication date: May 29, 2008
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Nobuyuki Mitsui, Hiroshi Inada
  • Patent number: 7348677
    Abstract: A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e.g., with metal plating, or conductive or non-conductive paste. In the case of the latter, it is also possible to provide a top covering conductive layer over the paste, e.g., to serve as a pad or the like on the board's external surface.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: March 25, 2008
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: James M. Larnerd, John M. Lauffer, Voya R. Markovich, Kostas I. Papathomas
  • Patent number: 7213334
    Abstract: A double-sided flexible printed board is manufactured by: (a) forming a polyimide precursor layer on a metal layer; (b) forming an upper circuit layer on the polyimide precursor layer by a semi-additive technique; and (c) imidating the polyimide precursor layer to form a polyimide insulating layer.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: May 8, 2007
    Assignees: Sony Corporation, Sony Chemical & Information Device Corporation
    Inventors: Hideyuki Kurita, Masanao Watanabe
  • Patent number: 7211289
    Abstract: A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e.g., with metal plating, or conductive or non-conductive paste. In the case of the latter, it is also possible to provide a top covering conductive layer over the paste, e.g., to serve as a pad or the like on the board's external surface.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: May 1, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: James M. Larnerd, John M. Lauffer, Voya R. Markovich, Kostas I. Papathomas
  • Patent number: 6935023
    Abstract: A method of forming an electrical connection for a fluid ejection device including a fluid channel communicating with a first side and a second side of the fluid ejection device and an array of drop ejecting elements formed on the first side of the fluid ejection device includes forming a trench in the second side of the fluid ejection device, depositing a conductive material in the trench, forming a first opening in the fluid ejection device between the first side of the fluid ejection device and the conductive material in the trench, depositing a conductive material in the first opening, and forming a conductive path between the conductive material in the first opening and a wiring line of one of the drop ejecting elements.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: August 30, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Timothy E. Beerling, Timothy L. Weber, Melissa D. Boyd