Abstract: A coil electrode included in an inductor component includes a plurality of metal pins upper end surfaces of which are exposed to the upper surface of a resin layer and lower end surfaces of which are exposed to a lower surface of the resin layer, and a plurality of wiring patterns that connect the upper end surfaces or the lower end surfaces of the predetermined metal pins, wherein surface roughnesses of the upper surface and the lower surface of the resin layer are larger than surface roughnesses of the upper end surfaces and the lower end surfaces of the respective metal pins, and wiring patterns are respectively formed on the upper and lower surfaces of the resin layer by plating.

Abstract: A method for manufacturing a touch screen which includes: providing a substrate including a display area and a non-display area located around the display area; forming a first transparent conductive layer on a side of the substrate, and forming a metal layer on a surface of the first transparent conductive layer facing away from the substrate; forming a first photoresist pattern on the metal layer, at least a portion of the first photoresist pattern corresponding to a metal trace to be formed in the non-display area; performing an etching process by using the first photoresist pattern to form the metal trace; forming a second photoresist pattern only in one of the display area and the non-display area, and performing an etching process to form a first transparent conductive pattern in the display area.

Abstract: A touch sensor includes a base layer; an electrode layer including, on the base layer, first array sensing cells connected and arranged in a first direction and second array sensing cells spaced apart from the first array sensing cells and arranged spaced apart in a second direction, the first and second sensing cells being provided with dummy holes; an insulation layer formed on the electrode layer and being provided with contact holes connecting the neighboring second array sensing cells in the second direction; and bridges formed on the contact hole and the insulation layer to electrically connect the neighboring second array sensing cells.

Abstract: A method of constructing conductive material in arbitrary three-dimensional (3D) geometries, such as 3D printing. The method may include selective application of an aerosol-based colloidal solution containing a catalytic palladium nanoparticle material onto a substrate and then immersion of the coated substrate into an electro-less plating bath for deposition of conductive copper material. The above steps may be repeated to create arbitrary 3D geometric constructs containing conductive metallic patterns.

Abstract: A touch input device comprises a body having a plurality of hole portions; and a signal transfer unit formed in the body, wherein the signal transfer unit is provided to pass on the body between the hole portions adjacent thereto to recognize a user's touch signal.

Abstract: The present disclosure relates to a method of forming an integrated circuit. In some embodiments, the method may be performed by forming a lower interconnect structure within a first inter-level dielectric (ILD) layer over an upper surface of a substrate, and forming a resistive random access memory (RRAM) device over the lower interconnect structure. A second ILD layer is formed over the RRAM device. The second ILD layer is patterned to remove a part of the second ILD layer that defines a cavity. The cavity vertically extends from an upper surface of the second ILD layer to an upper surface of the RRAM device and laterally extends past opposing sidewalls of the RRAM device. An upper interconnect wire is formed within the cavity.

Abstract: A package apparatus comprises a first wiring layer, a first dielectric material layer, a first conductive pillar layer, a first buffer layer, a second wiring layer, and a protection layer. The first wiring layer has a first surface and a second surface opposite to the first surface. The first dielectric material layer is disposed within partial zone of the first wiring layer. The first conductive pillar layer is disposed on the second surface of the first wiring layer. The first buffer layer is disposed within partial zone of the first conductive pillar layer. The second wiring layer is disposed on the first buffer layer and one end of the first conductive pillar layer. The protection layer is disposed on the first buffer layer and the second wiring layer.

Abstract: A device includes a hermetically sealed case with electronic circuitry housed within. One surface of the hermetically sealed case includes a metallic plate and a co-fired ceramic electrical feedthrough with a number of vias. The co-fired ceramic electrical feedthrough is hermetically joined to the metallic plate and a hybrid circuit is connected to the feedthrough.

Abstract: Apparatus and methods related to negative differential resistance (NDR) are provided. An NDR device includes a spaced pair of electrodes and at least two different materials disposed there between. One of the two materials is characterized by negative thermal expansion, while the other material is characterized by positive thermal expansion. The two materials are further characterized by distinct electrical resistivities. The NDR device is characterized by a non-linear electrical resistance curve that includes a negative differential resistance range. The NDR device operates along the curve in accordance with an applied voltage across the pair of electrodes.

Abstract: A solder on trace device includes a conductive trace on a semiconductor substrate surface. The conductive trace has a sidewall and a bonding surface. The solder on trace device also includes a passivation layer on at least one end of the conductive trace. The solder on trace device further includes a pre-solder material on the sidewall and the bonding surface of the conductive trace.

Abstract: A structure of via hole of electrical circuit board includes an adhesive layer and a conductor layer that are formed after wiring is formed on a carrier board. At least one through hole extends in a vertical direction through the carrier board, the wiring, the adhesive layer, and the conductor layer and forms a hole wall surface. The conductor layer shows a height difference with respect to an exposed zone of the circuit trace in the vertical direction. A conductive cover section covers the conductor layer and the hole wall surface of the through hole. The carrier board is a single-sided board, a double-sided board, a multi-layered board, or a combination thereof, and the single-sided board, the double-sided board, and multi-layered board can be flexible boards, rigid boards, or composite boards combining flexible and rigid boards.

Abstract: A wiring substrate includes a first insulating layer, an adhesion insulating layer formed under the first insulating layer and an outer face of the adhesion insulating layer is made to a roughened face, a first wiring layer formed on the first insulating layer, a second insulating layer formed on the first insulating layer, and in which a first via hole reaching the first wiring layer is provided, a second wiring layer formed on the second insulating layer, and connected to the first wiring layer through the first via hole, a second via hole formed in the adhesion insulating layer and the first insulating layer, and reaching the first wiring layer, and a third wiring layer formed on the outer face of the adhesion insulating layer, and connected to the first wiring layer through the second via hole.

Abstract: A circuit substrate includes: a substrate; an insulating coating layered structure formed on the substrate, having top and bottom surfaces, and formed with a patterned recess that is indented inwardly from the top surface, that is disposed above the bottom surface, and that is defined by a recess-defining wall, the recess-defining wall having a bottom wall portion and a surrounding wall portion that extends upwardly from a periphery of the bottom wall portion; and a patterned metallic layered structure including an electroless plating metal layer formed on the bottom wall portion of the recess-defining wall.

Abstract: For the production of a flexible circuit configuration, which contains a layer sequence and a film connected thereto, for the creation of through contacts through the film up to terminal surfaces of the layer sequence, it is proposed that the film be connected unstructured to the layer sequence provided in a defined position on the substrate and then, while the composite of layer sequence and film remains on the substrate, perforations be created through the film up to terminal surfaces of a conductive layer of the layer sequence and contact metal be deposited in structured form on the film and in the perforations as through contacts.

Abstract: A thermal management circuit material comprises a thermally conductive metallic core substrate, metal oxide dielectric layers on both sides of the metallic core substrate, electrically conductive metal layers on the metal oxide metal oxide dielectric layers, and at least one through-hole via filled with an electrically conductive metal-containing core element connecting at least a portion of each of the electrically conductive metal layers, wherein the containing walls of the through-hole via are covered by a metal oxide dielectric layer connecting at least a portion of the metal oxide dielectric layers on opposite sides of the metallic core substrate. Also disclosed are methods of making such circuit materials, comprising forming metal oxide dielectric layers by oxidative conversion of a surface portion of the metallic core substrate. Articles having a heat-generating electronic device such as an HBLED mounted in the circuit material are also disclosed.

Abstract: A flexible multilayer substrate includes a multilayer body including a plurality of laminated resin layers. The multilayer body includes an innermost surface, which is a surface on an inner side when the substrate is bent, and an outermost surface, which is a surface on an outer side when the substrate is bent. Each of the plurality of resin layers includes a skin layer on one surface. Lamination of the multilayer body includes a skin layer joint plane at one location at a central portion in the thickness direction, and the skin layer and other surface come in contact with each other at another location along the central portion in the thickness direction. A skin layer joint plane is arranged on a side closer to the innermost surface than a central plane in the thickness direction of the multilayer body.

Abstract: Provided is a method for manufacturing a probe card which inspects electrical characteristics of a plurality of semiconductor devices in batch. The method includes: a step of forming a plurality of probes, which are to be brought into contact with external terminals of the semiconductor devices, on one side of a board which forms the base body of the probe card; a step of forming on the board, by photolithography and etching, a plurality of through-holes which reach the probes from the other side of the board; a step of forming, in the through-holes, through electrodes to be conductively connected with the probes, respectively; and a step of forming wiring, which is conductively connected with the through electrodes, on the other side of the board.

Abstract: Disclosed herein is an interposer substrate, including: a core layer and a through core via (TCV) penetrating through the core layer; circuit wirings formed on both surfaces of the core layer and a TCV upper pad and a TCV lower pad which are each bonded to upper and lower surfaces of the TCV formed on both surfaces of the core layer; upper insulating layers covering the TCV upper pad and the circuit wiring formed on one surface of the core layer and having the circuit wirings formed on upper surfaces thereof; a stack via penetrating through the upper insulating layers of each layer and having one end connected to the TCV upper pad; and a lower insulating layer covering the TCV lower pad and the circuit wiring formed on the other surface of the core layer and provided with an opening which exposes the TCV lower pad.

Abstract: A method of manufacturing a thin support package structure includes the steps of: preparing a support plate formed with a plurality of grooves adjacent to an outer rim thereof, forming a releasing material layer on the support plate; forming a first circuit layer on the releasing material layer so as to form a thin circuit board; forming a dielectric layer on the releasing material layer; forming a plurality of openings in the dielectric layer; forming a second circuit layer on the dielectric layer; forming connection plugs by filling the openings; forming a solder mask on the dielectric layer; forming a plurality of notches on the lower surface of the support plate to communicate with the grooves, respectively; and removing the central part of the support plate between the notches and the central part of the releasing material on the support plate.

Abstract: There is provided a multilayer wiring substrate, including: a trench produced at one surface of an insulation layer, the trench having a depth shallower than a thickness of the insulation layer; and a copper plating applied to the trench. Also, there are provided a method of producing the multilayer wiring substrate, and a semiconductor product including the multilayer wiring substrate.

Abstract: The present invention provides a single-layer multi-point touch-control conductive film and a method for producing the same.

Abstract: Disclosed is a carrier for manufacturing a printed circuit board, which includes a first carrier including a first binder having a first opening and a first metal layer formed in the first opening of the first binder, and a second carrier, stacked with the first carrier and including a second binder having a second opening and a second metal layer which is formed in the second opening of the second binder and which partially overlaps with the first metal layer, so that the carrier is simply configured and the binders are formed not only on the lateral surfaces of the metal layers but also on the upper surfaces thereof, thus improving the reliability of bonding of the carrier at the periphery. A method of manufacturing the carrier and a method of manufacturing a printed circuit board using the carrier are also provided.

Abstract: This disclosure provides implementations of inductors, transformers, and related processes. In one aspect, a device includes a substrate having first and second surfaces. A first inducting arrangement includes a first set of vias, a second set of vias, a first set of traces arranged over the first surface connecting the first and second vias, and a second set of traces arranged over the second surface connecting the first and second vias. A second inducting arrangement is inductively-coupled and interleaved with the first inducting arrangement and includes a third set of vias, a fourth set of vias, a third set of traces arranged over the first surface connecting the third and fourth vias, and a fourth set of traces arranged over the second surface connecting the third and fourth vias. One or more sets of dielectric layers insulate portions of the traces from one another.

Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.

Abstract: The invention provides a method for manufacturing a thin film substrate. The method comprises steps of: providing a substrate having at least one through hole; forming a first metallic layer on a surface of the substrate and the through holes; forming a resist layer and a first opening on the first metallic layer; forming a second metallic layer in the first opening and the through hole; removing the resist layer and a part of the first metallic layer to form a circuit layer and a plurality of grooves; forming a solder mask layer on the circuit layer and in the groove, and forming a second opening on the solder mask layer to expose a part of the circuit layer; and polishing the surface of the exposed circuit layer and the solder mask layer.

Abstract: A method is provided which includes forming a metal layer and converting at least a portion of the metal layer to a hydrated metal oxide layer. Another method is provided which includes selectively depositing a dielectric layer upon another dielectric layer and selectively depositing a metal layer adjacent to the dielectric layer. Consequently, a microelectronic topography is formed which includes a metal feature and an adjacent dielectric portion comprising lower and upper layers of hydrophilic and hydrophobic material, respectively. A topography including a metal feature having a single layer with at least four elements lining a lower surface and sidewalls of the metal feature is also provided herein. The fluid/s used to form such a single layer may be analyzed by test equipment configured to measure the concentration of all four elements. In some cases, the composition of the fluid/s may be adjusted based upon the analysis.

Abstract: A printed wiring board includes an insulating substrate having a penetrating hole formed through the substrate, a first conductive pattern formed on first surface of the substrate, a second conductive pattern formed on second surface of the substrate on the opposite side of the first surface, and a through-hole conductor formed in the penetrating hole in the substrate such that the conductor is connecting the first conductive pattern on the first surface of the substrate and the second conductive pattern on the second surface of the substrate. The penetrating hole has a first opening portion opening on the first surface of the substrate, a second opening portion opening on the second surface of the substrate and a third opening portion connecting the first and second opening portions, and the third opening portion has the maximum diameter which is greater than the minimum diameters of the first and second opening portions.

Abstract: A method of fabricating flexible display device includes providing a flexible display panel having an uneven surface, and forming at least one filling layer on the uneven surface of the flexible display panel. The filling layer includes an organic filling layer polymerized by a precursor layer, or an inorganic filling layer including nanometer-scale carbon structure.

Abstract: Methods for fabricating sub-lithographic, nanoscale microchannels utilizing an aqueous emulsion of an amphiphilic agent and a water-soluble, hydrogel-forming polymer, and films and devices formed from these methods are provided.

Abstract: A method is described for manufacturing a component having a through-connection. The method includes providing a substrate; forming a trench structure in the substrate, a substrate area which is completely surrounded by the trench structure being produced; forming a closing layer for closing off the trench structure, a cavity girded by the closing layer being formed in the area of the trench structure; removing substrate material from the substrate area surrounded by the closed-off trench structure; and at least partially filling the substrate area surrounded by the closed-off trench structure with a metallic material. A component having a through-connection is also described.

Abstract: Disclosed herein is a printed circuit board, including: a base substrate; a first insulating layer formed on the base substrate; a first via formed on the base substrate and formed to penetrate through the first insulating layer; a first plating layer formed to surround an upper part of the first insulating layer and a side and a lower part of the first via; a second via formed on at least one of the first via and the first insulating layer; and a second insulating layer formed on the first insulating layer and formed to surround a side of the second via.

Abstract: A circuit board and a manufacturing method thereof are provided. A dielectric layer is formed on a substrate, wherein an internal circuit layer is formed on the substrate and the dielectric layer covers the internal circuit layer. A first trench, a second trench and an opening are formed in the dielectric layer. The opening is located below the first trench and connected with the first trench, and a portion of the internal circuit layer is exposed by the opening. A patterned conductive layer is formed on the dielectric layer. The patterned conductive layer covers a portion of the dielectric layer and fills the first trench, the second trench and the opening so as to form a first circuit layer, a second circuit layer and a conductive through via, respectively, wherein the conductive through via is electrically connected with the first circuit layer and the internal circuit layer.

Abstract: The invention comprises methods for filling holes in printed wiring boards and printed wiring boards produced by these methods. The methods involve plating metal conductors inside the holes of the printed wiring boards while protecting the conducting surfaces of the printed wiring boards from being plated using photoresist film. The side surfaces of a printed wiring board are covered with photoresist. The photoresist is exposed to developing light, except the photoresist covering the holes on one side of the board is masked to prevent exposure of the holes to the developing light. The undeveloped photoresist covering the holes is removed. The board is subjected to a plating process, which deposits conductive materials in the holes, but the photoresist on the conducting surfaces of the board prevents conductive materials to be plated on the surfaces of the board.

Abstract: Provided is a circuit board having a tie bar buried therein. The circuit board includes a dielectric stack, at least a first tie bar, at least a first gold finger and at least a first microvia. The dielectric stack includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located on the second dielectric layer. The dielectric stack includes a wireline region and a gold finger region. The first tie bar is buried in the gold finger region between the first dielectric layer and the second dielectric layer. The at least a first gold finger is located in the gold finger region on the first dielectric layer. The first microvia is located in the gold finger region in the first dielectric layer, and electrically connects the first gold finger to the first tie bar.

Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.

Abstract: Disclosed herein are a printed circuit board and a method for manufacturing the same. The printed circuit board includes: a core reinforcement having stiffness; insulating layers formed on both surfaces of the core reinforcement; a through hole formed by penetrating through the insulating layer and the core reinforcement; and a circuit layer formed on the insulating layer and a plating layer formed in the through hole for implementing inter-layer connection of the circuit layers.

Abstract: Glass interposer panels and methods for forming the same are described herein. The interposer panels include a glass substrate core formed from an ion-exchangeable glass. A first layer of compressive stress may extend from a first surface of the glass substrate into the thickness T of the glass substrate core to a first depth of layer D1. A second layer of compressive stress may be spaced apart from the first layer of compressive stress and extending from a second surface of the glass substrate core into the thickness T of the glass substrate core to a second depth of layer D2. A plurality of through-vias may extend through the thickness T of the glass substrate core. Each through-via is surrounded by an intermediate zone of compressive stress that extends from the first layer of compressive stress to the second layer of compressive stress adjacent to a sidewall of each through-via.

Abstract: A method is provided which includes forming a metal layer and converting at least a portion of the metal layer to a hydrated metal oxide layer. Another method is provided which includes selectively depositing a dielectric layer upon another dielectric layer and selectively depositing a metal layer adjacent to the dielectric layer. Consequently, a microelectronic topography is formed which includes a metal feature and an adjacent dielectric portion comprising lower and upper layers of hydrophilic and hydrophobic material, respectively. A topography including a metal feature having a single layer with at least four elements lining a lower surface and sidewalls of the metal feature is also provided herein. The fluid/s used to form such a single layer may be analyzed by test equipment configured to measure the concentration of all four elements. In some cases, the composition of the fluid/s may be adjusted based upon the analysis.

Abstract: A method of manufacturing a printed circuit board includes forming a through hole 2 in an insulating layer 1 having upper and lower faces so as to penetrate between the upper and lower surfaces; allowing a first plated conductor 4 to be deposited at least in the through hole 2 and on the upper and lower surfaces around the through hole; removing the first plated conductor overlying and underlying a periphery of the through hole by etching the first plated conductor 4, while leaving at least the first plated conductor 4 in a mid-portion in a vertical direction within the through hole 2; and forming by semi-additive method a second plated conductor 6 that fills an outer portion than the first plated conductor 4 in the through hole 2, and forms a wiring conductor on the upper and lower surfaces.

Abstract: The present invention is a method for fabricating an electrode pair precursor which comprises the steps of creating on one surface of a substrate one or more indents of a depth less than approximately 10 nm and a width less than approximately 1 ?m; depositing a layer of material on the top of this structured substrate to forming a first electrode precursor; depositing another layer the first electrode precursor to form a second electrode precursor; and finally forming a third layer on top of the second electrode precursor.

Abstract: Provided is a method of manufacturing a touch screen panel. The method of manufacturing the touch screen panel includes preparing a substrate including a cell region and an interconnection region formed around the cell region, forming bridge electrodes arranged at a predetermined distance on the cell region of the substrate, forming an insulation layer on the substrate including the bridge electrodes, patterning the insulation layer to form contact holes exposing both ends of the bridge electrodes, and forming X-axis electrode extending in a first direction between the contact holes spaced apart from and facing each other and Y-axis electrode cells filling the contact holes and formed in a second direction perpendicular to the first direction. The bridge electrodes, the X-axis electrodes, and the Y-axis electrode cells are formed as hybrid electrodes, respectively.

Abstract: The invention relates to a method for producing a plastic molded part (9) comprising an integrated conductor path (3), which plastic molded part is used in particular as an intermediate product to be further processed into an electrically heatable mirror (1). The method steps are: a) producing a substrate (7) from a carrier body (2) made of an electrically insulating plastic material having a conductor path (3) made of an electrically conductive material on or in a surface (8) of the carrier body (2), b) flooding the surface (8) of the substrate (7) equipped with the conductor path (3) or the surface (11) of the substrate (7) opposite said surface with a liquid, electrically insulating coating material. The flooding evens out depressions due to uneven shrinkage in the thick and thin areas of the carrier body and a smooth surface can be produced, which can subsequently be covered with a reflective layer.

Abstract: Disclosed herein are a method of manufacturing a multilayer printed circuit board (PCB), a via which is an inner via hole (IVH) having a stable structure so as to easily form a fine pattern, thereby thinning a product, and a multilayer PCB manufactured via the same. The method includes preparing a base substrate including copper foils formed on opposite surfaces or a single surface of the base substrate; forming an insulating layer on the base substrate via a coating process; processing a via hole through the insulating layer formed on the base substrate up to the base substrate; performing fill plating on the via hole; and stacking at least one circuit layer on a metal layer that is formed via the fill plating.

Abstract: A method of manufacturing a coreless substrate having filled via pads, including: forming a first insulating layer on one side of a carrier forming a build-up layer including a build-up insulating layer and a build-up circuit layer having a build-up via on the first insulating layer, and forming a second insulating layer on the build-up layer; removing the carrier, and forming via-holes in the first and second insulating layers; and conducting a filled plating process in the via-holes of the first and second insulating layers thus forming first and second filled via pads therein.

Abstract: Printed circuit boards have circuit layers with one or more via filled holes with copper wraps and methods of manufacturing the same. An embodiment of the present invention provides a method to enhance the consistency of the wraparound plating of through-hole vias of printed circuit boards with (requiring) via filling to provide extra reliability to the printed circuit boards and enables the designers and/or manufacturers of printed circuit boards to design and manufacture boards with relatively fine features and/or tight geometries.

Abstract: A hybrid substrate according to the present invention comprises a core layer composed of a glass woven cloth as a reinforcing material, and a glass-ceramic sintered body which at least comprises a glass component and a metal oxide component. The glass woven cloth and the glass-ceramic sintered body formed by an impregnation with respect to the glass woven cloth are in a form of sintering integration with each other.

Abstract: A conductive paste comprising 88-94% by mass of Ag powder having an average particle size of 3 ?m or less and 0.1-3% by mass of Pd powder, the total amount of the Ag powder and the Pd powder being 88.1-95% by mass. A multilayer ceramic substrate obtained by laminating and sintering pluralities of ceramic green sheets, and having conductor patterns and via-conductors inside, the via-conductors being formed in via-holes having diameters of 150 ?m or less after sintering, containing Ag crystal particles having a particle size of 25 ?m or more, and having a porosity of 10% or less.

Abstract: A method of manufacturing a multilayer printed wiring board includes forming a first interlaminar resin insulating layer, a first conductor circuit on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer, opening portions in the second interlaminar resin insulating layer to expose a face of the first conductor circuit, an electroless plating film on the second interlaminar resin insulating layer and the exposed face, and a plating resist on the electroless plating film. The method further includes substituting the electroless plating film with a thin film conductor layer, having a lower ion tendency than the electroless plating film, and a metal of the exposed face, forming an electroplating film including the metal on a portion of the electroless plating film and the thin film conductor layer, stripping the plating resist, and removing the electroless plating film exposed by the stripping.

Abstract: A structure for a core layer of a substrate and a method for fabricating a core layer of a substrate are disclosed. The core layer comprises a molding compound encapsulating a die or a plurality of dies, a dielectric layer on the surfaces of the molding compound, and a conductive layer on top of the dielectric layer. A through hole is formed through the dielectric layer and the molding compound, which may be filled with a metal plate. A laser via is formed similarly. Build-up layers may be assembled next to the core layer to form the substrate, which can be used to package dies.

Abstract: Disclosed herein is a method for manufacturing a printed circuit board. According to a preferred embodiment of the present invention, there is provided a method for manufacturing a printed circuit board, including: preparing a base substrate; forming a carrier layer on the base substrate; forming a through via hole penetrating the carrier layer and the base substrate; forming a plating layer on the carrier layer and an inner wall of the through via hole; filling the through via hole with a conductive paste; removing a portion of the plating layer formed on the carrier layer; removing the carrier layer; and forming a circuit layer on the base substrate.