Abstract: A method includes forming a first electrically conductive layer on a first side of a dielectric insulation layer, forming a structured mask layer on a side of the first electrically conductive layer that faces away from the dielectric insulation layer, forming at least one trench in the first electrically conductive layer, said at least one trench extending through the entire first electrically conductive layer to the dielectric insulation layer, forming a coating which covers at least the bottom and the side walls of the at least one trench, and removing the mask layer after the coating has been formed.

Abstract: An alignment coating method for a substrate includes providing at least one substrate and at least one alignment plate, covering the alignment plate on to the substrate, coating polyimide liquid on the alignment plate, and transferring a polyimide liquid on the alignment plate to a region out of a blind via on the substrate according to a preset printing direction through a printing mechanism. Each of the substrates has the blind via. The alignment plate has at least one opening. The opening corresponds to the blind via.

Abstract: A method of printing solder paste in a component board and a stencil set for doing the same are disclosed. In one embodiment, the method includes using a first stencil having a first thickness to print solder paste into at least one through hole in the component board. The method further includes using a second stencil having a second thickness to print solder paste for at least one surface mounted part on the component board, subsequent to using the first stencil.

Abstract: In a Cu wiring structure forming method, a barrier film serving as a Cu diffusion barrier is formed at least on a surface of a recess in a first insulating film formed on a substrate, and the recess is filled with an Al-containing Cu film. A Cu wiring is formed from the Al-containing Cu film, and a cap layer including a Ru film is formed on the Cu wiring. Further, an interface layer containing a Ru—Al alloy is formed at an interface between the Cu wiring and the cap layer by heat generated in forming the cap layer or by a heat treatment performed after forming the cap layer. A second insulating film is formed on the cap layer.

Abstract: Among other things, self-assembled conductive networks are formed on a surface of substrate containing through holes. The conductive network having a pattern is formed such that at least some of the conductive material in the conductive network reaches into the holes and, sometimes, even the opposite surface of the substrate through the holes. The network on the surface of the substrate electrically connects to the conductive material in the holes with good conductance.

Abstract: A method is provided which includes forming a metal layer and converting at least a portion of the metal layer to a hydrated metal oxide layer. Another method is provided which includes selectively depositing a dielectric layer upon another dielectric layer and selectively depositing a metal layer adjacent to the dielectric layer. Consequently, a microelectronic topography is formed which includes a metal feature and an adjacent dielectric portion comprising lower and upper layers of hydrophilic and hydrophobic material, respectively. A topography including a metal feature having a single layer with at least four elements lining a lower surface and sidewalls of the metal feature is also provided herein. The fluid/s used to form such a single layer may be analyzed by test equipment configured to measure the concentration of all four elements. In some cases, the composition of the fluid/s may be adjusted based upon the analysis.

Abstract: A composition for forming transition vias and transition line conductors is disclosed for minimizing interface effects at electrical connections between dissimilar metal compositions. The composition has (a) inorganic components selected from the group consisting of (i) 20-45 wt % gold and 80-55 wt % silver and (ii) 100 wt % silver-gold solid solution alloys, and (b) an organic medium. The composition may also contain (c) 1-5 wt %, based upon the weight of the composition, of oxides or mixed oxides of metals selected from the group consisting of Cu, Co, Mg and Al and/or high viscosity glasses mainly containing refractory oxides. The composition may be used as a multi-layer composition in a via fill. Multi-layer circuits such as LTCC circuits and devices may also be formed using the composition for forming transition vias and transition line conductors.

Abstract: Provided are a substrate for a printed wiring board, and a printed wiring board, which are not limited in size because vacuum equipment is not necessary for the production, in which an organic adhesive is not used, and which can include a conductive layer (copper foil layer) having a sufficiently small thickness. Also provided are a method for producing the substrate for a printed wiring board, and a method for producing the printed wiring board. A substrate 1 for a printed wiring board includes an insulating base 11, a first conductive layer 12 that is stacked on the insulating base 11, and a second conductive layer 13 that is stacked on the first conductive layer 12, in which the first conductive layer 12 is a coating layer composed of a conductive ink containing metal particles, and the second conductive layer 13 is a plating layer.

Abstract: A method of forming a low-resistance, high-reliability through/embedded electrode is provided, where the electrode can be arranged in a higher density according to the miniaturization of the semiconductor manufacturing technology. This method includes the step of filling an opening 51 of a substrate 50 with a paste 56 of a first conductive material and drying the paste 56; the step of solid-phase sintering the paste 56 filled in the opening 51, generating a first porous conductor 57; the step of applying a paste of a second conductive material so as to cover the first conductor 57; and the step of melting the paste of the second conductive material by heat treatment, impregnating the second conductive material into the first conductor 57.

Abstract: A method is provided which includes forming a metal layer and converting at least a portion of the metal layer to a hydrated metal oxide layer. Another method is provided which includes selectively depositing a dielectric layer upon another dielectric layer and selectively depositing a metal layer adjacent to the dielectric layer. Consequently, a microelectronic topography is formed which includes a metal feature and an adjacent dielectric portion comprising lower and upper layers of hydrophilic and hydrophobic material, respectively. A topography including a metal feature having a single layer with at least four elements lining a lower surface and sidewalls of the metal feature is also provided herein. The fluid/s used to form such a single layer may be analyzed by test equipment configured to measure the concentration of all four elements. In some cases, the composition of the fluid/s may be adjusted based upon the analysis.

Abstract: A conductive paste comprising 88-94% by mass of Ag powder having an average particle size of 3 ?m or less and 0.1-3% by mass of Pd powder, the total amount of the Ag powder and the Pd powder being 88.1-95% by mass. A multilayer ceramic substrate obtained by laminating and sintering pluralities of ceramic green sheets, and having conductor patterns and via-conductors inside, the via-conductors being formed in via-holes having diameters of 150 ?m or less after sintering, containing Ag crystal particles having a particle size of 25 ?m or more, and having a porosity of 10% or less.

Abstract: A packaging substrate device includes: a first laminate including a first ceramic substrate and a first copper pattern disposed on an upper surface of the first ceramic substrate; and a second laminate disposed over the first copper pattern and including a second ceramic substrate, a second copper pattern that is disposed on an upper surface of the second ceramic substrate, and a through hole extending through the second ceramic substrate and the second copper pattern to expose a copper portion of the first copper pattern. A light emitting semiconductor die can be mounted on the copper portion within the through hole. Efficient heat dissipation can be achieved through the first laminate.

Abstract: Disclosed herein are a multilayer ceramic substrate and a method for manufacturing the same. In a method for manufacturing the multilayer ceramic substrate, which has a ceramic laminate including multiple ceramic layers and allowing interconnection between layers through vias respectively formed in the multiple ceramic layers, the method includes: preparing a ceramic laminate in which a void is formed around a via in at least one ceramic layer of multiple ceramic layers; immersing the ceramic laminate in a precipitating bath in which an electrode solution is contained; putting the ceramic laminate out of the precipitating bath after a predetermined period of time, and then removing a nanoparticle film stacked on a surface of a multilayer ceramic substrate; and applying heat to the multilayer ceramic substrate to form nanoparticles filling an inside of the void, after the removing of the nanoparticle film.

Abstract: The invention relates to a method of depositing a layer of material onto the surface of an object, of the type comprising the deposition of a layer of solution of said material in a first liquid followed by the evaporation of the first liquid to form the layer of material. According to the invention, the method comprises the formation of a layer of a second liquid interposed between the object and the layer of solution, the second liquid being immiscible with the first liquid, of density greater than that of the first liquid and with an evaporating temperature higher than that of the first liquid.

Abstract: In one embodiment, a protective coating for an electrode of a sensor is described, the protective coating comprising an annealed catalyst, said annealed catalyst comprising at least one metal that has been subjected to thermal energy that is at least equivalent to or greater than that received from calcining the at least one metal for 24 hours at a temperature of 930 degrees C in air. In another embodiment, the annealed catalyst will comprise at least one metal that has been subjected to thermal energy that is equal to or less than that received from calcining the at least one metal for 24 hours at 1030 degrees C in air. In one exemplary embodiment, the annealed catalyst will comprise at least one metal that has been subjected to thermal energy that is equal to that received from calcining the at least one metal for 24 hours at 980 degrees C in air.

Abstract: The present invention provides a method for modification of microchannels of a polydimethylsiloxane (PDMS) microchip, which includes the steps of: a) mixing an alkoxysilane precursor, an alkyl alkoxysilane precursor, and a solvent to prepare a sol-gel solution; b) oxidizing microchannels of the PDMS microchip; and c) coating the oxidized microchannels with the sol-gel solution prepared in step a). The PDMS microchip modified according to the method of the present invention shows higher hydrophilicity than an unmodified PDMS microchip. And, when the modified PDMS channels are filled with an organic solvent, channel swelling can be reduced, and thus various organic solvents can be used for the modified PDMS microchip compared to an unmodified PDMS microchip. Further, it can be widely applied for various fields because absorptivity of non-polar substances can be reduced.

Abstract: In a coating method, such as a droplet discharge method which requires baking, it is an object of the present invention to reduce the baking temperature at the time of forming a wiring and a conductive film. As a feature of the present invention, a composition, in which nanoparticles of a conductive material are dispersed in a solvent, is discharged using a droplet discharge method, and then dried to vaporize the solvent. Then, pretreatment using active oxygen is performed. After which, baking is then performed, whereby a wiring and a conductive film are formed. By performance of the pretreatment by active oxygen before the baking, a baking temperature at the time of forming the wiring and conductive film can be reduced.

Abstract: Novel materials with thermally reversible curing mechanisms are provided. These inventive compositions are useful in forming microelectronic structures, such as dual damascene structures. The compositions comprise a crosslinkable polymer dispersed or dissolved in a solvent system with a crosslinking agent. In use, the compositions are applied to a substrate and crosslinked. Additional layers may be applied on top of the cured layer followed by additional processing steps. Upon exposure to a temperature above the crosslinking temperature of the composition, the cured layer will undergo a decrosslinking reaction to render the layer soluble in common photoresist solvents, including solvents used to make the composition itself. Thus, after processing, the remaining material can be dissolved away without damaging the substrate. The inventive materials are especially suited for processes involving low-k dielectric substrates.

Abstract: A method for making a printed circuit board includes: (a) preparing a laminate having a ceramic substrate, first and second metal foils disposed on two opposite surfaces of the ceramic substrate, and a through hole extending through the ceramic substrate and the first and second metal foils; (b) filling the through hole with a metal paste such that the metal paste is in contact with the first and second metal foils; and (c) sintering the metal paste and the laminate such that the metal paste is connected electrically to the first and second metal foils. A printed circuit board made according to the method is also disclosed.

Abstract: A film formation method includes: ejecting liquid onto a substrate; and drying the liquid ejected onto the substrate by a drying device before an amount of a solvent evaporation of the liquid exceeds 40%.

Abstract: The instant invention is a process for planarizing a microelectronic substrate with a cross-linked polymer dielectric layer, comprising the steps of: (a) heating such a substrate coated with a layer comprising an uncured cross-linkable polymer and a glass transition suppression modifier to a temperature greater than the glass transition temperature of the layer, the temperature being less than the curing temperature of the uncured cross-linkable polymer to form a substrate coated with a heat flowed layer; and (b) heating the substrate coated with the heat flowed layer to a curing temperature of the uncured cross-linkable polymer of the heated layer to cure the uncured cross-linkable polymer to form a planarized substrate wherein the percent planarization at 100 micrometers is greater than fifty percent. The instant invention is a microelectronic device made using the above-described process.

Abstract: A method for manufacturing a field emission substrate is disclosed. The method includes the following steps: providing a substrate having a conductive layer; forming a hydrophobic layer on the conduction layer; patterning the hydrophobic layer; and removing the hydrophobic layer from the surface of the conductive layer so that the formed layer of electron-emitting materials can contact the surface of the conductive layer. The patterned hydrophobic layer can include plural bumps, and the pitches between the neighboring bumps are in a range of 1 ?m to 500 ?m. By way of the steps illustrated above, the emitting layer on the substrate can be made easily and arranged accurately. Hence, the electrons can be emitted homogeneously.

Abstract: Described are methods of making an electronic device, such as an RFID tag, including fabricating an antenna by depositing an electrically conductive polymer onto a substrate. The electrically conductive polymer is electrically connected to an electronic component, such as an IC chip or a diode. The electronic component may be placed on the substrate before or after the electrically conductive polymer is deposited. Once deposited, the electrically conductive polymer is cured. The electrically conductive polymer may be deposited in a number of ways, such using a mask having a desired pattern and applying the electrically conductive polymer to the mask, by screen printing the electrically conductive polymer or by printing the electrically conductive polymer using ink jet printing techniques.

Abstract: A process for filling or lining the pores of a porous silicon, silica or alumina substrate with a material which exhibits voltage-dependent index of refraction n is provided comprising providing precursors for the deposited material as a precursor solution, forming a fine mist of droplets of precursor solution and applying the droplets to the porous substrate. The invention provides for the first time porous silicon, silica and alumina substrates having a fill fraction of at least 60%. Fill fractions of close to l00% can be achieved. When provided with top and bottom electrodes, filled porous silicon, silica and alumina wafers can be used as voltage-dependent photonic devices. The same process can be used for lining trenches in the surface of a silicon substrate, for instance for use in production of microelectronic devices such as random access memories.

Abstract: The present invention relates to a ceramic electronic component wherein via conductors that are embedded in through holes of dielectric layers formed from a sintered body of ceramic particles are made by firing a electrically conductive paste for via conductor that contains inorganic particles made of the same material as the ceramic particles that constitute the dielectric layer and having an average particle diameter smaller than that of the ceramic particles, and a method for manufacturing the same. According to the present invention, such a ceramic electronic component can be provided that the via conductors and the internal electrodes are electrically connected with each other satisfactorily without voids generated therein.

Abstract: Disclosed herein are techniques for using diblock copolymer (DBCP) films as etch masks to form small dots or holes in integrated circuit layers. In an embodiment, the DBCP film is deposited on the circuit layer to be etched. Then the DCBP film is confined to define an area of interest in the DCBP film in which hexagonal domains will eventually be formed. Such confinement can constitute masking and exposing the DCBP film using photolithographic techniques. Such masking preferably incorporates knowledge of the domain spacing and/or grain size of the to-be-formed domains in the area of interest to ensure that a predictable number and/or orientation of the domains will result in the area of interest, although this is not strictly necessary in all useful embodiments. Domains are then formed in the area of interest in the DBCP film which comprises a hexagonal array of cylindrical domains in a matrix. The film is then treated (e.g.

Abstract: Organic photosensitive optoelectronic devices are disclosed. The devises are thin-film crystalline organic optoelectronic devices capable of generating a voltage when exposed to light, and prepared by a method including the steps of: depositing a first organic layer over a first electrode; depositing a second organic layer over the first organic layer; depositing a confining layer over the second organic layer to form a stack; annealing the stack; and finally depositing a second electrode over the second organic layer.

Abstract: A phase changeable memory element is formed by conformally forming a phase changeable material film in a contact hole on a substrate so as to create a void in the phase changeable material film in the contact hole. A capping film is formed on the phase changeable material film, and the void is at least partially closed by a thermal treatment that is sufficient to reflow the phase changeable material film in the void.

Abstract: It is an object of the present invention to alleviate unevenness due to an opening for making a contact with the lower layer even when the opening has a large diameter (1 ?m or more). Thus, it is a further object of the invention to reduce defects caused by the unevenness due to the contact hole. It is a feature of the invention to form a wiring by filling the contact hole with conductive fine particles. The conductive fine particles can be easily dispersed into a wiring material by using conductive fine particles having high wettability with the wiring material, thereby making a contact. Thus, planarization of a contact hole can be achieved without performing a reflow process. Further, more planarity can be obtained by performing a reflow process in addition, and the reliability is improved accordingly.

Abstract: An insulating material comprising a cycloolefin polymer, specifically, an interlayer insulating material for a high-density assembly board having interlayer-connecting via holes at most 200 ?m in diameter, comprising a cycloolefin polymer containing at least 50 mol % of a repeating unit derived from a cycloolefin monomer; a dry film formed from a curable resin composition comprising a polymer having a number average molecular weight within a range of 1,000 to 1,000,000 as measured by gel permeation chromatography, and a hardener; and a resin-attached metal foil obtained by forming a film of a cycloolefin polymer on one side of a metal foil. Laminates, multi-layer laminates and build-up multi-layer laminates making use of these materials, and production processes thereof.