With Pretreatment Of Substrate Patents (Class 427/98.5)
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Patent number: 11978618Abstract: A component of an ion optical device is manufactured. The component comprises aligned first and second electrode sets. A first material is machined to provide a part-machined first electrode set that comprises the first electrode set attached to a frame part of the first material. A second material is machined to provide a part-machined second electrode set that comprises the second electrode set attached to a frame part of the second material. The component of the ion optical device is assembled by aligning the part-machined first and second electrode sets. Subsequent to aligning the part-machined first and second electrode sets, the part-machined first electrode set is further machined to separate the first electrode set from the frame part of the first material and the part-machined second electrode set is further machined to separate the second electrode set from the frame part of the second material.Type: GrantFiled: December 20, 2021Date of Patent: May 7, 2024Assignee: Thermo Fisher Scientific (Bremen) GmbHInventor: Wilko Balschun
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Patent number: 11861441Abstract: A resilient flexible adhesive tape platform includes a flexible substrate, a flexible cover layer on the flexible substrate, a device layer in between the flexible substrate and the flexible cover layer comprising components connected to a resilient printed circuit board, and the resilient printed circuit board (PCB) in between the flexible substrate and the flexible cover layer. The flexible printed circuit board includes a resilient conductive trace on the PCB connecting two of the components, the resilient conductive trace comprising a plurality of sub-traces, each of the plurality of sub-traces electrically redundantly connecting the two electronic components to each other.Type: GrantFiled: December 21, 2021Date of Patent: January 2, 2024Inventors: Hendrik J. Volkerink, Ajay Khoche
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Patent number: 11705281Abstract: A multilayer ceramic capacitor includes: a multilayer chip in which dielectric layers mainly composed of ceramic and internal electrode layers are alternately stacked so that the internal electrode layers are alternately exposed to two end faces of the multilayer chip having a substantially rectangular parallelepiped shape; and a pair of external electrodes formed from the two end faces to at least one side face of side faces, wherein each external electrode includes a metal layer formed from the end face to the at least one side face and mainly composed of copper, and an oxide layer covering at least a part of the metal layer, mainly composed of copper oxide, and having a maximum thickness of 0.5 ?m or greater, wherein a first surface, which is in contact with the plated layer, of the oxide layer has Cu particles formed thereon.Type: GrantFiled: June 25, 2021Date of Patent: July 18, 2023Assignee: TAIYO YUDEN CO., LTD.Inventors: Tomoaki Nakamura, Mikio Tahara, Masako Kanou, Fusao Sato
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Patent number: 11577543Abstract: The present invention provide a multi-layered heat transfer sheet comprising a plurality of distinct pieces forming one or more consecutive patterns that form shapes or objects having discontinuous peripheries, as well as a method for producing and/or making said item. The method for forming the heat transfer decorations includes ablating one or more layers of a heat transfer sheet using a defocused laser to define at least one plurality of discrete pieces that together define a heat transfer decoration. A single pass of the defocused laser may ablate the one or more layers of the heat transfer sheet so as to define the discrete pieces.Type: GrantFiled: December 3, 2019Date of Patent: February 14, 2023Assignee: STAHLS' INC.Inventors: Fred Ciaramitaro, Brett Stahl
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Patent number: 11208725Abstract: A substrate processing apparatus includes a rotary table comprising a base plate having a front surface where at least one suction hole is provided and an attraction plate having a front surface contacted with a non-processing surface of a substrate to attract the substrate, a rear surface contacted with the front surface of the base plate, and at least one through hole through which the front surface and the rear surface are connected; a rotation driving device configured to rotate the rotary table around a rotation axis; and a suction device configured to act a suction force on the suction hole, to contact the base plate with the attraction plate by acting the suction force between the base plate and the attraction plate, and to firmly contact the attraction plate with the substrate by acting the suction force between the attraction plate and the substrate through the through hole.Type: GrantFiled: September 26, 2019Date of Patent: December 28, 2021Assignee: TOKYO ELECTRON LIMITEDInventors: Kouichi Mizunaga, Masami Akimoto, Satoshi Morita, Katsuhiro Morikawa
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Patent number: 11121034Abstract: There is provided a method of manufacturing a semiconductor device that is suitable for forming a one-step tapered groove even when a substrate material is a difficult-to-etch material. The method of manufacturing a semiconductor device includes a metal mask forming step, a dry etching step, and a metal mask removing step. The metal mask formation step forms a tapered metal mask having an opening on the back surface of the substrate. The opening exposes a part in the back surface, and an edge portion of the opening has a forward taper to the back surface. The dry etching step forms a tapered groove on the substrate by performing, from an upper side of the tapered metal mask, dry etching on the edge portion of the opening and the substrate exposed from the opening. The metal mask removing step removes the tapered metal mask.Type: GrantFiled: March 24, 2017Date of Patent: September 14, 2021Assignee: Mitsubishi Electric CorporationInventor: Daisuke Tsunami
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Patent number: 10150133Abstract: A bore masking system for effectively protecting the interior surface of a bore during all phases of the painting process. The bore masking system includes a tubular shield formed from a hydrophobic sheet to protect the interior surface of the bore during the various phases of the painting process including cleaning, painting and curing. The hydrophobic sheet repels liquids such as water, chemicals and paint to ensure the structural integrity of the tubular shield during the painting phases.Type: GrantFiled: February 12, 2014Date of Patent: December 11, 2018Assignee: Irenic Solutions, LLCInventor: Corey A. Johnson
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Patent number: 9458305Abstract: A method includes heating a sulfonated polyester resin in an organic-free solvent adding an aqueous solution of silver (I) ion to the heated resin to form a mixture and heating the mixture to effect the reduction of silver (I) ion to silver (0) in the absence of an external reducing agent. A composite includes a sulfonated polyester matrix and a plurality of silver nanoparticles dispersed within the matrix; the composite lacks trace residual byproducts from external reducing agents.Type: GrantFiled: November 3, 2014Date of Patent: October 4, 2016Assignee: XEROX CORPORATIONInventors: Valerie M. Farrugia, Alana Desouza, Sandra J. Gardner
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Patent number: 9364822Abstract: Catalysts include five-membered nitrogen containing heterocyclic compounds as ligands for metal ions which have catalytic activity. The catalysts are used to electrolessly plate metal on metal clad and un-clad substrates.Type: GrantFiled: June 28, 2013Date of Patent: June 14, 2016Inventors: Kristen M. Milum, Donald E. Cleary, Maria Anna Rzeznik
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Patent number: 9161444Abstract: A circuit board is provided with a metal wiring layer 12 on at least one principal surface of a ceramic sintered body 11, wherein the above-described metal wiring layer includes a first region 12a which is in contact with the principal surface and which contains a glass component and a second region 12b which is located on the first region 12a and which does not contain a glass component, the thickness of the first region 12a is 35% or more and 70% or less of the thickness of the metal wiring layer 12, and the average grain size in the first region 12a is smaller than the average grain size in the second region 12b.Type: GrantFiled: September 28, 2012Date of Patent: October 13, 2015Assignee: KYOCERA CORPORATIONInventors: Kiyotaka Nakamura, Yoshio Ohashi, Kunihide Shikata
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Publication number: 20150024119Abstract: A method and an arrangement are disclosed for transferring electrically conductive material in fluid form onto a substrate. Said substrate is preheated to a first temperature, and of said electrically conductive material there is produced fluid electrically conductive material. The fluid electrically conductive material is sprayed onto the preheated substrate to form a pattern of predetermined kind. The substrate onto which said fluid electrically conductive material was sprayed is cooled to a third temperature, which is lower than the melting point of said electrically conductive material.Type: ApplicationFiled: January 30, 2013Publication date: January 22, 2015Inventors: Juha Maijala, Petri Sirviö
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Publication number: 20150008014Abstract: A conductive film includes a transparent insulating substrate and a conductive mesh formed on the transparent insulating substrate, one of them is imprinted to form a meshed-like grooves on a surface thereof, it is simple and quick, having high efficiency; the grooves is printed and filled with metal slurry and sintered to form a conductive mesh, the cost is low; the distance between the lines of the conductive mesh is defined as d1, 100 ?m?d1<600 ?m, the square resistance of the conductive mesh is defined as R, 0.1?/sq?R<200?/sq. In order to reduce the distance between the line, the width of the mesh line is reduced, thereby improving the light transmission of the conductive film; the smaller the square resistance, the better the conductivity of the conductive film, the faster the transmission speed of the signal; the lower metal content ensure the small square resistance, saving raw materials.Type: ApplicationFiled: August 16, 2013Publication date: January 8, 2015Applicant: Nanchang O-Film Tech. Co., Ltd.Inventors: FEI ZHOU, SHENG ZHANG, YULONG GAO
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Patent number: 8927054Abstract: Provided are a conductive substrate which can be produced from inexpensive materials at a lower temperature than those for conventional substrates, and a process for producing the conductive substrate. The conductive substrate comprises a substrate (1) and a conductive pattern (5) provided on the substrate (1), wherein the conductive pattern (5), except on a surface and in a vicinity thereof on a side opposite to the substrate side, entirely has a structure comprising a binder (2) and fine aluminum grains (3) dispersed therein, and on the surface and in the vicinity a surface metal aluminum layer (4) is formed in which the fine aluminum grains (3) are spread with a roller to form a conductive junction connecting the fine aluminum grains to each other.Type: GrantFiled: November 18, 2010Date of Patent: January 6, 2015Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Manabu Yoshida, Toshihide Kamata
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Publication number: 20150000962Abstract: A capacitive transparent conductive film comprises: a transparent substrate, comprises a first surface and a second surface which is opposite to the first surface; a light-shield layer, formed at the edge of the first surface of the transparent substrate, the light-shield layer forms a non-visible region on the first surface of the transparent substrate; and a polymer layer, formed on the first surface of the transparent substrate, and covering the light-shield layer, the surface of the polymer layer is patterned to form a meshed trench, the trench is filled with conductive material to form a sensing region on the surface of the polymer layer. The capacitive transparent conductive film can effectively protect the conductive material and has low cost and good conductivity. A preparation method of the capacitive transparent conductive film is also provided.Type: ApplicationFiled: July 5, 2013Publication date: January 1, 2015Applicant: NANCHANG O-FILM TECH. CO., LTD.Inventors: Yulong Gao, Ying Gu, Yunhua Zhao, Guanglong Xie
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Publication number: 20150004375Abstract: A pixel circuit, driving method thereof, organic light-emitting display panel and display apparatus, comprise driving transistor, first storage capacitor, collecting unit, writing unit and light-emitting unit; the collecting unit is used for collecting the threshold voltage of the driving transistor and storing the threshold voltage into the first storage capacitor, under the control of the first scan signal; the writing unit is used for storing the data voltage inputted from the input terminal for the data voltage under the control of the second scan signal; and the light-emitting unit is used for emitting lights, driven by the data voltage and a voltage inputted from the input terminal for the controllable low voltage, under the control of the light-emitting control signal. Thus, the organic light-emitting device is not affected by the threshold voltage shift of the driving transistor, which may enhance the image uniformity of the organic light-emitting display panel effectively.Type: ApplicationFiled: December 9, 2013Publication date: January 1, 2015Inventors: Wenjun Hou, Ze Liu
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Patent number: 8911608Abstract: The present invention provides a circuit creation technology that improves conductive line manufacture by adding active and elemental palladium onto the surface of a substrate. The palladium is disposed in minute amounts on the surface and does not form a conductive layer by itself, but facilitates subsequent deposition of a metal onto the surface, according to the pattern of the palladium, to form the conductive lines.Type: GrantFiled: May 13, 2010Date of Patent: December 16, 2014Assignee: SRI InternationalInventors: Sunity Sharma, Jaspreet Singh Dhau
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Publication number: 20140321091Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for interconnect structures embedded in a package assembly including a bridge. In one embodiment, a package assembly may include a package substrate, a bridge embedded in the package substrate and including a bridge substrate, and an interconnect structure including a via extending through the package substrate into a surface of the bridge substrate and configured to interface with a conductive feature disposed on or beneath the surface of the bridge substrate. The interconnect structure may be configured to route electrical signals between the conductive feature and a die mounted on the package substrate. Other embodiments may be described and/or claimed.Type: ApplicationFiled: April 25, 2013Publication date: October 30, 2014Inventors: Chong Zhang, Stefanie M. Lotz, Islam A. Salama
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Publication number: 20140268534Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming an opening in a dielectric material of a package substrate, and then plating a conductive interconnect structure in the opening utilizing a plating process. The plating process may comprises a conductive metal and a dopant comprising between about 0.05 and 10 percent weight, wherein the dopant comprises at least one of magnesium, zirconium and zinc.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Inventors: Rajen S. Sidhu, Mukul P. Renavikar, Sandeep B. Sane
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Patent number: 8815333Abstract: Disclosed is a manufacturing method of metal structure in multi-layer substrate. The manufacturing method includes following steps: coating at least one photoresist layer on a surface of a dielectric layer; exposing the photoresist dielectric layer to define a predetermined position of the metal structure; removing the photoresist layer at the predetermined position to undercut an edge of the photoresist layer adjacent to the predetermined position by a horizontal distance of at least 0.1 ?m between a top and a bottom of the edge; forming the metal structure at the predetermined position; and forming at least one top-cover metal layer to cover a top surface and two side surfaces of the metal structure. The present invention can form a cover metal layer covering the top surface and the two side surfaces by one single photomask.Type: GrantFiled: April 16, 2012Date of Patent: August 26, 2014Assignee: Princo Middle East FZEInventor: Chih-kuang Yang
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Patent number: 8802183Abstract: The system of the present invention includes a conductive element, an electronic component, and a partial power source in the form of dissimilar materials. Upon contact with a conducting fluid, a voltage potential is created and the power source is completed, which activates the system. The electronic component controls the conductance between the dissimilar materials to produce a unique current signature. The system can also measure the conditions of the environment surrounding the system.Type: GrantFiled: July 11, 2011Date of Patent: August 12, 2014Assignee: Proteus Digital Health, Inc.Inventors: Jeremy Frank, Peter Bjeletich, Hooman Hafezi, Robert Azevedo, Robert Duck, Iliya Pesic, Benedict Costello, Eric Snyder
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Patent number: 8753748Abstract: The purpose of the present invention is to provide a wiring substrate from which a metal film cannot be detached easily. A process for forming a metal film comprises a step (X) of applying an agent containing a compound (?) onto the surface of a base and a step (Y) of forming a metal film on the surface of the compound (?) by a wet-mode plating technique, wherein the compound (?) is a compound having either an OH group or an OH-generating group, an azide group and a triazine ring per molecule, and the base comprises a polymer.Type: GrantFiled: September 30, 2011Date of Patent: June 17, 2014Assignees: Sulfur Chemical Laboratory Incorporated, Meiko Electronics Co., Ltd.Inventors: Kunio Mori, Yusuke Matsuno, Katsuhito Mori, Takahiro Kudo, Shigeru Michiwaki, Manabu Miyawaki
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Publication number: 20140144684Abstract: The present invention relates to a conductive pattern including a layer (A) including a substrate, an absorbing layer (B), and a conductive layer (C). The absorbing layer (B) is formed by applying conductive ink containing a conductive substance (c) that constitutes the conductive layer (C) to a surface of a resin layer (B1) including a vinyl resin (b1) produced by polymerizing a monomer mixture containing 10% by mass to 70% by mass of methyl (meth)acrylate; and subsequently forming crosslinks in the resin layer (B1).Type: ApplicationFiled: June 22, 2012Publication date: May 29, 2014Applicant: DIC CORPORATIONInventors: Yukie Saitou, Wataru Fujikawa, Jun Shirakami
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Publication number: 20140099432Abstract: A fabrication method for a flexible circuit board is provided. The fabrication method includes the following steps. Firstly, a release film having an upper surface and a lower surface opposite to each other is provided. Next, two flexible substrates are respectively disposed on the upper surface and the lower surface. Next, a plurality of nano-scale micro-pores are formed on each flexible substrate to form two non-smooth flexible substrates. The nano-scale micro-pores evenly distributed over an outer surface of each non-smooth flexible substrate. Each non-smooth flexible substrate being adapted to be performed a plating process directly on the outer surface thereof.Type: ApplicationFiled: December 27, 2012Publication date: April 10, 2014Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: Tzyy-Jang Tseng, Chang-Ming Lee, Wen-Fang Liu, Cheng-Po Yu
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Publication number: 20140087063Abstract: The present invention provides a method for preparing an ion optical device. A substrate is fabricated with a hard material adapted for a grinding process, the substrate at least including a planar surface, and including at least one insulating material layer. Next, one or more linear grooves are cut on the planar surface, to form multiple discrete ion optical electrode regions on the planar surface separated by the linear grooves. Then, conductive leads are fabricated on other substrate surfaces than the planar surface and in a through hole inside the substrate, to provide voltages required on ion optical electrodes. By using high-hardness materials in cooperation with high-precision machining, higher precision and a desired discrete electrode contour can be obtained.Type: ApplicationFiled: December 2, 2013Publication date: March 27, 2014Applicant: SHIMADZU RESEARCH LABORATORY (SHANGHAI) CO. LTD.Inventors: Hui Mu, Gongyu Jiang, Li Ding, Jianliang Li, Wenjian Sun
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Patent number: 8575021Abstract: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.Type: GrantFiled: March 14, 2013Date of Patent: November 5, 2013Assignee: Intermolecular, Inc.Inventors: Thomas R. Boussie, Tony P. Chiang, Anh Duong, Zachary Fresco, Nitin Kumar, Chi-I Lang, Sandra G. Malhotra, Jinhong Tong
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Publication number: 20130271175Abstract: A probe card assembly and associated processes of forming them may include a wiring substrate with a first surface and an opposite surface, an electrically conductive first via comprising electrically conductive material extending into the wiring substrate from the opposite surface and ending before reaching the first surface, and a plurality of electrically conductive second vias, and a custom electrically conductive terminal disposed on the first surface such that said custom terminal covers the first via and contacts one of the second vias adjacent to said first via without electrically contacting the first via. Each of the second vias may be electrically conductive from the first surface to the opposite surface. The first via may include electrically insulating material disposed within a hole in the first via.Type: ApplicationFiled: April 3, 2013Publication date: October 17, 2013Applicant: FormFactor, Inc.Inventor: Shawn Powell
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Patent number: 8551560Abstract: Methods for improving selective deposition of a capping layer on a patterned substrate are presented, the method including: receiving the patterned substrate, the patterned substrate including a conductive region and a dielectric region; forming a molecular masking layer (MML) on the dielectric region; preparing an electroless (ELESS) plating bath, where the ELESS plating bath includes: a cobalt (Co) ion source: a complexing agent: a buffer: a tungsten (W) ion source: and a reducing agent; and reacting the patterned substrate with the ELESS plating bath for an ELESS period at an ELESS temperature and an ELESS pH so that the capping layer is selectively formed on the conductive region. In some embodiments, methods further include a pH adjuster for adjusting the ELESS pH to a range of approximately 9.0 pH to 9.2 pH. In some embodiments, the pH adjuster is tetramethylammonium hydroxide (TMAH). In some embodiments, the MML is hydrophilic.Type: GrantFiled: May 22, 2009Date of Patent: October 8, 2013Assignee: Intermolecular, Inc.Inventors: Jinhong Tong, Zhi-Wen Sun, Chi-I Lang, Nitin Kumar, Bob Kong, Zachary Fresco
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Publication number: 20130240366Abstract: Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations.Type: ApplicationFiled: March 15, 2013Publication date: September 19, 2013Applicant: AVX CORPORATIONInventors: Andrew P. Ritter, Robert Heistand, II, John L. Galvagni, Sriram Dattaguru
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Publication number: 20130183534Abstract: The purpose of the present invention is to provide a wiring substrate from which a metal film cannot be detached easily. A process for forming a metal film comprises a step (X) of applying an agent containing a compound (?) onto the surface of a base and a step (Y) of forming a metal film on the surface of the compound (?) by a wet-mode plating technique, wherein the compound (?) is a compound having either an OH group or an OH-generating group, an azide group and a triazine ring per molecule, and the base comprises a polymer.Type: ApplicationFiled: September 30, 2011Publication date: July 18, 2013Applicants: Kunio Mori, Meiko Electronics Co., Ltd., Sulfur Chemical Institute IncorporatedInventors: Kunio Mori, Yusuke Matsuno, Takahiro Kudo, Shigeru Michiwaki, Manabu Miyawaki
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Patent number: 8475666Abstract: A toughening agent composition for increasing the hydrophobicity of an organosilicate glass dielectric film when applied to said film. It includes a component capable of alkylating or arylating silanol moieties of the organosilicate glass dielectric film via silylation, and an activating agent selected from the group consisting of an amine, an onium compound and an alkali metal hydroxide.Type: GrantFiled: September 15, 2004Date of Patent: July 2, 2013Assignee: Honeywell International Inc.Inventors: Teresa A. Ramos, Robert R. Roth, Anil S. Bhanap, Paul G. Apen, Denis H. Endisch, Brian J. Daniels, Ananth Naman, Nancy Iwamoto, Roger Y. Leung
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Publication number: 20130146332Abstract: A method for forming a conductive pattern on a substrate surface comprises altering the surface energy of the substrate surface, depositing a catalyst-doped liquid on to said substrate surface; forming a seed layer from said deposited catalyst-doped liquid, and plating the seed layer thereby forming the conductive pattern. In some embodiments, 3-D structures are placed on the substrate to delimit the size and shape of the conductive pattern. In other embodiments, the surface energy of the areas of the substrate in which conductive material is not desired (i.e., inverse pattern) is altered (e.g., lowered) to avoid having conductive liquid adhere thereto.Type: ApplicationFiled: October 29, 2010Publication date: June 13, 2013Applicant: UNIPIXEL DISPLAYS ,INC.Inventors: Ed S. Ramakrishnan, Robert J. Petcavich
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Publication number: 20130140063Abstract: A method for making printed circuits and printed circuit boards which includes coating a non-metallized substrate and plating an image of a desired circuit design directly onto the coated substrate without the need to image the circuit design on an intermediate silver halide polyester film or diazo and utilizing existing imaging, developing and etching subtractive techniques in conventional printed circuit board processing. One exemplary embodiment of the method for making printed circuit boards includes coating a non-metallized substrate with a palladium based material including a ferric based solution combined with palladium.Type: ApplicationFiled: November 19, 2012Publication date: June 6, 2013Inventor: Steven Lee Dutton
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Publication number: 20130105211Abstract: A low cost and high performance method for bonding a wafer to an interposer is provided. The technology provides designs and metallization techniques for through via glass applications that is thermal coefficient expansion matched to the glass or synthetic fused quartz substrates. An off-the-shelf glass, such as borosilicate based or Fused Synthetic Quartz, is used with a thick film Cu or Ag and/or a Sodium Ion Enriched (SIE) coating or glass, which may be applied or fired onto the substrate or wafer. Polymer based coatings can be applied in a sequential build-up process for purposes of redistribution of signals from a silicon integrated circuit to the opposite side of the substrate or wafer. Additionally, metallizations can be applied on top of the polymers and patterned to create a multilayer circuit.Type: ApplicationFiled: November 1, 2012Publication date: May 2, 2013Inventor: Tim Mobley
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Patent number: 8404124Abstract: Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.Type: GrantFiled: June 12, 2007Date of Patent: March 26, 2013Assignee: Micron Technology, Inc.Inventors: Dan B. Millward, Donald Westmoreland, Gurtej Sandhu
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Publication number: 20130068511Abstract: A method for printing an electrical conductor on a substrate has been developed. In the method, a reverse image of the electrical conductor pattern is printed on a substrate with an electrically non-conductive material to form a second pattern that exposes a portion of the surface area of the substrate. The entire surface area of the substrate is then covered with an electrically conductive material. The non-conductive material of the reverse image electrically isolates the electrically conductive material covering the reverse image from the electrically conductive material covering the second pattern.Type: ApplicationFiled: September 19, 2011Publication date: March 21, 2013Applicant: XEROX CORPORATIONInventor: Yiliang Wu
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Publication number: 20130068723Abstract: A method of producing substrates having a patterned mask layer with fine features such as repeating stripes. The method including the steps of forming a substrate having a transfer layer with a predetermined pattern on a first major surface of the substrate; providing the substrate having the transfer layer on the first major surface; providing a structured tool having a body and a plurality of contact portions, the contact portions having a Young's Modulus between about 0.5 Gpa to about 30 Gpa; heating either the structured tool or the substrate; contacting the transfer layer with the structured tool; cooling the transfer layer; and withdrawing the structured tool from the transfer layer such that portions of the transfer layer separate with the structured tool leaving openings in the transfer layer that extend all the way through the transfer layer to the substrate forming the transfer layer with the predetermined pattern.Type: ApplicationFiled: December 20, 2010Publication date: March 21, 2013Inventors: Matthew S. Stay, Mikhail L. Pekurovsky
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Patent number: 8323739Abstract: A method for forming a metal pattern on a substrate via printing and electroless plating is disclosed, which includes printing a pattern on the substrate with an ink composition, drying the printed pattern, and contacting the dried pattern with an electroless plating solution. The ink composition either contains components (i), (ii) and (iii), components (i) and (iv), or components (i) and (v), which are dissolved or dispersed in a solvent, wherein (i) is a binder; (ii) is a sulfate terminated polymer of an ethylenically unsaturated monomer; (iii) is a catalytic metal precursor; (iv) is a polymer of an ethylenically unsaturated monomer deposited with particles of catalytic metal; and (v) is a copolymer of an ethylenically unsaturated monomer and a hydrophilic monomer deposited with particles of catalytic metal. The binder (i) is a water swellable resin. The catalytic metal may be Au, Ag, Pd, Pt or Ru.Type: GrantFiled: November 8, 2007Date of Patent: December 4, 2012Assignee: National Defense UniversityInventors: Yuh Sung, Ming-Der Ger, Chang-Ping Chang, Chun-Chieh Tseng, Wen-Ding Chen
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Patent number: 8318254Abstract: A copolymer deposited with particles of catalytic metal is disclosed in the present invention, which is formed from an ethylenically unsaturated monomer and a hydrophilic monomer, and the catalytic metal is Au, Ag, Pd, Pt or Ru. The copolymer is hydrophilic when the temperature is lower than a specific temperature, and will become hydrophobic when the temperature is greater than the specific temperature. The present invention also discloses a method for forming a metal layer on a substrate via electroless plating, which includes contacting the substrate with an ink composition, drying the ink composition on the substrate, and contacting the dried ink composition with an electroless plating solution, wherein the ink composition contains the copolymer of the present invention in an aqueous phase. The present invention further discloses a method for forming metal conductors in through holes of a substrate.Type: GrantFiled: October 30, 2008Date of Patent: November 27, 2012Assignee: National Defense UniversityInventors: Yuh Sung, Ming-Der Ger, Chang-Ping Chang, Chun-Chieh Tseng, Wen-Ding Chen
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Publication number: 20120261172Abstract: A structure and manufacturing method of transparent conductive circuits, comprises a base material, ink layer provided with absorbing polymer liquid characteristics and a conductive layer composed of a conductive polymer coating. The ink layer is attached to the areas on the surface of the base material not requiring electrical conductivity, and heat energy or radiation is used to accelerate drying and hardening of the ink layer. The conductive layer with an area larger than that of the ink layer is attached to and contacts the ink layer, thereby enabling the ink layer attached to the surface of the base material to increase electrical resistivity of conductive layer in contact therewith. The areas relative to the conductive layer on the surface of the base material not in contact with the ink layer are provided with electrical conductivity. Accordingly, the required conductive circuits or patterns are formed on the base material.Type: ApplicationFiled: August 19, 2011Publication date: October 18, 2012Inventor: Yung-Shu YANG
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Publication number: 20120255771Abstract: A packaging substrate includes a core board having a first surface and an opposite second surface; at least a conic through hole formed in the core board and penetrating the first and second surfaces; a plurality of conductive paths formed on a wall of the conic through hole, free from being electrically connected to one another in the conic through hole; and a plurality of first circuits and second circuits disposed on the first and second surfaces of the core board, respectively, and being in contact with peripheries of two ends of the conic through hole, wherein each of the first circuits is electrically connected through each of the conductive paths to each of the second circuits. Compared to the prior art, the packaging substrate has a reduced number of through holes or vias and an increased overall layout density.Type: ApplicationFiled: April 6, 2012Publication date: October 11, 2012Applicant: UNIMICRON TECHNOLOGY CORPORATIONInventors: Wen-Hung Hu, Chao-Meng Cheng, Yu-Hsiang Huang, Ya-Ping Chiou
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Patent number: 8277901Abstract: In the condition where a nozzle for applying a coating liquid is disposed on the lower side of a substrate and a substrate surface controlled in wettability is faced down, the nozzle and the substrate are moved relative to each other, whereby the coating liquid is applied to a desired region of the substrate, and then the coating liquid is dried, to obtain a pattern included a dried coating layer.Type: GrantFiled: February 25, 2008Date of Patent: October 2, 2012Assignee: Sony CorporationInventor: Akihiro Nomoto
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Publication number: 20120231179Abstract: An embedded wiring board includes an upper wiring layer, a lower wiring layer, an insulation layer, a first conductive pillar and a second conductive pillar. The upper wiring layer contains an upper pad, the lower wiring layer contains a lower pad, and the insulation layer contains an upper surface and a lower surface opposite to the upper surface. The upper pad is embedded in the upper surface and the lower pad is embedded in the lower surface. The first conductive pillar is located in the insulation layer and includes an end surface which is exposed by the upper surface. A height of the first conductive pillar relative to the upper surface is larger than a depth of the upper pad relative to the upper surface. In addition, the second conductive pillar is located in the insulation layer and is connected between the first conductive pillar and the lower pad.Type: ApplicationFiled: May 18, 2012Publication date: September 13, 2012Applicant: UNIMICRON TECHNOLOGY CORP.Inventor: Cheng-Po Yu
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Publication number: 20120231154Abstract: A method for fabricating a ceramic device is provided. A green sheet is adhered on an adhesive film. A photoresist film is then formed on the green sheet. A photolithographic process is carried out to form circuit trenches in the photoresist film. The circuit trenches are filled with metal paste, thereby forming a circuit pattern. The photoresist film is then removed.Type: ApplicationFiled: January 19, 2012Publication date: September 13, 2012Inventors: Wen-Hsiung Liao, Wen-Yu Lin, Wei-Chien Chang
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Publication number: 20120195016Abstract: Since lead-tin solder was outlawed, electronic circuits constructed with lead-free tin solders have been plagued growth of whiskers of tin emanating from the tin soldered and/or tin coated surfaces. Such whiskers often short out the electronic circuits when present. The growth of tin whiskers in such electronic circuits (i.e., those fully or partially populated with components is addressed here by depositing a tin-whisker-impenetrable metal cap on all exposed tin coated surfaces in the circuit. In the process, metal surfaces where no cap is desired are masked, where after all exposed metal surfaces are cleaned, followed by immersing the entire circuit in an electroless bath, e.g., a nickel electroless bath, for a time sufficient to form a metal cap on all exposed metal surfaces, removing the circuit from the bath, rinsing and de-masking covered surfaces.Type: ApplicationFiled: August 5, 2011Publication date: August 2, 2012Inventors: Robert J. Landman, J. Gordon Davy, Dennis Fritz
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Patent number: 8231766Abstract: A novel board for printed wiring comprising a fine conductor wiring having a clear and favorable boundary line and fabricated by an ordinal printing method such as screen printing, a printed wiring board using the same, and methods for manufacturing them. A board for printed wiring and a method for manufacturing the same are characterized in that the surface of a board is subjected to one of the surface treatments: (a) roughening, (2) plasma treatment, (3) roughening and then plasma treatment, and (4) roughening and then forming of a metal film coating by sputtering. A printed wiring board and a method for manufacturing the same is characterize in that a conductor wiring is fabricated by printing using a conductive paste containing metal particles the average particle diameter of which is 4 ?m or less and the maximum particle diameter of which is 15 ?m or less.Type: GrantFiled: October 25, 2007Date of Patent: July 31, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Noriki Hayashi, Yoshio Oka, Masahiko Kanda, Narito Yagi, Kenji Miyazaki, Kyouichirou Nakatsugi
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Publication number: 20120171362Abstract: Disclosed are a non-fluorine and non-silicon hydrocarbon-based adhesive composition for substrate surface treatment for inkjet printing, a substrate surface-treated by the composition, and a method for modifying the surface of the substrate by using the composition so as to form fine lines by means of inkjet nano ink. The disclosed composition includes only an epoxy resin, or includes an epoxy resin and an acrylic compound, so as to hydrophobically modify the substrate. The composition can achieve better properties such as an increase in an ink contact angle, an ink spreadability inhibiting effect, and a wiring adhesive strength, as compared to a conventional silicon-based and/or fluorinated adhesive. Furthermore, since a conventional silicon-based and fluorinated adhesive component is not used, it is possible to perform substrate surface treatment in terms of environmental safety, thereby improving the productivity and the economic efficiency.Type: ApplicationFiled: December 14, 2009Publication date: July 5, 2012Applicant: DOOSAN CORPORATIONInventors: Young Hoon Kim, Min Su Lee, Yong Wook Kim
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Patent number: 8202567Abstract: To improve the transmission properties of antennae manufactured with known methods, more specifically antennae for application in the UHF range, a method is proposed of producing pattern-forming metal structures on a carrier substrate. The method comprises the following method steps: providing the carrier substrate, forming the pattern on the carrier substrate with a composite material containing dispersed metal, bringing the carrier substrate into contact with halide ions, and thereafter depositing a metal layer onto the pattern formed by the composite material, producing thereby metal structures.Type: GrantFiled: August 4, 2006Date of Patent: June 19, 2012Assignee: Atotech Deutschland GmbHInventors: Franz Kohnle, Michael Guggemos, Matthias Dammasch, Wolfgang Ptak
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Patent number: 8187664Abstract: The invention provides a method of forming a metallic pattern including: (a) forming, in a pattern form on a substrate, a polymer layer which contains a polymer that has a functional group that interacts with an electroless plating catalyst or a precursor thereof; (b) imparting the electroless plating catalyst or precursor thereof onto the polymer layer; and (c) forming a metallic film in the pattern form by subjecting the substrate having the polymer layer to electroless plating using an electroless plating solution, wherein the substrate is treated using a solution comprising a surface charge modifier or 1×10?10 to 1×10?4 mmol/l of a plating catalyst poison before or during the (c) forming of the metallic film. The invention further provides a metallic pattern obtained thereby. Furthermore, the invention provides a printed wiring board and a TFT wiring board, each of which uses the metallic pattern as a conductive layer.Type: GrantFiled: February 8, 2006Date of Patent: May 29, 2012Assignee: FUJIFILM CorporationInventors: Kazuhiko Matsumoto, Koichi Kawamura, Takeyoshi Kano
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Publication number: 20120121800Abstract: A method may include providing a surface modification inkjet head and a target inkjet head to be movable on a substrate, and forming a surface modification printed pattern by moving the surface modification inkjet head and ejecting surface modification ink onto the substrate. A target printed pattern may be formed by ejecting a target ink from the target inkjet head to the surface modification printed pattern and a metal wiring pattern may be formed on the substrate by removing the surface modification printed pattern.Type: ApplicationFiled: April 26, 2011Publication date: May 17, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joong-hyuk Kim, Jae-woo Chung, Young-ki Hong
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Patent number: 8178156Abstract: A surface treatment process for a circuit board is provided. The circuit board includes a substrate, a first circuit layer disposed on an upper surface of the substrate, and a second circuit layer disposed on a lower surface of the substrate. The first circuit layer is electrically connected to the second circuit layer. In the surface treatment process for the circuit board, a first oxidation protection layer and a second oxidation protection layer are respectively formed on a portion of the first circuit layer and a portion of the second circuit layer by immersion. Afterwards, the first circuit layer exposed by the first oxidation protection layer is subjected to black oxidation to form a black oxide layer. The thickness of the first oxidation protection layer is thinner than or equal to the thickness of the black oxide layer.Type: GrantFiled: January 12, 2009Date of Patent: May 15, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Chien-Hao Wang