Manufacture Of Electrical Device Controlled Printhead Patents (Class 438/21)
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Patent number: 12052907Abstract: Provided is a mask, including: a plurality of mask pattern regions, a transition region disposed between the plurality of mask pattern regions, and a mask marginal region surrounding the plurality of mask pattern regions and the transition region; wherein the transition region includes at least one first half-etched sub-region with a thickness less than a thickness of the mask marginal region.Type: GrantFiled: September 11, 2020Date of Patent: July 30, 2024Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Peng Xu, Fengli Ji
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Patent number: 12029232Abstract: The present invention relates to an apparatus for drying food products, for example fruit or eggs, comprising; •—a tunnel section as dryer compartment (10) with supply unit and discharge unit for dryer gas, with the dryer gas being blown on the products substantially from above, and •—a roller conveyor (1) with at least one row of supply rollers (3) for thereon conveying wet products in a conveying direction T to, through, and away from the dryer compartment (10), wherein the dryer compartment (10) comprises for the row a corresponding at least one ceiling element (14) with a curvature in line with that of the product, while in the ceiling element (14) at least one slit (15) is provided, directed substantially transversely to the conveying direction T, for blowing in the dryer gas.Type: GrantFiled: June 5, 2019Date of Patent: July 9, 2024Assignee: Moba Group B.V.Inventors: Willem Frans Neels, Willem Henri Hanekamp, Johannes Michiel Maria Bekelaar
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Patent number: 11894395Abstract: A display device includes a substrate including a display area and a non-display area driving circuits disposed in the non-display area; first voltage wirings and second voltage wirings extending from the display area to the non-display area; and a first auxiliary wiring electrically connected to the first voltage wirings and a second auxiliary wiring electrically connected to the second voltage wirings, the first auxiliary wiring and the second auxiliary wiring being electrically connected to the driving circuit, wherein the first voltage wirings electrically connected to an odd-numbered driving circuit among the driving circuits are electrically connected to the first auxiliary wiring through a first connection wiring, and the second voltage wirings electrically connected to an even-numbered driving circuit among the driving circuits are electrically connected to the second auxiliary wiring through a second connection wiring.Type: GrantFiled: December 1, 2021Date of Patent: February 6, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventor: Yeon Kyung Kim
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Patent number: 11652331Abstract: A method for producing a housing cover for a laser component, a housing for a laser component, and a laser component are provided. The method includes providing an at least partially radiation-permeable window including an aluminum oxide, provide a copper carrier for the window, and forming a copper oxide in an oxide region on the copper carrier. The method further includes arranging the window at the oxide region, forming a eutectic bond between the window and the copper oxide in the oxide region, and thereby fixing the window to the copper carrier.Type: GrantFiled: January 16, 2019Date of Patent: May 16, 2023Inventor: Matthias Knörr
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Patent number: 11646395Abstract: A method of growing an AlGaN semiconductor material utilizes an excess of Ga above the stoichiometric amount typically used. The excess Ga results in the formation of band structure potential fluctuations that improve the efficiency of radiative recombination and increase light generation of optoelectronic devices, in particular ultraviolet light emitting diodes, made using the method. Several improvements in UV LED design and performance are also provided for use together with the excess Ga growth method. Devices made with the method can be used for water purification, surface sterilization, communications, and data storage and retrieval.Type: GrantFiled: December 20, 2019Date of Patent: May 9, 2023Assignee: Trustees of Boston UniversityInventors: Yitao Liao, Theodore D. Moustakas
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Patent number: 11644437Abstract: There is provided a nanopore sensor including cis and trans fluidic reservoirs. A nanopore is provided in a support structure separating the cis and trans reservoirs. The nanopore has an inlet in fluidic connection with the cis fluidic reservoir and an outlet in fluidic connection with the trans fluidic reservoir. The cis fluidic reservoir has a fluidic access resistance, RC, the trans fluidic reservoir has a fluidic access resistance, RT, and the nanopore has a fluidic resistance, RP. RP is of the same order of magnitude as RT and both RP and RT are at least an order of magnitude greater than RC. An electrical transduction element is disposed at a nanopore sensor site that exposes the transduction element to the trans reservoir. An electrical circuit is connected to the electrical transduction element for producing an electrical signal indicative of changes in electrical potential local to the trans reservoir.Type: GrantFiled: June 14, 2021Date of Patent: May 9, 2023Assignee: President and Fellows of Harvard CollegeInventors: Ping Xie, Charles M. Lieber
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Patent number: 11465401Abstract: An ejector device that includes one or more ejectors comprises an ejector layer that spans at least one hollow area. The ejector layer has a first surface and an opposing second surface arranged to receive a viscous material with viscosity between 20 and 50,000 centipoise. The ejector layer includes a radiation absorber material configured to thermally expand without phase transition in response to heating by activation radiation transmitted to the first surface. Thermal expansion of the ejector layer causes displacement of the ejector layer and ejection of the material from the second surface of the ejector layer.Type: GrantFiled: April 19, 2021Date of Patent: October 11, 2022Assignee: Palo Alto Research Center IncoporatedInventors: David K. Biegelsen, Timothy D. Stowe, Mandana Veiseh
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Patent number: 11402672Abstract: A method that includes: providing a substrate including a layer of a crystalline material having a first surface; and exposing the first surface to an environment under conditions sufficient to cause epitaxial growth of a layer of a deposition material on the first surface, wherein exposing the first surface to the environment includes illuminating the substrate with light at a first wavelength while causing the epitaxial growth of the layer of the deposition material. The first surface includes one or more discrete growth sites at which an epitaxial growth rate of the quantum confined nanostructure material is larger than areas of the first surface away from the growth sites by an amount sufficient so that the deposition material forms a quantum confined nanostructure at each of the one or more discrete growth sites.Type: GrantFiled: May 3, 2018Date of Patent: August 2, 2022Assignee: X Development LLCInventors: Michael Jason Grundmann, Martin Friedrich Schubert
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Patent number: 11355383Abstract: A process for handling MEMS wafers includes the steps of: (i) attaching a first carrier substrate to a first side of a MEMS wafer, the first carrier substrate being attached via a first wafer bonding tape and a silicone-free peel tape, the peel tape contacting the first side of the MEMS wafer; (ii) performing wafer processing steps on an opposite second side of the MEMS wafer; (iii) releasing the first carrier substrate from the first side of the MEMS wafer via exposure to an energy source, the energy source selectively releasing the wafer bonding tape from the first side of the MEMS wafer; and (iv) peeling the peel tape away from the first side of the MEMS wafer.Type: GrantFiled: June 1, 2020Date of Patent: June 7, 2022Inventors: Nicolas Arnal, Troy Pasiola Quimpo, Angus North
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Patent number: 11339470Abstract: The present disclosure provides methods for forming diamond nanostructures and diamonds from amorphous carbon nanostructures in ambient temperature and pressure by irradiating carbon nanostructures to an undercooled state and quenching the melted carbon to convert a portion of the nanostructure into diamond.Type: GrantFiled: November 8, 2019Date of Patent: May 24, 2022Assignee: North Carolina State UniversityInventor: Jagdish Narayan
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Patent number: 10998352Abstract: In a micro-device integration process, a donor substrate is provided on which to conduct the initial manufacturing and pixelation steps to define the micro devices, including functional, e.g. light emitting layers, sandwiched between top and bottom conductive layers. The microdevices are then transferred to a system substrate for finalizing and electronic control integration. The transfer may be facilitated by various means, including providing a continuous light emitting functional layer, breakable anchors on the donor substrates, temporary intermediate substrates enabling a thermal transfer technique, or temporary intermediate substrates with a breakable substrate bonding layer.Type: GrantFiled: August 15, 2019Date of Patent: May 4, 2021Assignee: VueReal Inc.Inventors: Gholamreza Chaji, Ehsanollah Fathi
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Patent number: 10811324Abstract: An ink jet process is used to deposit a material layer to a desired thickness. Layout data is converted to per-cell grayscale values, each representing ink volume to be locally delivered. The grayscale values are used to generate a halftone pattern to deliver variable ink volume (and thickness) to the substrate. The halftoning provides for a relatively continuous layer (e.g., without unintended gaps or holes) while providing for variable volume and, thus, contributes to variable ink/material buildup to achieve desired thickness. The ink is jetted as liquid or aerosol that suspends material used to form the material layer, for example, an organic material used to form an encapsulation layer for a flat panel device. The deposited layer is then cured or otherwise finished to complete the process.Type: GrantFiled: November 2, 2017Date of Patent: October 20, 2020Assignee: Kateeva, Inc.Inventors: Eliyahu Vronsky, Nahid Harjee
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Patent number: 10573684Abstract: A process for producing a light emitting diode device, the process including: forming a plurality of quantum dots on a surface of a layer including a first area and a second area, the forming including: exposing the first area of the surface to light having a first wavelength while exposing the first area to a quantum dot forming environment that causes the quantum dots in the first area to form at a first growth rate while the quantum dots have a dimension less than a first threshold dimension; exposing the second area of the surface to light having a second wavelength while exposing the second area to the quantum dot forming environment that causes the quantum dots in the second area to form at a third growth rate while the quantum dots have a dimension less than a second threshold dimension; and processing the layer to form the LED device.Type: GrantFiled: December 6, 2018Date of Patent: February 25, 2020Assignee: X Development LLCInventors: Martin Friedrich Schubert, Michael Jason Grundmann
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Patent number: 10562306Abstract: A liquid ejection head is manufactured by covering a mold material arranged on a patterned protecting layer on a substrate and subsequently removing the mold material to produce a flow path. A sacrificial layer employed as the mold material operates as mask for patterning the protecting layer.Type: GrantFiled: June 12, 2018Date of Patent: February 18, 2020Assignee: CANON KABUSHIKI KAISHAInventors: Seiichiro Yaginuma, Koji Sasaki, Kazuhiro Asai
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Patent number: 10493758Abstract: Ejection device for fluid, comprising a solid body including: first semiconductor body including a chamber for containing the fluid, an ejection nozzle in fluid connection with the chamber, and an actuator operatively connected to the chamber to generate, in use, one or more pressure waves in the fluid such as to cause ejection of the fluid from the ejection nozzle; and a second semiconductor body including a channel for feeding the fluid to the chamber, coupled to the first semiconductor body, in such a way that the channel is in fluid connection with the chamber. The second semiconductor body integrates a damping cavity over which extends a damping membrane, the damping cavity and the damping membrane extending laterally to the channel for feeding the fluid.Type: GrantFiled: January 30, 2018Date of Patent: December 3, 2019Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS, INC.Inventors: Domenico Giusti, Marco Ferrera, Carlo Luigi Prelini, Simon Dodd
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Patent number: 10418785Abstract: An ultraviolet (UV) radiation emitting device includes an epitaxial heterostructure comprising an AlGaInN active region. The AlGaInN active region includes one or more quantum well structures with Al content greater than about 50% and having a non-c-plane crystallographic growth orientation. The AlGaInN active region is configured to generate UV radiation in response to excitation by an electron beam generated by an electron beam pump source.Type: GrantFiled: November 19, 2018Date of Patent: September 17, 2019Assignee: Palo Alto Research Center IncorporatedInventors: Thomas Wunderer, Noble M. Johnson
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Patent number: 10365510Abstract: The present invention provides a method for manufacturing an organic functional layer in a display panel by adhering an organic material pattern corresponding to the transfer protrusions from an organic material layer by using the transfer protrusion on a transfer head, then, the organic material pattern which is adhered by the transfer head is disposed on a receiving substrate, so as to form a patterned organic functional layer on the receiving substrate. The present invention provides a patterned organic functional layer in a display panel by a micro transfer print technology, which is capable of effectively reducing the material consumption of the organic functional layer and the production method is simple, which is capable of effectively reducing the online production cycle.Type: GrantFiled: June 20, 2017Date of Patent: July 30, 2019Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Lixuan Chen
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Patent number: 10326054Abstract: In an example, the present invention provides a light-emitting device configured to emit electromagnetic radiation in a range of 210 to 360 nanometers. The device has a substrate member comprising a surface region. The device has a thickness of AlGaN material formed overlying the surface region and an aluminum concentration characterizing the AlGaN material having a range of 0 to 100%. The device has a boron doping concentration characterizing the AlGaN material having a range between 1e15 to 1e20 atoms/centimeter3.Type: GrantFiled: January 22, 2018Date of Patent: June 18, 2019Assignee: RayVio CorporationInventors: Yitao Liao, Douglas A. Collins, Wei Zhang
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Patent number: 10135227Abstract: An ultraviolet (UV) radiation emitting device includes an epitaxial heterostructure comprising an AlGaInN active region. The AlGaInN active region includes one or more quantum well structures with Al content greater than about 50% and having a non-c-plane crystallographic growth orientation. The AlGaInN active region is configured to generate UV radiation in response to excitation by an electron beam generated by an electron beam pump source.Type: GrantFiled: May 19, 2017Date of Patent: November 20, 2018Assignee: Palo Alto Research Center IncorporatedInventors: Thomas Wunderer, Noble M. Johnson
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Patent number: 10128404Abstract: A superlattice and method for forming that superlattice are disclosed. In particular, an engineered layered single crystal structure forming a superlattice is disclosed. The superlattice provides p-type or n-type conductivity, and comprises alternating host layers and impurity layers, wherein: the host layers consist essentially of a semiconductor material; and the impurity layers consist of a donor or acceptor material.Type: GrantFiled: May 12, 2017Date of Patent: November 13, 2018Assignee: Silanna UV Technologies Pte LtdInventor: Petar Atanackovic
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Patent number: 9935240Abstract: A near-infrared light emitting device can include semiconductor nanocrystals that emit at wavelengths beyond 1 ?m. The semiconductor nanocrystals can include a core and an overcoating on a surface of the core.Type: GrantFiled: December 10, 2013Date of Patent: April 3, 2018Assignee: Massachusetts Institute of TechnologyInventors: Geoffrey J. S. Supran, Katherine W. Song, Gyuweon Hwang, Raoul Emile Correa, Yasuhiro Shirasaki, Moungi G. Bawendi, Vladimir Bulovic, Jennifer Scherer
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Patent number: 9899571Abstract: Disclosed is a semiconductor light emitting device. The semiconductor light emitting device includes a plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; a pad on the plurality of compound semiconductor layers; an electrode layer under the plurality of compound semiconductor layers; and a supporting member disposed under the plurality of compound semiconductor layers and corresponding to the pad.Type: GrantFiled: July 3, 2014Date of Patent: February 20, 2018Assignee: LG INNOTEK CO., LTD.Inventor: Hwan Hee Jeong
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Patent number: 9853187Abstract: Disclosed is a light emitting diode using light of a short wavelength band. The light emitting diode includes a first conductivity type semiconductor layer having a front side and a back side, a second conductivity type semiconductor layer having a front side and a back side, an active layer formed between the back side of the first conductivity type semiconductor layer and the front side of the second conductivity type semiconductor layer, a first electrode electrically connected to the first conductivity type semiconductor layer, a second conductivity type reflective layer formed on the back side of the second conductivity type semiconductor layer, and a reflective part formed on the second conductivity type reflective layer to reflect light of a short wavelength band and light of a blue wavelength band and electrically connected to the second conductivity type semiconductor layer. The second conductivity type reflective layer includes DBR unit layers.Type: GrantFiled: November 18, 2016Date of Patent: December 26, 2017Assignee: Lumens Co., Ltd.Inventor: Dae Won Kim
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Orifice surface, print head comprising an orifice surface and method for forming the orifice surface
Patent number: 9833996Abstract: Disclosed is a method for preparing a nozzle surface provided with a coating having anti-wetting and anti-fouling property. The method is based, for example, on the self-healing property of the coating used in the method. Also disclosed is a nozzle surface having such coating and a print head having the nozzle surface.Type: GrantFiled: November 29, 2016Date of Patent: December 5, 2017Assignee: OCÉ-TECHNOLOGIES B.V.Inventors: Zhanhua Wang, Johannes T. Zuilhof, Marcus J. Van den Berg -
Patent number: 9679821Abstract: Provided are methods of generating and revising overlay correction data, a method of performing a photolithography process using the overlay correction data, and a method of performing a photolithography process while revising the overlay correction data.Type: GrantFiled: January 20, 2016Date of Patent: June 13, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Woojin Jung, Sang-Ho Yun, Un Jeon, Byeongsoo Kim, Cheolhong Kim, Taehong Min, Joonsoo Park
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Patent number: 9627580Abstract: A method of growing an AlGaN semiconductor material utilizes an excess of Ga above the stoichiometric amount typically used. The excess Ga results in the formation of band structure potential fluctuations that improve the efficiency of radiative recombination and increase light generation of optoelectronic devices, in particular ultraviolet light emitting diodes, made using the method. Several improvements in UV LED design and performance are also provided for use together with the excess Ga growth method. Devices made with the method can be used for water purification, surface sterilization, communications, and data storage and retrieval.Type: GrantFiled: October 5, 2012Date of Patent: April 18, 2017Assignee: Trustees of Boston UniversityInventors: Yitao Liao, Theodore D. Moustakas
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Patent number: 9616666Abstract: Provided is a method of manufacturing an element substrate, including: forming first and second resists on a predetermined surface of a substrate so that part of the predetermined surface is exposed; etching the substrate with the first and second resists being used as a mask to form a first recess in the substrate; removing the second resist to expose a portion of the substrate that is different from the first recess; etching the substrate with the first resist being used as a mask to deepen the first recess and to form a second recess communicating with the first recess in the substrate; and covering openings of the first and second recesses with an orifice forming member to form a pressure chamber by the first recess and an orifice forming member and to form a flow reducing portion by the second recess and the orifice forming member.Type: GrantFiled: August 7, 2015Date of Patent: April 11, 2017Assignee: CANON KABUSHIKI KAISHAInventors: Toshifumi Yoshioka, Toru Nakakubo, Shinichiro Watanabe
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Patent number: 9552984Abstract: There are provided a processing method of a substrate in which in forming a trench on the substrate by etching, a side wall surrounding the trench is surely protected, and a manufacturing method of a liquid ejection head. The methods include: repeating sequentially a plurality of cycles of a trench forming step of forming the trench on a printing element substrate, a first protection layer forming step of forming a passivation layer, and a first protection layer removing step of removing a portion at which the trench is excavated in the passivation layer. A second protection layer forming step and a second protection layer removing step are performed between the trench forming step through the first protection layer removing step repeated in a plurality of cycles and the trench forming step through the first protection layer removing step repeated next.Type: GrantFiled: December 9, 2015Date of Patent: January 24, 2017Assignee: CANON KABUSHIKI KAISHAInventors: Atsushi Hiramoto, Atsunori Terasaki, Ryoji Kanri
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Patent number: 9472627Abstract: A III-V compound semiconductor heterostructure grown on a substrate is described. The heterostructure includes a first semiconductor layer, wherein the first layer semiconductor layer is a compound semiconductor layer with (III) (V), wherein (III) represents one or more group-III elements and (V) represents one or more group-V elements, an intermediate layer on the first semiconductor layer, wherein the intermediate layer is a compound semiconductor layer with (III)x>1(V)2-x, and wherein the intermediate layer has a thickness of 10 monolayers or below, and a second semiconductor layer, wherein the first layer semiconductor layer is a compound semiconductor layer with (III)1(V)1.Type: GrantFiled: October 17, 2013Date of Patent: October 18, 2016Assignee: Brolis Semiconductors Ltd.Inventors: Kristijonas Vizbaras, Augustinas Vizbaras
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Patent number: 9412629Abstract: An apparatus and method bond a first wafer to a second wafer. The apparatus includes a first pressure application device configured to apply pressure at a central region of the first wafer in a direction toward the second wafer to initiate a bonding process between the first wafer and the second wafer. The apparatus also includes one or more second pressure application devices configured to apply pressure between the central region and an outer edge of the first wafer to complete the bonding process. The one or more second pressure application devices apply pressure on the first wafer after the first pressure application device has initiated the bonding process and while the first pressure application device continues to apply pressure at the central region. A controller controls the first pressure application device and the one or more second pressure application devices.Type: GrantFiled: October 24, 2012Date of Patent: August 9, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Tuan A. Vo
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Patent number: 9371225Abstract: A substrate processing method for forming a through-hole in a substrate by reactive ion etching includes preparing a substrate that has a first surface and a second surface and on the first surface side of which a first layer and a second layer are disposed, the second surface being on the opposite side to the first surface, the second layer covering the first layer; and performing reactive ion etching on the substrate from the second surface to form a through-hole extending through the substrate from the first surface to the second surface, the reactive ion etching being performed to reach the first layer. The etching rate of the second layer for the reactive ion etching is lower than that of the first layer.Type: GrantFiled: July 14, 2014Date of Patent: June 21, 2016Assignee: Canon Kabushiki KaishaInventors: Seiko Minami, Toshiyasu Sakai
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Patent number: 9362389Abstract: A nitride-based field effect transistor (FET) comprises a compositionally graded and polarization induced doped p-layer underlying at least one gate contact and a compositionally graded and doped n-channel underlying a source contact. The n-channel is converted from the p-layer to the n-channel by ion implantation, a buffer underlies the doped p-layer and the n-channel, and a drain underlies the buffer.Type: GrantFiled: August 27, 2014Date of Patent: June 7, 2016Assignee: University of Notre Dame du LacInventors: Huili (Grace) Xing, Debdeep Jena, Kazuki Nomoto, Bo Song, Mingda Zhu, Zongyang Hu
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Patent number: 9338837Abstract: According to one embodiment, there is provided a lighting device which includes a substrate; a light emitting element which is provided on the substrate; and a resistive element which is provided on the substrate, and is connected to the light emitting element in series. A voltage rate of the resistive element when a value of a first voltage which is reduced to half is applied to a first circuit to which the light emitting element and the resistive element are connected in series becomes equal to or smaller than 25% of a voltage rate of the resistive element when the first voltage is applied to the first circuit.Type: GrantFiled: March 13, 2014Date of Patent: May 10, 2016Assignee: Toshiba Lighting & Technology CorporationInventor: Kiyokazu Hino
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Patent number: 9324615Abstract: A method of producing a semiconductor body includes providing a semiconductor wafer having at least two chip regions and at least one separating region arranged between the chip regions, wherein the semiconductor wafer includes a layer sequence, an outermost layer of which has, at least within the separating region a transmissive layer transmissive to electromagnetic radiation, carrying out at least one of: removing the transmissive layer within the separating region, applying an absorbent layer within the separating region, increasing the absorption coefficient of the transmissive layer within the separating region, and separating the chip regions along the separating regions by a laser.Type: GrantFiled: April 4, 2012Date of Patent: April 26, 2016Assignee: OSRAM Opto Semiconductors GmbHInventors: Korbinian Perzlmaier, Heribert Zull, Franz Eberhard, Thomas Veit, Mathias Kämpf, Jens Dennemarck
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Patent number: 9259932Abstract: An assembly for selectively etching an inkjet printhead includes a substrate and printhead layers formed on the substrate. A bonding region can provide a location on the printhead layers for an electrical bond. An ink channeling region can be defined at least in part by the printhead layers. A mask layer can partially cover the printhead layers and include a first opening positioned over the bonding region and a second opening positioned over the ink channeling region. The assembly can also include a via at the first opening and a trench at the second opening having greater depth than the via.Type: GrantFiled: May 27, 2011Date of Patent: February 16, 2016Assignee: Hewlett-Packard Development Company, L.P.Inventors: Lawrence H. White, Robel Vina, Sara Jensen Homeijer, Terry Mcmahon
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Patent number: 9252375Abstract: A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.Type: GrantFiled: March 15, 2013Date of Patent: February 2, 2016Assignee: LuxVue Technology CorporationInventors: Andreas Bibl, Kapil V. Sakariya, Charles R. Griggs, James Michael Perkins
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Patent number: 9219246Abstract: The invention relates to an organic electronic device, particularly an OLED device (100), and to a method for its manufacturing. The device (100) comprises at least one functional unit (LU1, LU2, LU3) with an organic layer (120). On top of this functional unit (LU1, LU2, LU3), at least one inorganic encapsulation layer (140, 141) and at least one organic encapsulation layer (150, 151) are disposed in which at least one conductive line (161, 162) is embedded. In this way an OLED with a thin film encapsulation can be provided that can electrically be contacted at contact points (CL) on its back side.Type: GrantFiled: October 6, 2011Date of Patent: December 22, 2015Assignee: KONINKLIJKE PHILIPS N.V.Inventors: Sören Hartmann, Holger Schwab, Herbert Lifka, Herbert Friedrich Boerner
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Patent number: 9142798Abstract: A package of an environmental sensitive electronic element including a first substrate, a second substrate, an environmental sensitive electronic element, a flexible structure layer and a filler layer is provided. The environmental sensitive electronic element is disposed on the first substrate and located between the first substrate and the second substrate. The environmental sensitive electronic element includes an anode layer, a hole injecting layer, a hole transporting layer, an organic light emitting layer, a cathode layer and an electron injection layer. The flexible structure layer is disposed on the environmental sensitive electronic element and includes a soft layer, a trapping layer and a protective layer. The material of the trapping layer is the same as the material of the electron injection layer. The filler layer is disposed between the first substrate and the second substrate and encapsulates the environmental sensitive electronic element and the flexible structure layer.Type: GrantFiled: January 19, 2012Date of Patent: September 22, 2015Assignee: Industrial Technology Research InstituteInventors: Kuang-Jung Chen, Jian-Lin Wu, Shu-Tang Yeh
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Patent number: 9102145Abstract: A method for producing a liquid ejecting head of the present invention includes the steps of: forming an etching stop layer on a portion corresponding to a region in which an independent supply port is formed, on a first face of a substrate; conducting dry etching treatment for the substrate from a second face side until the etched portion reaches the etching stop layer; and removing the etching stop layer by isotropic etching to form the independent supply port, after having conducted the dry etching treatment, wherein the isotropic etching is conducted in such a state that a side etching stopper portion having etching resistance to the isotropic etching is formed in the side face perimeter of the etching stop layer.Type: GrantFiled: April 5, 2013Date of Patent: August 11, 2015Assignee: Canon Kabushiki KaishaInventors: Masahiko Kubota, Ryoji Kanri, Akihiko Okano, Atsushi Hiramoto, Masataka Sakurai, Yoshiyuki Fukumoto
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Patent number: 9096063Abstract: A method of manufacturing a liquid ejection head includes the steps of (1) forming a recess in a second surface of a substrate to form a common supply port, (2) forming an etching mask, which specifies opening positions of independent supply ports, on a bottom surface of the common supply port, and (3) performing ion etching using plasma with the etching mask employed as a mask, thereby forming the independent supply ports. The etching mask has an opening pattern formed therein such that respective distances from an ejection energy generation element to openings of two independent supply ports adjacent to the ejection energy generation element on the first surface side of the substrate are equal to each other.Type: GrantFiled: January 22, 2013Date of Patent: August 4, 2015Assignee: Canon Kabushiki KaishaInventors: Masahiko Kubota, Ken Tsuchii, Masataka Sakurai, Yoshiyuki Nakagawa, Akiko Saito, Shinji Kishikawa, Ryoji Kanri, Atsunori Terasaki, Akihiko Okano, Atsushi Hiramoto
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Patent number: 9093608Abstract: The process for the manufacture of a light-emitting diode comprises the following stages: the formation of a stack (1) of layers intended to emit light comprising first (2), second (3) and third (4) layers of aluminum gallium nitride, the said second layer (3), positioned between the first and third layers (2, 4), having an aluminum gallium nitride composition different from that of the first and third layers (2, 4); and the implementation of a demixing of the second layer (3) of aluminum gallium nitride carried out after formation of the said second layer.Type: GrantFiled: December 26, 2013Date of Patent: July 28, 2015Assignee: Commissariat a L'energie Atomique et aux Energies AlternativesInventor: Bruno Daudin
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Patent number: 9048100Abstract: A base at least one principal plane of which is a nitride is prepared for use in epitaxial growth. The base is placed on a susceptor in an epitaxial growth reactor and heated to a predetermined temperature (step A). The heating is started with inactive, nitrogen gas being supplied into the reactor. Then, active, NH3 gas is supplied. Then, a growth step (step B) of a first nitride semiconductor layer is started without an intervening step of thermally cleaning the principal nitride plane of the base. In step B, the first nitride semiconductor layer is epitaxially grown on a principal nitride plane of a base without supply of an Si source material. Then, a relatively thick, second nitride semiconductor layer is epitaxially grown on the first nitride semiconductor layer by supplying an n-type dopant source material (step C).Type: GrantFiled: November 20, 2008Date of Patent: June 2, 2015Assignee: Mitsubishi Chemical CorporationInventors: Hideyoshi Horie, Kaori Kurihara
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Patent number: 9038269Abstract: A nanoprinthead including an array of nanotip cantilevers, where each nanotip cantilever includes a nanotip at an end of a cantilever, and a method for forming the nanoprinthead. Each nanotip may be individually addressable through use of an array of piezoelectric actuators. Embodiments for forming a nanoprinthead including an array of nanotip cantilevers can include an etching process from a material such as a silicon wafer, or the formation of a metal or dielectric nanotip cantilever over a substrate. The nanoprinthead may operate to provide uses for technologies such as dip-pen nanolithography, nanomachining, and nanoscratching, among others.Type: GrantFiled: April 2, 2013Date of Patent: May 26, 2015Assignee: XEROX CORPORATIONInventors: Peter J. Nystrom, Andrew W. Hays, Bijoyraj Sahu
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Patent number: 9029174Abstract: A structure includes a substrate, a template layer formed on the surface of the substrate and including an AlN layer, and a device structure portion formed by stacking AlGaN semiconductor layers on the template layer. For the structure, the AlN layer is irradiated from a side close to the substrate with a laser light with a wavelength by which the laser light passes through the substrate and the laser light is absorbed by the AlN layer, in a state in which the AlN layer receives compressive stress from the substrate. This allows the AlN layer to expand more than the surface of the substrate on at least an interface between the AlN layer and the substrate so as to increase the compressive stress, in order to remove the substrate from the AlN layer.Type: GrantFiled: February 25, 2011Date of Patent: May 12, 2015Assignees: Meijo University, Soko Kagaku Co., Ltd.Inventors: Motoaki Iwaya, Hiroshi Amano, Isamu Akasaki
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Patent number: 9023669Abstract: A processing method of a silicon substrate including forming a second opening in a bottom portion of a first opening using a patterning mask having a pattern opening by plasma reactive ion etching. The reactive ion etching is performed with a shield structure formed in or on the silicon substrate, the shield structure preventing inside of the first opening from being exposed to the plasma.Type: GrantFiled: July 20, 2011Date of Patent: May 5, 2015Assignee: Canon Kabushiki KaishaInventors: Atsushi Hiramoto, Masahiko Kubota, Ryoji Kanri, Akihiko Okano, Yoshiyuki Fukumoto, Atsunori Terasaki
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Patent number: 9023670Abstract: The disclosure generally relates to a modular printhead configured for ease of access and quick replacement of the printhead. In one embodiment, the disclosure is directed to an integrated printhead which includes: a printhead die supporting a plurality of micropores thereon; a support structure for supporting the printhead die; a heater interposed between the printhead die and the support structure; and an electrical trace connecting the heater to a supply source. The support structure accommodates the electrical trace through a via formed within it so as to form a solid state printhead containing all of the connections within and providing easily replaceable printhead.Type: GrantFiled: November 5, 2013Date of Patent: May 5, 2015Assignee: Kateeva, Inc.Inventors: Dariusz Golda, Valerie Gassend, Hyeun-Su Kim
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Publication number: 20150109368Abstract: A liquid ejection head including a recording element substrate provided with a substrate and a flow-path-forming member forming a flow path in a principal surface of the substrate, a support member supporting the recording element substrate and an underfill material covering at least a joint portion at which the substrate and the support member are joined to each other, wherein the flow-path-forming member is formed in such a manner that an end portion thereof projects from at least one side surface of the substrate, the underfill material covers an external surface of the joint portion and covers the at least one side surface of the substrate in such a manner that the underfill material reaches the projecting end portion of the flow-path-forming member.Type: ApplicationFiled: September 8, 2014Publication date: April 23, 2015Inventors: Satoshi IBE, Shingo Nagata
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Publication number: 20150111321Abstract: A method for processing a silicon substrate, comprising the steps of providing a silicon substrate having a first surface and a second surface, forming a non-penetrated hole extending from the first surface toward the second surface side in the silicon substrate, sticking a sealing tape comprising a support member and an adhesive layer on the first surface and filling at least part of the non-penetrated hole with the adhesive layer, performing reactive ion etching from the second surface toward the first surface side to allow the reactive ion etching to reach the adhesive layer filled in the non-penetrated hole and to expose the adhesive layer, and peeling the sealing tape from the silicon substrate to form a through hole in the silicon substrate.Type: ApplicationFiled: October 20, 2014Publication date: April 23, 2015Inventors: Seiko Minami, Toshiyasu Sakai, Masataka Kato, Masaya Uyama, Hiroshi Higuchi, Yoshinao Ogata
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Patent number: 9012247Abstract: A method of manufacturing an ink jet printhead includes: providing a silicon substrate including active ejecting elements; providing a hydraulic structure layer; providing a silicon orifice plate having a plurality of nozzles for ejection of said ink; and assembling the silicon substrate with said hydraulic structure layer and said silicon orifice plate. Providing the silicon orifice plate comprises: providing a silicon wafer having a substantially planar extension delimited by a first and a second surfaces; performing a thinning step at the second surface so as to remove a central portion having a preset height; and forming in the silicon wafer a plurality of through holes, each defining a respective nozzle for ejection of the ink.Type: GrantFiled: June 7, 2011Date of Patent: April 21, 2015Assignee: SICPA Holding SAInventors: Silvia Baldi, Danilo Bich, Lucia Giovanola, Anna Merialdo, Paolo Schina
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Patent number: 8993357Abstract: A method for manufacturing a liquid discharge includes a process of forming a plurality of blind holes extending from a first surface of the silicon substrate toward a second surface which is a surface opposite to the first surface in the silicon substrate and a process of subjecting the silicon substrate in which the plurality of blind holes are formed to anisotropic etching from the first surface to form a liquid supply port in the silicon substrate, in which, in the process of forming the liquid supply port, the silicon in a region sandwiched by the plurality of blind holes when the silicon substrate is seen from the second surface side is left without being removed by the anisotropic etching to use the left silicon as a beam.Type: GrantFiled: March 5, 2014Date of Patent: March 31, 2015Assignee: Canon Kabushiki KaishaInventors: Keisuke Kishimoto, Taichi Yonemoto