Complementary Bipolar Transistors Patents (Class 438/313)
  • Patent number: 7071536
    Abstract: A high voltage semiconductor device having a high current gain hFE is formed with a collector region (20) of a first conduction type, an emitter region (40) of the first conduction type, and a base region (30) of a second conduction type opposite to the first conduction type located between the collector region and the emitter region. The free carrier density of the base region (30) where no depletion layer is formed is smaller than the space charge density of a depletion layer formed in the base region (30).
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: July 4, 2006
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Saichirou Kaneko, Masakatsu Hoshi, Yoshinori Murakami, Tetsuya Hayashi, Hideaki Tanaka
  • Patent number: 7033899
    Abstract: A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: April 25, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Cha-Hsin Lin, Zing-Way Pei, Shing-Chii Lu, Wen-Yi Hsieh
  • Patent number: 7015085
    Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: March 21, 2006
    Assignee: Intel Corporation
    Inventors: Shahriar Ahmed, Mark Bohr, Stephen Chambers, Richard Green
  • Patent number: 7008852
    Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: March 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Douglas D. Coolbaugh, Jeffrey Gilbert, Joseph R. Greco, Glenn R. Miller
  • Patent number: 7001806
    Abstract: A semiconductor structure comprises a buried first semiconductor layer of a first doping type, a second semiconductor layer of the first doping type on the buried semiconductor layer, which is less doped than the buried first semiconductor layer, a semiconductor area of a second doping type on the second semiconductor layer, so that a pn junction is formed between the semiconductor area and the second semiconductor layer, and a recess present below the semiconductor area in the buried first semiconductor layer, which comprises a semiconductor material of the first doping type, which can be less doped than the buried first semiconductor layer and has a larger distance to the semiconductor area of the second doping type on the second semiconductor layer, such that the breakdown voltage across the pn junction is higher than if the recess were not provided.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: February 21, 2006
    Assignee: Infineon Technologies AG
    Inventors: Armin Tilke, Wolfgang Klein
  • Patent number: 6992338
    Abstract: According to an exemplary method in one embodiment, a transistor gate is fabricated on a substrate. Next, an etch stop layer may be deposited on the substrate. The etch stop layer may, for example, be TEOS silicon dioxide. Thereafter, a conformal layer is deposited over the substrate and the transistor gate. The conformal layer may, for example, be silicon nitride. An opening is then etched in the conformal layer. Next, a base layer is deposited on the conformal layer and in the opening. The base layer may, for example, be silicon-germanium. According to this exemplary embodiment, an emitter may be formed on the base layer in the opening. Next, the base layer is removed from the conformal layer. The conformal layer is then etched back to form a spacer adjacent to the transistor gate. In one embodiment, a structure is fabricated according to the above described exemplary method.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: January 31, 2006
    Assignee: Newport Fab, LLC
    Inventors: Kevin Q. Yin, Amol Kalburge, Klaus F. Schuegraf
  • Patent number: 6979577
    Abstract: Concerning a plurality of wafers which compose one lot, amounts of misalignment between alignment marks of these wafers and alignment patterns transferred on photoresists are measured in advance, and then, a mutual relation between a thickness of an interlayer dielectric film and a value of Wafer Scaling is calculated. When exposure is actually executed, first, an interlayer dielectric film is formed on the alignment marks in a lot and planarized. After that, the thickness of the interlayer dielectric film after planarization is measured. The value of the Wafer Scaling is estimated from an average value of the thicknesses of the interlayer dielectric films in the lot and the above-mentioned mutual relation. Then, photoresists are coated on the interlayer dielectric films in the lot, and the photoresists are exposed while the correction is executed so as to compensate the value of the Wafer Scaling.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: December 27, 2005
    Assignee: FASL LLC
    Inventor: Tohru Higashi
  • Patent number: 6953728
    Abstract: This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: October 11, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Eiichi Murakami, Akio Nishida, Kazunori Umeda, Kousuke Okuyama, Toshiaki Yamanaka, Jiro Yugami, Shinichiro Kimura
  • Patent number: 6940149
    Abstract: Structure and a method are provided for making a bipolar transistor, the bipolar transistor including a collector, an intrinsic base overlying the collector, an emitter overlying the intrinsic base, and an extrinsic base spaced from the emitter by a gap, the gap including at least one of an air gap and a vacuum void.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: September 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Rama Divakaruni, Gregory Freeman, Marwan Khater, William Tonti
  • Patent number: 6939771
    Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: September 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Douglas D. Coolbaugh, Jeffrey Gilbert, Joseph R. Greco, Glenn R. Miller
  • Patent number: 6936910
    Abstract: A method and a BICMOS structure are provided. The BiCMOS structure includes an SOI substrate having a bottom Si-containing layer, a buried insulating layer located atop the bottom Si-containing layer, a top Si-containing layer atop the buried insulating layer and a sub-collector which is located in an upper surface of the bottom Si-containing layer. The sub-collector is in contact with a bottom surface of the buried insulating layer.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: August 30, 2005
    Assignee: International Business Machines Corporation
    Inventors: John Joseph Ellis-Monaghan, Alvin Jose Joseph, Qizhi Liu, Kirk David Peterson
  • Patent number: 6917061
    Abstract: A heterojunction bipolar transistor is provided that has a reduced turn-on voltage threshold. A base spacer layer is provided and alternately an emitter layer is provided that has a lowered energy gap. The lowered energy gap of the base spacer or the emitter spacer allow the heterojunction bipolar transistor to realize a lower turn-on voltage threshold. The thickness of the emitter layer if utilized is kept to a minimum to reduce the associated space charge recombination current in the heterojunction bipolar transistor.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: July 12, 2005
    Assignee: Microlink Devices, Inc.
    Inventors: Noren Pan, Byung-Kwon Han
  • Patent number: 6911369
    Abstract: The present disclosure provides a process for producing a SiGe layer in a bipolar device having a reduced amount of gaps or discontinuities on a shallow trench isolation (STI) region use for a base electrode connection. The process is used for forming an SiGe layer for use in a semiconductor device. The process includes doping a single crystal substrate with a first dopant type, baking the doped single crystal substrate at a temperature less than 900° C., and at a pressure less than 100 torr; and depositing the SiGe layer on the baked single crystal substrate (epi SiGe) to serve as the base electrode and on the STI region (poly SiGe) to serve as a connection for the base electrode. The semiconductor device is thereby created from the combination of the doped single crystal substrate and the deposited SiGe layer.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: June 28, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuen-Chyr Lee, Liang-Gi Yao, Fu Chin Yang, Shih-Chang Chen, Mong-Song Liang
  • Patent number: 6908824
    Abstract: A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: June 21, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Jian Xun Li, Lap Chan, Purakh Raj Verma, Jia Zhen Zheng, Shao-fu Sanford Chu
  • Patent number: 6893934
    Abstract: A Si1-xGex layer 111b functioning as the base composed of an i—Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n? polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: May 17, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Teruhit Ohnishi, Akira Asai
  • Patent number: 6888221
    Abstract: A method and structure for a bipolar transistor comprising a patterned isolation region formed below an upper surface of a semiconductor substrate and a single crystal extrinsic base formed on an upper surface of the isolation region. The single crystal extrinsic base comprises a portion of the semiconductor substrate located between the upper surface of the isolation region and the upper surface of the semiconductor substrate. The bipolar transistor further comprises a single crystal intrinsic base, wherein a portion of the single crystal extrinsic base merges with a portion of the single crystal intrinsic base. The isolation region electrically isolates the extrinsic base from a collector. The intrinsic and extrinsic bases separate the collector from an emitter. The extrinsic base comprises epitaxially-grown silicon. The isolation region comprises an insulator, which comprises oxide, and the isolation region comprises any of a shallow trench isolation region and a deep trench isolation region.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: May 3, 2005
    Assignee: International Business Machines Corporation
    Inventors: Alvin J. Joseph, Qizhi Liu, Devendra K. Sadana
  • Patent number: 6828205
    Abstract: A method for using an isotropic wet etching process chemical process for trimming semiconductor feature sizes with improved critical dimension control including providing a hard mask overlying a substrate included in a semiconductor wafer said hard mask patterned for masking a portion of the substrate for forming a semiconductor feature according to an anisotropic plasma etching process; isotropically wet etching the hard mask to reduce a dimension of the hard mask prior to carrying out the anisotropic plasma etching process; and, anisotropically plasma etching a portion of the substrate not covered by the hard mask to form the semiconductor feature.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: December 7, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Ming-Huan Tsai, Ming-Jie Huang, Huan-Just Lin, Hun-Jan Tao
  • Patent number: 6818520
    Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base. The heterojunction bipolar transistor further comprises a first nitride spacer and a second nitride spacer situated on the base, where the first nitride spacer and the second nitride spacer are separated by a distance substantially equal to a critical dimension. For example, the first nitride spacer and the second nitride spacer may comprise LPCVD or RTCVD silicon nitride. According to this exemplary embodiment, the heterojunction bipolar transistor further comprises an emitter situated between said first nitride spacer and said second nitride spacer, where the emitter has a width substantially equal to the critical dimension. The emitter may, for example, comprise polycrystalline silicon. In another embodiment, a method that achieves the above-described heterojunction bipolar transistor is disclosed.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: November 16, 2004
    Assignee: Newport Fab, LLC dba Jazz Semiconductor
    Inventor: Klaus F. Schuegraf
  • Publication number: 20040224473
    Abstract: The present invention provides a method for manufacturing bipolar transistors having reduced parasitic resistance and therefore improved performance compared to conventionally made bipolar transistors. Dry etching of a compound semiconductor in the transistor allows a perimeter of the compound semiconductor layer to be substantially coextensive with a perimeter of an overlying metal layer. This, in turn, reduces the gap between the compound semiconductor and subsequently deposited metal layer to be minimized, thereby reducing the parasitic resistance of the bipolar transistor.
    Type: Application
    Filed: May 6, 2003
    Publication date: November 11, 2004
    Applicant: Lucent Technologies Inc.
    Inventors: Lay-Lay Chua, Yang Yang, Chun-Ting Liu
  • Patent number: 6815801
    Abstract: The present invention provides a vertical bipolar transistor 110, a method of manufacture therefor, and an integrated circuit including the same. The vertical bipolar transistor 110 may include, in one embodiment, a second epitaxial layer 140 located over a first epitaxial layer 130, wherein the second epitaxial layer includes at least two dopant profiles 143, 147. The vertical bipolar transistor 110 may further include a collector 154, a base 156 and an emitter 158 located over or within the second epitaxial layer 140.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: November 9, 2004
    Assignee: Texas Instrument Incorporated
    Inventors: Gregory G. Romas, Darrel C. Oglesby, Jr., Scott F. Jasper, Philip Najfus, Venkatesh Govindaraju, ChunLiang Yeh, James Lisenby
  • Patent number: 6808998
    Abstract: The present invention is an apparatus and method for eliminating parasitic bipolar transistor action in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device. In accordance with the invention a SOI electronic device and an active discharging device coupled to said SOI electronic device is provided to deactivate the parasitic bipolar transistor. The parasitic bipolar transistor action is deactivated by controlling the conduction of an active discharging device, said active discharging device being coupled to said SOI device.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: October 26, 2004
    Assignee: International Business Machines Corporation
    Inventors: Salvatore N. Storino, Andrew Douglas Davies
  • Patent number: 6806129
    Abstract: A method for forming a heterojunction bipolar transistor (HBT) includes forming an etch mask a top layer of the HBT to expose a portion of the emitter cap layer, and selectively etching the exposed portion of the emitter cap layer to (1) form a reentry feature and (2) to expose a portion of the emitter layer. The method further includes selectively etching the exposed portion of the emitter layer to expose a portion of the base layer, and forming a metal layer over the exposed portion of the base layer and the exposed portion of the emitter cap layer.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: October 19, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Scott A. McHugo, Gregory N. DeBrabander
  • Patent number: 6800531
    Abstract: A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the sub-collector, and also serves as an etch stop to protect the sub-collector during device fabrication. A portion of the sub-collector lateral to the remainder of the HBT is rendered electrically insulative, preferably by an ion implant, to provide electrical isolation for the device and improve its planarity by avoiding etching through the sub-collector.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: October 5, 2004
    Assignee: Rockwell Scientific Licensing, LLC
    Inventors: Richard L. Pierson, Jr., James Chingwei Li, Berinder P. S. Brar, John A. Higgins
  • Patent number: 6797577
    Abstract: A method is disclosed for the improvement of BiCMOS or CMOS manufactured device performance, specifically bipolar junction transistor performance, in a cost effective manner. The method provides for fewer masking operations during bipolar junction transistor formation, in a CMOS flow process, yet also provides for the bipolar junction transistor to be optimized.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: September 28, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Frank Scott Johnson, Jerold A. Seitchik, John Soji
  • Patent number: 6797995
    Abstract: A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the sub-collector, and also serves as an etch stop to protect the sub-collector during device fabrication. A portion of the sub-collector lateral to the remainder of the HBT is rendered electrically insulative, preferably by an ion implant, to provide electrical isolation for the device and improve its planarity by avoiding etching through the sub-collector.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: September 28, 2004
    Assignee: Rockwell Scientific Licensing, LLC
    Inventors: Richard L. Pierson, Jr., James Chingwei Li, Berinder P. S. Brar, John A. Higgins
  • Patent number: 6790722
    Abstract: A method and structure for forming an emitter in a vertical bipolar transistor includes providing a substrate having a collector layer and a base layer over the collector layer, forming a patterning mask over the collector layer, and filling openings in the mask with emitter material in a damascene process. The CMOS/vertical bipolar structure has the collector, base regions, and emitter regions vertically disposed on one another, the collector region having a peak dopant concentration adjacent the inter-substrate isolation oxide.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: September 14, 2004
    Assignee: International Business Machines Corporation
    Inventors: Ramachandra Divakaruni, Russell J. Houghton, Jack A. Mandelman, Wilbur D. Pricer, William R. Tonti
  • Patent number: 6780725
    Abstract: A method of manufacturing vertical NPN and PNP transistors on a substrate includes forming a first oxide film, a P-polycrystal silicon film, and a second oxide film successively on N-silicon epitaxial film on the substrate. An opening is made in the first oxide film to expose the N-silicon epitaxial film and a bottom of the P-polycrystal silicon film anisotropically etching the second oxide film and the P-polycrystal silicon film, and then isotropically etching the exposed first oxide film. A part of the opening is plugged by growing a selective epitaxial layer including a P-monocrystal layer from the surface of the N-silicon epitaxial film, and growing a polycrystal layer from the bottom of the P-polycrystal silicon film. Then, within a PNP transistor section, position and impurity concentration of a P-N junction are adjusted by self-aligned implanting or diffusing of P-impurities into the N-silicon epitaxial layer through the opening.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: August 24, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hirokazu Fujimaki
  • Patent number: 6773615
    Abstract: A method of producing a planar waveguiding device having a core [10] and a cladding [17]. The cladding has groves [11,12] directly interfacing [15,16] with the core [10]. A layer of core glass [10] is deposited on the surface of a substrate [23,24]. This layer is etched to produce a shaped layer which includes a first core portion [10] having the same configuration as the intended core [10] and an expanded core portion [30] wherein the core glass extends beyond the intended core boundary. A glass covering layer [21] is deposited over the etched core glass and grooves [11,12] are produced by etching through the covering layer [21] and into said expanded core portion [30].
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: August 10, 2004
    Assignee: British Telecommunications public limited company
    Inventors: David C Rogers, Graeme D Maxwell, Alistair J Poustie
  • Patent number: 6773973
    Abstract: A polysilicon-emitter-type transistor has a substrate with a collector region, a base region on the collector region, and an oxide layer on the base region with an emitter window therein exposing part of the base region. The polysilicon emitter is formed by forming a first polysilicon layer of approximately 30 to 100 Angstroms at least within the emitter window and at least on the exposed base region. Then, an interfacial oxide layer being approximately 5 to 50 Angstroms thick is formed in an upper portion of the first polysilicon layer, for example, by exposing the first polysilicon layer to oxygen and annealing. Then, a second polysilicon layer is formed on the interfacial oxide layer. The thickness of the second polysilicon layer may be approximately 500 to 5000 Angstroms thick. Subsequent annealing diffuses dopants in the emitter more uniformly into the base region.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: August 10, 2004
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Alexander Kalnitsky, Sudarsan Uppili, Sang Park
  • Patent number: 6767842
    Abstract: A semiconductor device wherein Si—Ge is the base of a bipolar transistor and a Silicon layer is the emitter. A method of making such a semiconductor device including steps of forming a Silicon dioxide layer on a Silicon substrate, using a photo resist application and exposure to define where a HBT device will be placed. Plasma etching the Silicon dioxide layer to define an undercut, epitaxially growing an Si—Ge layer and a Silicon layer, and continuing manufacture to form one or more bipolar and CMOS devices and define interconnect and passivation.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: July 27, 2004
    Assignee: LSI Logic Corporation
    Inventors: Robi Banerjee, Derryl J. Allman, David T. Price
  • Patent number: 6746928
    Abstract: According to one disclosed embodiment, a transistor gate is fabricated on a substrate. For example, the gate can be a polycrystalline silicon gate in a FET. Thereafter, a conformal layer is deposited over the substrate and the gate and is then etched back to form spacers on the sides of the gate. An underlying dielectric layer is formed on the substrate, gate, and spacers. The conformal layer and the underlying dielectric layer can be comprised of, for example, a dielectric such as silicon dioxide, silicon nitride, or a low-k dielectric. Next, an overcoat layer is fabricated on the underlying dielectric layer. The overcoat layer can be, for example, polycrystalline silicon. Following, an opening is etched in the overcoat layer and the underlying dielectric layer wherein subsequent films can be grown. For example, silicon germanium can be grown in the opening for fabrication of a silicon germanium heterojunction bipolar transistor.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: June 8, 2004
    Assignee: Newport Fab, LLC
    Inventors: Klaus F. Schuegraf, Marco Racanelli
  • Publication number: 20040102013
    Abstract: In accordance with some embodiments, codoping with carbon or fluorine and phosphorous may form NMOS source drain junctions with desirable short channel performance, improved drive current, and desirable polysilicon depletion. Thus, phosphorous doping levels may be increased, improving transistor performance without other significant adverse effects.
    Type: Application
    Filed: November 27, 2002
    Publication date: May 27, 2004
    Inventors: Jack Hwang, Mitchell Taylor, Craig Andyke, Mark Armstrong, Jerry Zietz, Harold Kennel, Stephen Cea, Thomas Hoffman, Seok-Hee Lee
  • Patent number: 6727146
    Abstract: This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: April 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Eiichi Murakami, Akio Nishida, Kazunori Umeda, Kousuke Okuyama, Toshiaki Yamanaka, Jiro Yugami, Shinichiro Kimura
  • Publication number: 20040077150
    Abstract: A switch semiconductor integrated circuit having a switch FET for controlling passage of a high-frequency signal so that the switch FET is switched between on-operation and off-operation. The switch semiconductor integrated circuit includes a logic control section using of an inverter circuit which generates the switching signal in accordance with a control signal applied from outside, the inverter circuit uses a junction-type FET the gate of the switch FET is connected to an output end of the inverter circuit via a gate resistor, and the output end is connected to a coupling capacitor which couples a part of the high-frequency signal. The coupled high-frequency signal is rectified by an equivalent diode between the gate and drain of the junction-type FET, and is superposed onto a DC voltage applied to the gate of the switch FET.
    Type: Application
    Filed: March 19, 2003
    Publication date: April 22, 2004
    Applicant: NEW JAPAN RADIO CO., LTD.
    Inventor: Hiroyuki Tosaka
  • Patent number: 6703283
    Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: March 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Douglas D. Coolbaugh, Jeffrey Gilbert, Joseph R. Greco, Glenn R. Miller
  • Patent number: 6699741
    Abstract: A high frequency bipolar transistor that has a silicon germanium intrinsic base region is formed in a semiconductor fabrication process that forms the extrinsic base regions after the intrinsic base region has been formed. The extrinsic base regions are epitaxially grown single crystal silicon that is doped during the growth.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: March 2, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Alexei Sadovnikov, Christopher John Knorr
  • Patent number: 6664157
    Abstract: Plug electrodes of silicon are formed so as to be buried in through holes in a first insulating film, the plug electrodes being electrically connected to the source and drain regions of a MISFET on the main surface of a semiconductor substrate. Then, a second insulating film is deposited thereon and holes are formed therein such that the plug electrodes of silicon are exposed. A barrier film is formed on the surfaces of the silicon plugs, and in the holes a dielectric is formed to form lower electrodes of the capacitor elements and an upper electrode therefor.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: December 16, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Shinpei Iijima, Yoshitaka Nakamura, Masahiko Hiratani, Yuichi Matsui, Naruhiko Nakanishi
  • Patent number: 6624497
    Abstract: An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: September 23, 2003
    Assignee: Intersil Americas, Inc
    Inventor: James D. Beasom
  • Publication number: 20030160302
    Abstract: Silicon carbide bipolar junction transistors having an overgrown base layer are provided. The bipolar junction transistors can be made with a very thin (e.g., 0.3 &mgr;m or less) base layer while still possessing adequate peripheral base resistance values. Self aligning manufacturing techniques for making the silicon carbide bipolar junction transistors are also provided. Using these techniques, the spacing between emitter and base contacts on the device can be reduced. The silicon carbide bipolar junction transistors can also be provided with edge termination structures such as guard rings to increase the blocking capabilities of the device.
    Type: Application
    Filed: February 22, 2002
    Publication date: August 28, 2003
    Inventors: Igor Sankin, Janna B. Dufrene
  • Patent number: 6590273
    Abstract: In the semiconductor integrated circuit device, a first P+ type buried layer formed as an anode region and an N+ type diffused region formed in a cathode region are spaced from each other in the direction of the depth. This makes it possible to provide a semiconductor integrated circuit device in which a large depletion layer forming region can be provided in an N type region at a PN junction formed by first and second epitaxial layers and when a reverse bias voltage is applied to a diode element and in which a withstand voltage can be maintained by a depletion layer thus formed to prevent breakdown of elements in the device attributable to a breakdown current.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: July 8, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeaki Okawa, Toshiyuki Ohkoda
  • Publication number: 20030116822
    Abstract: A bipolar transistor and a method for manufacturing the bipolar transistor are provided.
    Type: Application
    Filed: May 9, 2002
    Publication date: June 26, 2003
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Hun Joo Hahm
  • Patent number: 6579752
    Abstract: A method of manufacturing a semiconductor device comprising the step of epitaxially growing of an n-type doped layer of a semiconductor material using an n-type dopant gas, the growth process being performed at a pressure higher than 2.66×104 Pa.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: June 17, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Wiebe Barteld De Boer
  • Patent number: 6573157
    Abstract: A manufacturing method of semiconductor devices, micromachines such as semiconductor device, narrow pitch connectors, electrostatic actuators or piezoelectric actuators, and ink jet heads, ink jet printers, liquid crystal panels, and electronic appliances, including them characterized in that short circuit due to dusts floating in the air will not take place. In a method where a silicon wafer (30) undergoes dicing to manufacture semiconductor devices (20), a groove (30a) covered by an insulating layer and spanning a dicing line is formed in the above described silicon wafer, and the silicon wafer undergoes dicing along the dicing line.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: June 3, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Eiichi Sato
  • Patent number: 6569730
    Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: May 27, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jun-Lin Tsai, Ruey-Hsin Liu, Jei-Feng Hwang, Kuo-Chio Liu
  • Patent number: 6544835
    Abstract: There is provided a technique for forming an Ru film on the bottom of a deep hole with a considerable film thickness for the lower electrode of an information storage capacity element in order to improve the yield of manufacturing DRAMs. The Ru film is formed on the side wall and the bottom of a deep hole as material for preparing the lower electrode of an information storage capacity element to be produced there under the condition of a gasification flow rate ratio of the raw materials ((Ru(C2H5C5H4)2/O2) is not less than 10% Then, the ratio of the film thickness of the Ru film on the bottom “b” of the hole to the largest film thickness “a” of the Ru film in the hole is not less than 50%.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: April 8, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Yamamoto, Shinpei Iijima
  • Patent number: 6528375
    Abstract: A bipolar transistor compatible with CMOS processes utilizes only a single layer of polysilicon while maintaining the low base resistance associated with conventional double-polysilicon bipolar designs. Dopant is implanted to form the intrinsic base through the same dielectric window in which the polysilicon emitter contact component is later created. Following poly deposition within the window and etch to create the polysilicon emitter contact component, large-angle tilt ion implantation is employed to form a link base between the intrinsic base and a subsequently-formed base contact region. Tilted implantation enables the link base region to extend underneath the edges of the polysilicon emitter contact component, creating a low resistance path between the intrinsic base and the extrinsic base. Fabrication of the device is much simplified over a conventional double-poly transistor, particularly if tilted implantation is already employed in the process flow to form an associated structure such as an LDMOS.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: March 4, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Haydn James Gregory
  • Patent number: 6521972
    Abstract: An RF microwave power transistor has an input/output feed structure which functions as a low impedance microstrip line by providing a ground plane in close proximity to the feed structure on one surface of a semiconductor body. A second ground plane can be provided on an opposing surface of the semiconductor body with vias interconnecting the first and second ground planes. In addition to reducing feed impedance, a larger total transistor size can be provided before “odd mode oscillation” occurs.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: February 18, 2003
    Assignee: EiC Corporation
    Inventors: Wei-Shu Zhou, Shuo-Yuan Hsiao, Nanlei Larry Wang
  • Publication number: 20020185708
    Abstract: A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.
    Type: Application
    Filed: June 11, 2001
    Publication date: December 12, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORORATION
    Inventors: Douglas D. Coolbaugh, Kathryn T. Schonenberg
  • Patent number: 6492237
    Abstract: A method of forming an NPN semiconductor device includes the steps of forming a collector region within a substrate, forming a base region over the collector region, and forming an oxide-nitride-oxide stack over the base region. Once these three structures are formed, an opening is created through the oxide-nitride-oxide stack to expose the top surface of the base region. Then, a doped polysilicon material is used to fill the opening and make electrical contact to the base region. The use of the oxide-nitride-oxide stack with appropriate etching of the opening eliminates the exposure of the base region to reactive ion etch environment typical of prior art methods for forming NPN semiconductor devices. As an option, after the opening of the oxide-nitride-oxide stack is formed, a local oxidation of silicon (LOCOS) and etched can be preformed to create oxide spacers to line the opening wall above the base region.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: December 10, 2002
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Alexander Kalnitsky, Sang Hoon Park, Robert F. Scheer
  • Publication number: 20020158308
    Abstract: A semiconductor component and a method for fabricating it includes a substrate and an epitaxial layer situated thereon and integrating at least a first and a second bipolar component in the layer. The first and second bipolar components have a buried layer and different collector widths. The buried layer of the second component has a larger layer thickness than that of the first component; exactly one epitaxial layer is provided. The different collector widths produced as a result thereof are influenced by the outdiffusion of the dopant of the buried layers by other substances.
    Type: Application
    Filed: May 13, 2002
    Publication date: October 31, 2002
    Inventors: Jakob Huber, Wolfgang Klein