Air Isolation (e.g., Mesa, Etc.) Patents (Class 438/319)
  • Patent number: 9105488
    Abstract: A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: August 11, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Peter J. Zampardi, Jr., Hsiang-Chih Sun
  • Publication number: 20150137185
    Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base. An airgap is located vertically between the extrinsic base and the collector. A contact surface is located adjacent to the airgap. The contact surface is coupled with the collector. A spacer is located laterally between the airgap and the subcollector contact surface.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicant: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater, Anthony K. Stamper
  • Patent number: 9029229
    Abstract: Disclosed are devices and methods of forming the devices wherein pair(s) of first openings are formed through a dielectric layer and a first semiconductor layer into a substrate and, within the substrate, the first openings of each pair are expanded laterally and merged to form a corresponding trench. Dielectric material is deposited, filling the upper portions of the first openings and creating trench isolation region(s). A second semiconductor layer is deposited and second opening(s) are formed through the second semiconductor and dielectric layers, exposing monocrystalline portion(s) of the first semiconductor layer between the each pair of first openings. A third semiconductor layer is epitaxially deposited with a polycrystalline section on the second semiconductor layer and monocrystalline section(s) on the exposed monocrystalline portion(s) of the first semiconductor layer. A crystallization anneal is performed and a device (e.g.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, Peng Cheng, Vibhor Jain, Vikas Kumar Kaushal, Qizhi Liu, John J. Pekarik
  • Patent number: 8975146
    Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a lateral boundary for an active device region and an intrinsic base layer is formed on the substrate. The intrinsic base layer has a section overlying the active device region. After the intrinsic base layer is formed, the first isolation region is partially removed adjacent to the active device region to define a trench that is coextensive with the substrate in the active device region and that is coextensive with the first isolation region. The trench is at least partially filled with a dielectric material to define a second isolation region.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Marwan H. Khater
  • Patent number: 8872305
    Abstract: A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Renata A. Camillo-Castillo, James S. Dunn, David L. Harame, Anthony K. Stamper
  • Patent number: 8710549
    Abstract: A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: April 29, 2014
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Science
    Inventors: Xiaolu Huang, Jing Chen, Xi Wang, Deyuan Xiao
  • Patent number: 8697532
    Abstract: A wafer comprising at least one emitter-up Heterojunction Bipolar Transistor (HBT) and at least one emitter-down HBT on a common InP based semiconductor wafer. Isolation and N-type implants into the device layers differentiate an emitter-down HBT from an emitter-up HBT. The method for preparing a device comprises forming identical layers for all HBTs and performing ion implantation to differentiate an emitter-down HBT from an emitter-up HBT.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: April 15, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Mary Chen, Marko Sokolich
  • Patent number: 8692318
    Abstract: A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: April 8, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Chin-Te Kuo, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8466033
    Abstract: A light emitting diode comprises a substrate, a buffer layer, a semiconductor layer and a semiconductor light emitting layer. The buffer layer is disposed on the substrate. The semiconductor layer is disposed on the buffer layer. The semiconductor light emitting layer is disposed on the semiconductor layer. A plurality of voids is defined within the semiconductor layer. Each void encloses air therein. A method for manufacturing the light emitting diode is also provided. Light generated by the semiconductor light emitting layer toward the substrate is reflected by the voids to emit out of the light emitting diode.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: June 18, 2013
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Po-Min Tu, Shih-Cheng Huang, Shun-Kuei Yang, Chia-Hung Huang
  • Patent number: 8294194
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes memory transistors, an interlayer insulating film, a peripheral transistor and a sidewall. The memory transistors are formed on a semiconductor substrate. Each of the memory transistors includes a first stack gate which includes a floating gate electrode, a second gate insulating film, and a control gate electrode. The interlayer insulating film is formed between the first stack gates. The interlayer insulating film includes a first air gap. The peripheral transistor is formed on the substrate. The peripheral transistor includes a second stack gate which includes a first gate electrode, a third gate insulating film, and a second gate electrode. The sidewall is formed on a side surface of the second stack gate and includes a second air gap. An upper end of the second air gap is located at a position lower than the third gate insulating film.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: October 23, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiko Noda, Hidenobu Nagashima
  • Patent number: 8264060
    Abstract: Providing a first layer of a semiconductor structure having at least one air gap between conductive lines formed in the first layer. The air gap extends into the first layer from a first surface of the first layer. A barrier dielectric material over the first surface and the air gap is selected to have a dielectric constant less than 3.5 and to provide a barrier to prevent chemicals entering the at least one air gap. An air gap can extend from a first surface of the first layer to at least a portion of side surfaces of the at least two conductive lines to expose at least a portion of the side surfaces.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: September 11, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Greg Braeckelmann, Marius Orlowski, Andreas Wild
  • Publication number: 20120119262
    Abstract: A SiGe heterojunction bipolar transistor is fabricated by etching an epitaxially-formed structure to form a mesa that has a collector region, a cap region, and a notched SiGe base region that lies in between. A protective plug is formed in the notch of the SiGe base region so that thick non-conductive regions can be formed on the sides of the collector region and the cap region. Once the non-conductive regions have been formed, the protective plug is removed. An extrinsic base is then formed to lie in the notch and touch the base region, followed by the formation of isolation regions and an emitter region.
    Type: Application
    Filed: November 15, 2010
    Publication date: May 17, 2012
    Inventors: Wibo Van Noort, Jamal Ramdani, Andre Labonte, Donald Robertson Getchell
  • Patent number: 8084794
    Abstract: A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction which crosses the first direction and being disposed with a space interposed between the first wiring and the second wiring, and including a tantalum layer, a tantalum nitride layer formed over the tantalum layer, and a metal layer formed over the tantalum nitride layer.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: December 27, 2011
    Assignee: Fujitsu Limited
    Inventors: Yoichi Kamada, Naoya Okamoto
  • Patent number: 8071459
    Abstract: A method of sealing an air gap in a layer of a semiconductor structure comprises providing a first layer of the semiconductor structure having at least one air gap for providing isolation between at least two conductive lines formed in the first layer. The at least one air gap extends into the first layer from a first surface of the first layer. The method further comprises forming a barrier layer of a barrier dielectric material over the first surface of the first layer and the at least one air gap. The barrier dielectric material is selected to have a dielectric constant less than 3.5 and to provide a barrier to prevent chemicals entering the at least one air gap.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: December 6, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Greg Braeckelmann, Marius Orlowski, Andreas Wild
  • Patent number: 8043931
    Abstract: The embodiments of the present invention are directed to the formation of multi-layer silicon structures by forming and attaching a plurality of individual layers or structures where each of the layers or the structures comprises at least silicon forming a desired pattern. In some embodiments or some applications of some embodiments, at least one of the plurality of individual layers or the structures comprises a plurality of discrete silicon features that are combined together with at least one sacrificial material. In some embodiments or some applications of some embodiments, at least one of the plurality of individual layers or the structures comprises a plurality of discrete silicon features that are supported by a temporary substrate. Still in some embodiments or some applications of some embodiments, at least one of the plurality of individual layers or the structures needs to be machined after it is attached to a receiver such as a substrate or an another layer or structure.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: October 25, 2011
    Inventor: Gang Zhang
  • Patent number: 8022501
    Abstract: The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a device isolation layer selectively and partially filled into the plurality of micro trenches.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: September 20, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung-Ho Pyi
  • Patent number: 8022485
    Abstract: A semiconductor device having reduced input capacitance is disclosed. The semiconductor device includes a pedestal region having a gate overlying a sidewall of the pedestal region and gate interconnect overlying a major surface of the pedestal region. The pedestal region includes a conductive shield layer (260). The conductive shield layer (260) is isolated from the gate of the transistor by more than one dielectric layer (330, 340, and 350) to reduce input capacitance. The pedestal region includes an air gap region (1525) to further lower the dielectric constant of the pedestal region between the gate/gate interconnect and the conductive shield layer (260).
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: September 20, 2011
    Assignee: HVVi Semiconductors, Inc.
    Inventor: Robert Bruce Davies
  • Patent number: 7985977
    Abstract: Briefly, in accordance with one or more embodiments, a dielectric platform is at least partially formed in a semiconductor substrate and extending at least partially below a surface of a semiconductor substrate. The dielectric platform may include structural pillars formed by backfilling a first plurality of cavities etched in the substrate, and a second plurality of cavities formed by etching away sacrificial pillars disposed between the structural pillars. The second plurality of cavities may be capped to hermetically seal the second plurality of cavities to impart the dielectric constant of the material contained therein, for example air, to the characteristic dielectric constant of the dielectric platform. Alternatively, the second plurality of cavities may be backfilled with a material having a lower dielectric constant than the substrate, for example silicon dioxide where the substrate comprises silicon.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: July 26, 2011
    Assignee: HVVi Semiconductors, Inc.
    Inventors: Bishnu Prasanna Gogoi, David William Wolfert, Jr.
  • Patent number: 7947566
    Abstract: A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a plurality of lateral void gap isolation regions for isolating portions of each of the semiconductor layers from portions of the other semiconductor layers.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: May 24, 2011
    Assignee: International Business Machines Corporation
    Inventors: Howard Hao Chen, Louis Lu-Chen Hsu, Jack Allan Mandelman
  • Patent number: 7892943
    Abstract: A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: February 22, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Michael Violette
  • Patent number: 7868335
    Abstract: A bipolar junction transistor having an emitter, a base, and a collector includes a stack of one or more layer sets adjacent the collector. Each layer set includes a first material having a first band gap, wherein the first material is highly doped, and a second material having a second band gap narrower than the first band gap, wherein the second material is at most lightly doped.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: January 11, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: James Chingwei Li, Marko Sokolich, Tahir Hussain, David H. Chow
  • Patent number: 7846806
    Abstract: A system and method are disclosed for providing a self aligned silicon germanium (SiGe) heterojunction bipolar transistor using a mesa emitter-base architecture. The transistor of the present invention comprises a non-selective epitaxial growth (NSEG) collector, an NSEG base, an NSEG emitter and a raised external base that is formed by the selective epitaxial growth (SEG) of a doped polysilicon layer.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: December 7, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Jamal Ramdani, Mingwei Xu
  • Patent number: 7829449
    Abstract: An electronic integrated circuit is fabricated by forming on a substrate, of which a part is composed of absorbing material, a portion made of a sacrificial material. The sacrificial material includes cobalt, nickel, titanium, tantalum, tungsten, molybdenum, gallium, indium, silver, gold, iron and/or chromium. A rigid portion is then formed in fixed contact with the substrate, on one side of the portion of sacrificial material opposite to the part of the substrate composed of absorbing material. The circuit is heated such that the sacrificial material is absorbed into the part of the substrate composed of absorbing material. A substantially empty volume is thus created in place of the portion of sacrificial material. The volume that is substantially empty can replace a dielectric material situated between the electrodes of a capacitor.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: November 9, 2010
    Assignees: STMicroelectronics (Crolles 2) SAS, Koninklijke Phillips Electronics N.V.
    Inventors: Christophe Regnier, Aurelie Humbert
  • Patent number: 7821014
    Abstract: A semiconductor device and a manufacturing method thereof uses a semiconductor substrate of silicon carbide. On one principal surface side of the substrate, at its central section, a layer of silicon carbide or gallium nitride as a semiconductor layer having the thickness at least necessary for breakdown voltage blocking is epitaxially grown or formed from part of the substrate. A recess is formed in the other principal surface side of substrate at a position facing the central section. A supporting section surrounds the bottom of the recess and provides the side face of the recess. The recess is formed by processing such as dry etching. The semiconductor device, even though the semiconductor substrate is made thinner for the realization of small on-resistance, can maintain the strength of the semiconductor substrate capable of reducing occurrence of a wafer cracking during the manufacturing process.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: October 26, 2010
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventors: Yoshiyuki Yonezawa, Daisuke Kishimoto
  • Patent number: 7759153
    Abstract: A method of manufacturing an electric field sensor having an electric field shield. The method includes providing a substrate doped with a first impurity; forming a resistive tip having a resistance region doped with a low concentration of a second impurity at an apex of a protruding portion of the substrate, and first and second semiconductor electrode regions doped with a high concentration of the second impurity on both slopes of the protruding portion with the resistive region therebetween, wherein the second impurity has a polarity opposite to that of the first impurity; forming a dielectric layer on the resistive tip; forming a mask having a high aspect ratio on the dielectric layer; depositing a metal layer on the dielectric layer; and exposing the dielectric layer formed on the resistance region through the metal layer by removing the mask.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: July 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul-min Park, Hyoung-soo Ko, Seung-bum Hong
  • Patent number: 7675054
    Abstract: Phase change memory devices and methods for fabricating the same are provided. A phase change memory device includes a first conductive electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer and electrically connected to the first conductive electrode. A space is disposed in the second dielectric layer to at least isolate a sidewall of the phase change material layer and the second dielectric layer adjacent thereto. A second conductive electrode is disposed in the second dielectric layer and electrically connected to the phase change material layer.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: March 9, 2010
    Assignees: Industrial Technology Research Institute, Powerchip Semiconductor Corp., Nanya Technology Corporation, ProMOS Technologies Inc., Winbond Electronics Corp.
    Inventor: Li-Shu Tu
  • Patent number: 7666754
    Abstract: A method for forming an air gap structure on a substrate is described. The method comprises forming a sacrificial layer on a substrate, wherein the sacrificial layer comprises a decomposable material that thermally decomposes at a thermal decomposition temperature above approximately 350 degrees C. Thereafter, a cap layer is formed on the sacrificial layer at a substrate temperature less than the thermal decomposition temperature of the sacrificial layer. The sacrificial layer is decomposed by performing a first exposure of the substrate to ultraviolet (UV) radiation and heating the substrate to a first temperature less than the thermal decomposition temperature of the sacrificial layer, and the decomposed sacrificial layer is removed through the cap layer. The cap layer is cured to cross-link the cap layer by performing a second exposure of the substrate to UV radiation and heating the substrate to a second temperature greater than the first temperature.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: February 23, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Dorel I. Toma, Junjun Liu
  • Patent number: 7553756
    Abstract: An object of the present invention is to prevent formation of a badly situated via metal in a Damascene wiring portion in multiple layers having an air-gap structure. In the present invention, a via is completely separated from an air-gap 45 by forming an interlayer insulating film 44 having the air-gap 45 between adjacent Damascene wiring portions after forming a sacrifice film pillar 42 from a selectively removable insulating film in a formation region of a connection hole. The present invention can provide multiple-layered buried wiring in which a high reliable via connection and a reduced parasitic capacitance due to the air-gap are achieved.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: June 30, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Hayashi, Takayuki Oshima, Hideo Aoki
  • Patent number: 7531444
    Abstract: A method of forming airgaps is provided where a blocking mask is applied to a substrate to shield a portion of the substrate from a beam of energy. After irradiation, the blocking mask is removed and a capping material is applied to the substrate. Alternatively, the capping material may be applied before irradiation. The capping material is perforated to allow an etchant to pass therethrough to the substrate below the capping material. The exposed portions of the substrate are removed from underneath the capping material by etching. The capping material is then sealed leaving sealed airgaps within the substrate.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: May 12, 2009
    Assignee: International Business Machines Corporation
    Inventors: Christos D. Dimitrakopoulos, Daniel C. Edelstein, Vincent J. McGahay, Satyanarayana V. Nittta, Kevin S. Petrarca, Shom Ponoth, Shahab Siddiqui
  • Patent number: 7504699
    Abstract: A method of forming an air gap or gaps within solid structures and specifically semiconductor structures to reduce capacitive coupling between electrical elements such as metal lines, wherein a norbornene-type polymer is used as a sacrificial material to occupy a closed interior volume in a semiconductor structure. The sacrificial material is caused to decompose into one or more gaseous decomposition products which are removed, preferably by diffusion, through an overcoat layer. The decomposition of the sacrificial material leaves an air gap or gaps at the closed interior volume previously occupied by the norbornene-type polymer. The air gaps may be disposed between electrical leads to minimize capacitive coupling therebetween.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: March 17, 2009
    Assignee: George Tech Research Corporation
    Inventors: Paul A. Kohl, Qiang Zhao, Sue Ann Bidstrup Allen
  • Patent number: 7482261
    Abstract: A semiconductor interconnect structure is provided that includes a new capping layer/dielectric material interface which is embedded inside the dielectric material. In particular, the new interface is an air gap that is located in the upper surface of a dielectric material that is adjacent to a conductive region or feature. The air gap may be unfilled, partially filled or completely filled with either a dielectric capping layer or an upper dielectric material. The presence of the air gap in the upper surface of the dielectric material that is adjacent to the conductive region or feature provides a new interface that has a high mechanical strength and thus the resultant structure is highly reliable. Moreover, the new interface provided in the present invention has a high dielectric breakdown resistance which is important for future technology extendibility.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: January 27, 2009
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 7462547
    Abstract: A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: December 9, 2008
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Akatsu, Rama Divakaruni, Marwan Khater, Christopher M. Schnabel, William Tonti
  • Patent number: 7396757
    Abstract: An interconnect structure with improved performance and capacitance by providing air gaps inside the dielectric layer by use of a multi-phase photoresist material. The interconnect features are embedded in a dielectric layer having a columnar air gap structure in a portion of the dielectric layer surrounding the interconnect features. The interconnect features may also be embedded in a dielectric layer having two or more phases with a different dielectric constant created. The interconnect structure is compatible with current back end of line processing.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: July 8, 2008
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Publication number: 20080099799
    Abstract: A semiconductor process is taught for performing electroless plating of copper overlying at least a portion of a layer comprising cobalt, nickel, or both cobalt and nickel. The cobalt and/or nickel comprising layer may be formed using electroless plating. For some embodiments, a tin layer is then formed overlying the copper. The tin layer may be formed using immersion plating or electroless plating. A micropad may comprise the cobalt and/or nickel comprising layer and the copper layer. In some embodiments, the micropad may also comprise the tin layer. In one embodiment, the micropad may be compressed at an elevated temperature to form a copper tin intermetallic compound which provides an interconnect between a plurality of semiconductor devices.
    Type: Application
    Filed: October 25, 2006
    Publication date: May 1, 2008
    Inventors: Varughese Mathew, Eddie Acosta, Ritwik Chatterjee, Sam S. Garcia
  • Patent number: 7358179
    Abstract: After a HEMT is formed, side walls are formed on a semiconductor substrate. Next, a sacrificial layer is formed to cover the HEMT. Next, contact holes are formed in the sacrificial layer to expose upper surfaces of source electrodes. Next, a metal interconnect line is formed by patterning a metal film formed on the entire top surface. Next, slits are formed in the metal interconnect line to partially expose an upper surface of the sacrificial layer. After the sacrificial layer is dissolved, the dissolved sacrificial layer is discharged through the slits to the outside. An air space is formed as a result of the removal of the sacrificial layer.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: April 15, 2008
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Ogawa, Toshiaki Kitano, Hiroyuki Minami
  • Patent number: 7214594
    Abstract: A method and apparatus are provided an interconnect cladding layer. In one embodiment, a first sacrificial layer is deposited over a substrate and patterned. In the vias created during the patterning operation, a conductive material is placed to create conductive interconnects. After planarizing the conductive material, the sacrificial layer is removed leaving the interconnect exposed. A cladding layer is then deposited over the conductive material.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: May 8, 2007
    Assignee: Intel Corporation
    Inventors: Lawrence D. Wong, Jihperng Leu, Grant Kloster, Andrew Ott, Patrick Morrow
  • Patent number: 7138329
    Abstract: An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with a tungsten plug process. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: November 21, 2006
    Assignee: United Microelectronics Corporation
    Inventors: Water Lur, David Lee, Kuang-Chih Wang, Ming-Sheng Yang
  • Patent number: 7112866
    Abstract: The invention provides a new multilevel interconnect structure of air gaps in a layer of IMD. A first layer of dielectric is provided over a surface; the surface contains metal points of contact. Trenches are provided in this first layer of dielectric. The trenches are filled with a first layer of nitride or disposable solid and polished. A second layer of dielectric is deposited over the first layer of dielectric. Trenches are formed in the second layer of dielectric, a second layer of nitride or disposable solid is deposited over the second layer of dielectric. The layer of nitride or disposable solid is polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. The thin layer of oxide is masked and etched thereby creating openings in this thin layer of oxide, these openings align with the points of intersect of the trenches in the first layer of dielectric and in the second layer of dielectric. The nitride or removable solid is removed from the trenches.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: September 26, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Lap Chan, Cher Liang Cha, Kheng Chok Tee
  • Patent number: 7094669
    Abstract: A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: August 22, 2006
    Assignee: Chartered Semiconductor Manufacturing LTD
    Inventors: Xiaomei Bu, Alex See, Tae Jong Lee, Fan Zhang, Yeon Kheng Lim, Liang Choo Hsia
  • Patent number: 6998695
    Abstract: A method of manufacturing a semiconductor device has the steps of: forming a mushroom gate traversing an active region of a semiconductor substrate and having a fine gate and an expanded over gate formed thereon; coating a first organic material film on the semiconductor substrate; patterning the first organic material film and leaving the first organic material film only near the mushroom gate; coating a second organic (insulating) material film covering the left first organic material film; forming an opening through the second organic material film to expose the first organic material film; and dissolving and removing the first organic material film via the opening to form a hollow space in the second organic material film.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: February 14, 2006
    Assignees: Fujitsu Limited, Eudyna Devices Inc.
    Inventors: Kozo Makiyama, Tsuyoshi Takahashi, Masahiro Nishi
  • Patent number: 6964907
    Abstract: In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a <110> direction of a <100> orientation wafer.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: November 15, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Alexei Sadovnikov, Vladislav Vashchenko, Peter Johnson
  • Patent number: 6946355
    Abstract: A hetero-bipolar transistor on Ga—As basis which has an advantageous design and to a method for producing the same which allows production of inexpensive and long-term stable components.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: September 20, 2005
    Assignee: United Monolithic Semiconductors GmbH
    Inventor: Dag Behammer
  • Patent number: 6924203
    Abstract: A heterojunction bipolar transistor (HBT) device structure is provided which facilitates the reduction of the base-collector capacitance and a method for making the same. The base-collector capacitance is decreased by fabricating a base micro-bridge connecting a base contact to a base mesa on the HBT. The base micro-bridge is oriented along about one of 001, 010, 00{overscore (1)}, and 0{overscore (1)}0 direction to a major flat of the wafer. The HBT device employs a phosphorous based collector material. During removal of the phosphorous based collector material, the base layer is undercut forming the micro-bridge, successfully removing the collector and sub-collector material below the bridge due to the orientation of the micro-bridge. The removal of collector and sub-collector material reduces the base-collector junction area, and therefore reduce the base-collector junction capacitance.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: August 2, 2005
    Assignee: Northrop Grumman Corporation
    Inventors: Donald James Sawdai, Gregory Scott Leslie, Augusto Gutierrez-Aitken
  • Patent number: 6924201
    Abstract: A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: August 2, 2005
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Masahiro Tanomura, Hidenori Shimawaki, Yosuke Miyoshi, Fumio Harima
  • Patent number: 6905929
    Abstract: Leakage of a single-poly EPROM cell is prevented by eliminating field oxide isolating the source, channel, and drain from the control gate n-well, and by replacing field oxide surrounding the cell with a heavily doped surface isolation region. The EPROM cell also utilizes a floating gate having an open-rectangular floating gate portion over the control gate region, and a narrow floating gate portion over the channel and intervening silicon substrate. The surface area of the open-rectangular floating gate portion ensures a high coupling ratio with the control gate region. The small width of the narrow floating gate portion prevents formation of a sizeable leakage path between the n-well and the source, channel, and drain. To conserve surface area, the EPROM cell also eliminates the p+ contact region and the PLDD region in the control gate well of the conventional EPROM design.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: June 14, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Richard B. Merrill, Albert Bergemont, Min-hwa Chi
  • Patent number: 6890828
    Abstract: A method for forming interlevel dielectric levels in a multilevel interconnect structure formed by a damascene process. The conductive features characteristic of the damascene process are formed in a removable mandrel material for each level of the interconnect structure. In at least one level, a portion of the mandrel material underlying the bond pad is clad on all sides with the metal forming the conductive features to define a support pillar. After all levels of the interconnect structure are formed, the mandrel material surrounding the conductive features is removed to leave air-filled voids that operate as an interlevel dielectric. The support pillar is impermeable to the etchant such that mandrel material and metal inside the support pillar is retained. The support pillar braces the bond pad against vertical mechanical forces applied by, for example, probing or wire bonding and thereby reduces the likelihood of related damage to the interconnect structure.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: May 10, 2005
    Assignee: International Business Machines Corporation
    Inventors: David Vaclav Horak, Charles William Koburger, III, Peter H. Mitchell, Larry Alan Nesbit
  • Patent number: 6867079
    Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: March 15, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Atsushi Kurokawa, Toshiaki Kitahara, Hiroshi Inagawa, Yoshinori Imamura
  • Publication number: 20040256663
    Abstract: A memory cell includes first and second data holding portions for holding stored data and its inverted data. First and second p channel TFT compensate for charges leaked from first and second capacitors, respectively. A first (second) access transistor has first and second gate electrodes connected to a first (second) word line and to a second (first) node, respectively. The first (second) access transistor discharges the charges leaked from a power supply node via the first (second) p channel TFT in the OFF state in the leakage mode where the first (second) word line is inactivated and the second (first) node is at an H level.
    Type: Application
    Filed: June 16, 2004
    Publication date: December 23, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Yuji Kihara
  • Publication number: 20040175895
    Abstract: The invention relates to a hetero-bipolar transistor on Ga—As basis which has an advantageous design and to a method for producing the same which allows production of inexpensive and long-term stable components.
    Type: Application
    Filed: February 10, 2004
    Publication date: September 9, 2004
    Inventor: Dag Behammer
  • Publication number: 20040175896
    Abstract: A new method is provided for creating air gaps in a layer of IMD. A first layer of dielectric is deposited over a surface; the surface contains metal points of contact. Trenches are etched in this first layer of dielectric. The trenches are filled with a first layer of nitride or disposable solid and polished. A second layer of dielectric is deposited over the first layer of dielectric. Trenches are formed in the second layer of dielectric, a second layer of nitride or disposable solid is deposited over the second layer of dielectric. The layer of nitride or disposable solid is polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. The thin layer of oxide is masked and etched thereby creating openings in this thin layer of oxide, these openings align with the points of intersect of the trenches in the first layer of dielectric and in the second layer of dielectric. The nitride or removable solid is removed from the trenches.
    Type: Application
    Filed: March 9, 2004
    Publication date: September 9, 2004
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Lap Chan, Cher Liang Cha, Kheng Chok Tee