Abstract: A method of forming an electronic fuse including providing an Mx level including a first Mx metal, a second Mx metal, and an Mx cap dielectric above of the first and second Mx metal, forming an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via electrically connecting the second Mx metal to the Mx+1 metal in a vertical orientation, and forming a nano-pillar from the Mx cap dielectric at a bottom of the via and above the second Mx metal, the nano-pillar having a height less than a height of the via.

Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

Abstract: In one general aspect, an apparatus can include a semiconductor substrate, and a first conductive fuse bus having a triangular-shaped portion with a bottom surface aligned along a plane substantially parallel to a surface of the semiconductor substrate. The apparatus can include a second conductive fuse bus having a bottom surface aligned along the plane, and a plurality of fuse links coupled between the triangular-shaped portion of the first conductive fuse bus and the second conductive fuse bus.

Abstract: An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.

Abstract: An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.

Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

Abstract: An embodiment is a fuse structure. In accordance with an embodiment, a fuse structure comprises an anode, a cathode, a fuse link interposed between the anode and the cathode, and cathode connectors coupled to the cathode. The cathode connectors are each equivalent to or larger than about two times a minimum feature size of a contact that couples to an active device.

Abstract: A fabrication method for fabricating an electrically programmable fuse method includes depositing a polysilicon layer on a substrate, patterning an anode contact region, a cathode contact region and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, depositing a silicide layer on the polysilicon layer, and forming a plurality of anisometric contacts on the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.

Abstract: A fuse part of a semiconductor device includes an insulation layer over a substrate, and a fuse over the insulation layer, wherein the fuse includes a plurality of blowing pads for irradiating a laser beam and the plurality of blowing pads have laser coordinates different from one another.

Abstract: Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure.

Abstract: In a replacement gate approach, the semiconductor material of the gate electrode structures may be efficiently removed during a wet chemical etch process, while this material may be substantially preserved in electronic fuses. Consequently, well-established semiconductor-based electronic fuses may be used instead of requiring sophisticated metal-based fuse structures. The etch selectivity of the semiconductor material may be modified on the basis of ion implantation or electron bombardment.

Abstract: Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure.

Abstract: A semiconductor device includes an electric fuse formed on a substrate. The electric fuse includes: a first interconnect formed on one end side thereof; a second interconnect formed in a layer different from a layer in which the first interconnect is formed; a first via provided in contact with the first interconnect and the second interconnect to connect those interconnects; a third interconnect formed on another end side thereof, the third interconnect being formed in the same layer in which the first interconnect is formed, as being separated from the first interconnect; and a second via provided in contact with the third interconnect and the second interconnect to connect those interconnects, the second via being lower in resistance than the first via. The electric fuse is disconnected by a flowing-out portion to be formed of a conductive material forming the electric fuse which flows outwardly during disconnection.

Abstract: In sophisticated integrated circuits, an electronic fuse may be formed such that an increased sensitivity to electromigration may be accomplished by including at least one region of increased current density. This may be accomplished by forming a corresponding fuse region as a non-linear configuration, wherein at corresponding connection portions of linear segments, the desired enhanced current crowding may occur during the application of the programming voltage. Hence, increased reliability and more space-efficient layout of the electronic fuses may be accomplished.

Abstract: A semiconductor device includes an electric fuse formed on a semiconductor substrate and composed of an electric conductor. The electric fuse includes an upper layer interconnect, a via coupled to the upper interconnect and a lower layer interconnect coupled to the via, which are formed in different layers, respectively, in a condition before cutting the electric fuse, and wherein the electric fuse includes a flowing-out region formed of the electric conductor being flowed toward outside from the second interconnect and a void region formed between the first interconnect and the via or in the via, in a condition after cutting the electric fuse.

Abstract: A fuse element is laminated on a resistor and the resistor is formed in a concave shape below a region in which cutting of the fuse element is carried out with a laser. Accordingly, there can be provided a semiconductor device which occupies a small area, causes no damage on the resistor in the cutting of the fuse element, has a small contact resistance occurred between elements, and has stable characteristics, and a method of manufacturing the same.

Abstract: An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.

Abstract: A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer.

Abstract: A semiconductor power device is formed on a semiconductor substrate. The semiconductor power device includes a plurality of transistor cells distributed over different areas having varying amount of ballasting resistances depending on a local thermal dissipation in each of the different areas. An exemplary embodiment has the transistor cells with a lower ballasting resistance formed near a peripheral area and the transistor cells having a higher ballasting resistance are formed near a bond pad area. Another exemplary embodiment comprises cells with a highest ballasting resistance formed in an area around a wire-bonding pad, the transistor cells having a lower resistance are formed underneath the wire-bonding pad connected to bonding wires for dissipating heat and the transistor cells having a lowest ballasting resistance are formed in an areas away from the bonding pad.

Abstract: A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern.

Abstract: The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the links contacts the electrically conductive plate as a separate region relative to the other links, and the region where a link makes contact to the electrically conductive plate is a fuse. The invention also includes methods of forming semiconductor fuse arrangements.

Abstract: An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.

Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.

Abstract: An electrostatic discharge (ESD) protection clamp (21, 21?, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21?, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (?Vt1)MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21?, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.

Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.

Abstract: An electronic fuse (“E-fuse”) has a silicide filament link extending along a gap between polysilicon structures formed on a silicon substrate. The silicide filament link extends across diffusions formed in the gap. A P-N junction between terminals of the E-fuse provides high resistivity after programming (fusing) the silicide filament link.

Abstract: A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protective film which is formed on the metal wiring layer and the layer insulating film; and an organic insulating protective film which is formed on the inorganic insulating protective film. An opening is formed in the organic insulating protective film so that the inorganic insulating protective on the fuse portion is exposed. According to this configuration, it is not required to etch away the layer insulating film in order to form an opening above the fuse portion. Therefore, the time period required for forming the opening can be shortened and the whole production time period can be shortened.

Abstract: A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing compressive stress liner material over the fuse material, and patterning the compressive stress liner material.

Abstract: An upper electrode of a capacitor has a two-layer structure of first and second upper electrodes. A gate electrode of a MOS field effect transistor and a fuse are formed by patterning conductive layers used to form the lower electrode, first upper electrode and second upper electrode of the capacitor. In forming a capacitor and a fuse on a semiconductor substrate by a conventional method, at least three etching masks are selectively used to pattern respective layers to form the capacitor and fuse before wiring connection. The number of etching masks can be reduced in manufacturing a semiconductor device having capacitors, fuses and MOS field effect transistors so that the number of processes can be reduced and it becomes easy to improve the productivity and reduce the manufacture cost.

Abstract: A disclosed method of producing a semiconductor device includes the steps of (A) forming a gate electrode and a trimming fuse on a semiconductor substrate; (B) forming a side wall insulating film covering the gate electrode and the trimming fuse; (C) forming a conductive film on the side wall insulating film and patterning the conductive film to form an etching stop layer and a resistance element; (D) forming a side wall on the sides of the gate electrode; (E) repeating, one or more times, sub-steps of forming an interlayer insulating film and of forming an upper wiring layer, and then forming a passivation film; (F) removing the passivation film and the interlayer insulating film in the trimming opening forming area until the etching stop layer is exposed; and (G) forming the trimming opening by removing the etching stop layer in the trimming opening forming area.

Abstract: Fuses for integrated circuits and semiconductor devices and methods for using the same. The semiconductor fuse contains two conductive layers, an overlying and underlying refractory metal nitride layer, on an insulating substrate. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure including the same materials. The fuse, which may be used to program redundant circuitry, may be blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: An upper electrode of a capacitor has a two-layer structure of first and second upper electrodes. A gate electrode of a MOS field effect transistor and a fuse are formed by patterning conductive layers used to form the lower electrode, first upper electrode and second upper electrode of the capacitor. In forming a capacitor and a fuse on a semiconductor substrate by a conventional method, at least three etching masks are selectively used to pattern respective layers to form the capacitor and fuse before wiring connection. The number of etching masks can be reduced in manufacturing a semiconductor device having capacitors, fuses and MOS field effect transistors so that the number of processes can be reduced and it becomes easy to improve the productivity and reduce the manufacture cost.

Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.

Abstract: The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the links contacts the electrically conductive plate as a separate region relative to the other links, and the region where a link makes contact to the electrically conductive plate is a fuse. The invention also includes methods of forming semiconductor fuse arrangements.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least one via.

Abstract: A method of forming a fuse region in a semiconductor damascene process in which a specific layer is formed to prevent corrosion and re-connection of a severed part of the fuse region to prevent malfunction. A first conductive layer is formed over a substrate and an interlayer dielectric layer is deposited over the first conductive layer. A second conductive layer is buried in the interlayer dielectric layer by a dual damascene process to simultaneously form an interconnection and a fuse. The resultant structure is coated with a passivation layer. The fuse is cut to form a severed portion. A selective metal layer is deposited over the severed portion.

Abstract: Electrostatic discharge (ESD) protection is provided for an integrated circuit. Snap back from a lower initial critical voltage and critical current is provided, as compared to contemporary designs. A dynamic region having doped regions is formed on a substrate, interconnects contacting the dynamic region. The dynamic region includes an Nwell region, a Pwell region and shallow diffusions, defining a PNP region, an NPN region and a voltage Breakdown region. In an aspect, the Nwell region includes a first N+ contact, a first P+ contact and an N+ doped enhancement, while the Pwell region includes a second N+ contact, a second P+ contact and a P+ doped enhancement. The N+ doped enhancement contacts the P+ doped enhancement forming the breakdown voltage region therebetween, in one case forming a buried breakdown voltage junction.

Abstract: Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.

Abstract: A method for reducing the scrap rate of fuse structures after laser repairing is provided. The method includes providing a semiconductor wafer comprising integrated circuits, performing a yield test on the semiconductor wafer to determine defective circuits, predetermining a wavelength limit, and keeping the semiconductor wafer away from lights having wavelengths lower than the wavelength limit. The defects on the semiconductors wafer are repaired by burning laser fuses. For copper-based fuse structures, the wavelength limit is about 550 nm.

Abstract: A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process.

Abstract: A redundant fuse is provided with a redundant length, here a winding structure, at one end thereof, here at a vicinity of a second wire side to which a high voltage (Vcc) is impressed. A disconnected portion is provided between the other end side of the redundant fuse, here a second wire side which is on the ground potential (GND) and the winding structure.

Abstract: A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.

Abstract: A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse element is constructed with a rectangular-shaped contact. The contact is made long enough so that it makes contact at each end with a metal layer, but design rule spacing is still maintained between the connections with the metal layer. The overlapping areas between the rectangular contact and the metal layers are asymmetrical. Alternatively, these overlapping areas are smaller than the design rule overlap requirements. In a second embodiment, a fuse element is constructed with a plurality of rectangular-shaped contacts. As a result, a current value that is significantly lower than conventional fuse current values, can be used to melt such a contact or blow the fuse.

Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.

Abstract: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.

Abstract: A semiconductor structure including at least one e-fuse embedded within a trench that is located in a semiconductor substrate (bulk or semiconductor-on-insulator) is provided. In accordance with the present invention, the e-fuse is in electrical contact with a dopant region that is located within the semiconductor substrate. The present invention also provides a method of fabricating such a semiconductor structure in which the embedded e-fuse is formed substantially at the same time with the trench isolation regions.

Abstract: A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is preferably a material that minimizes stresses on the crystalline body, such as an oxide. The body may be doped, and may also include a silicide layer on the upper surface. This fuse structure may be successfully programmed over a wide range of programming voltages and time.

Abstract: In a fuse region of a semiconductor device, and a method of fabricating the same, the fuse region includes an interlayer insulating layer on a semiconductor substrate, a plurality of fuses on the interlayer insulating layer disposed in parallel with each other, a blocking layer on the interlayer insulating layer between each of the plurality of fuses and in parallel with the plurality of fuses, and a plurality of fuse grooves recessed into the interlayer insulating layer between each of the plurality of fuses and the blocking layer.

Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film supported by a semiconductor substrate, forming an aluminum layer supported by the first insulating film, etching the aluminum layer to form a bonding pad and fuse elements, depositing by plasma chemical vapor deposition a second insulating film covering the bonding pad and the fuse elements, the second insulating film having planar portions between the fuse elements and ridged portions opposite the fuse elements, depositing by plasma chemical vapor deposition a third insulating film covering the second insulating film, etching the third insulating film to form a first hole exposing a first region of the second insulating film, opposite the fuse elements, and a second hole exposing a second region of the second insulating film, opposite at least part of said bonding pad, and etching the second insulating film to form a third hole exposing at least part of the bonding pad.

Abstract: A semiconductor device comprises a multiple insulation layer structure in which multiple insulation layers each having interconnection layer are built up and either one of the interconnection layer forming a fuse is blown in order to select a spare cell to relieve a defective cell; and an opening area corresponding to said fuse, the opening being formed on one or more insulation layers disposed above the layer which includes the fuse, wherein a side wall position corresponding to the opening of the first protective insulation film formed on the top layer of the multiple layers and a side wall position corresponding to the opening of the second protective insulation film formed on the first protective insulation film are continuous at the boundary thereof.