Abstract: Methods for depositing rhenium-containing thin films on a substrate are described. The substrate is exposed to a rhenium precursor and a reducing agent to form the rhenium-containing film (e.g., metallic rhenium, rhenium nitride, rhenium oxide, rhenium carbide). The exposures can be sequential or simultaneous. The rhenium-precursors are substantially free of halogen.

Abstract: A thermal transfer method includes a step of forming a donor member having a base layer, a light-to-heat conversion layer disposed on the base layer, an intermediate layer disposed on the light-to-heat conversion layer, an organic transfer layer disposed on the intermediate layer, and a first protecting film disposed over the base layer and contacting at least one edge of the base layer, irradiating a first laser onto the donor member to form a preliminary organic layer on the display substrate, forming a pressing member having a second protecting film and a third protecting film disposed over the second protecting film and contacting at least one edge of the second protecting film, disposing the display substrate within a space formed by the second protecting film and the third protecting film, and irradiating a second laser onto the pressing member to change the preliminary organic layer to an organic layer.

Abstract: A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.

Abstract: Methods and apparatus teach a substrate wafer having a plurality of plugs configured there within. The method also includes depositing and patterning a layer of a second metallic material over the substrate wafer, providing a layer of a dielectric material of a predetermined thickness over the patterned layer of the second metallic material, and conducting chemical mechanical polishing of the layer of the dielectric material to form a planarized top surface while exposing the patterned layer of the second metallic material. The method further includes cleaning the planarized top surface, depositing and patterning a resistor film over the planarized top surface, depositing one or more blanket films over the patterned resistor film, and patterning and etching the one or more blanket films. Further disclosed are planar heater structures and additional methods for fabricating the planar heater structures.

Abstract: A production method for producing a semiconductor device capable of improving surface flatness and suppressing a variation in electrical characteristics of the semiconductor chip, and improving production yield. The production method includes the steps of: forming a first insulating film on a semiconductor substrate and on a conductive pattern film formed on the semiconductor substrate and reducing a thickness of the first insulating film in a region where the conductive pattern film is arranged by patterning; forming a second insulating film and polishing the second insulating film, thereby forming a flattening film; implanting a substance for cleavage into the semiconductor substrate through the flattening film, thereby forming a cleavage layer; transferring the semiconductor chip onto a substrate with an insulating surface so that the chip surface on the side opposite to the semiconductor substrate is attached thereto; and separating the semiconductor substrate from the cleavage layer.

Abstract: One or more embodiments relate to a method of forming a semiconductor device, including: providing a substrate; forming a gate stack over the substrate, the gate stack including a control gate over a charge storage layer; forming a conductive layer over the gate stack; etching the conductive layer to remove a portion of the conductive layer; and forming a select gate, the forming the select gate comprising etching a remaining portion of the conductive layer.

Abstract: Provided is a semiconductor device including: a silicon substrate; at least two trenches spaced apart from each other, being in parallel with each other, and being formed by vertically etching the silicon substrate from a surface thereof; an electrically insulating film for burying therein at least bottom surfaces of the trenches; a base region formed in a region of the silicon substrate located between the two trenches; and an emitter region and a collector region formed on portions of side surfaces of the trenches, respectively, the portions of the sides located above the insulating film and formed in the base region.

Abstract: A thin film transistor (TFT) and a method of manufacturing the same are provided. The TFT includes a transparent substrate, an insulating layer on a region of the transparent substrate, a monocrystalline silicon layer, which includes source, drain, and channel regions, on the insulating layer and a gate insulating film and a gate electrode on the channel region of the monocrystalline silicon layer.

Abstract: A method of cleaning a patterning device, the patterning device having at least organic coating material (OLED material) deposited thereon, where the method includes the step of providing a cleaning plasma for removing the coating material from the patterning device by means of a plasma etching process. During the step of removing the coating material from the patterning device, the temperature of the patterning device does not exceed a critical temperature causing damage to the patterning device, while maintaining a plasma etching rate of at least 0.2 ?m/min. In order to generate a pulsed cleaning plasma, pulsed energy is provided. The method can be carried out in a direct plasma etching process or in a remote plasma etching process. Different etching processes may be combined or carried out subsequently.

Abstract: An LED structure includes a first substrate; an adhering layer formed on the first substrate; first ohmic contact layers formed on the adhering layer; epi-layers formed on the first ohmic contact layers; a first isolation layer covering the first ohmic contact layers and the epi-layers at exposed surfaces thereof; and first electrically conducting plates and second electrically conducting plates, both formed in the first isolation layer and electrically connected to the first ohmic contact layers and the epi-layers, respectively. The trenches allow the LED structure to facilitate complex serial/parallel connection so as to achieve easy and various applications of the LED structure in the form of single structures under a high-voltage environment.

Abstract: A process for producing a base connection of a bipolar transistor is provided. The process includes the steps of providing a semiconductor structure that can include a three-dimensional sacrificial structure that is selectively removable with respect to adjacent regions. A first semiconductor layer and a second layer of dielectric material is deposited. The first semiconductor layer is partially exposed by partial removal of the second layer. A first reaction layer is deposited that, together with the first semiconductor layer forms reaction products, which are selectively removable with respect to adjacent regions. Remaining material of the first reaction layer that has not reacted with the material of the first semiconductor layer is removed. A second reaction layer is deposited that, with the first semiconductor layer, forms a low-resistivity compound. Remaining material of the second reaction layer that has not reacted with the material of the first semiconductor layer is removed.

Abstract: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.

Abstract: A semiconductor layer (10) provided on a BOX (buried oxide) layer (2) includes a first P-type region (11), an N+-type region (12), and an N−type region (13) which together form a diode. A plurality of second P-type regions (14) are provided on a bottom part of the semiconductor layer (10). A plurality of insulating oxide films (21) are interposed between the plurality of second P-type regions (14). When the diode is in a reverse-biased state, the second P-type region (14) directly below the N+-type region (12) is approximately the same in potential as the N+-type region (12). The second P-type region (14) will be lower in potential relative to this second P-type region (14) directly below the N+-type region (12), as the second P-type region (14) gets nearer to the first P-type region (11). Electric field concentration can thus be relaxed at an interface between the semiconductor layer (10) and the BOX layer (2), whereby improvement in breakdown voltage of the diode is realized.

Abstract: A semiconductor wafer structure having a device layer, an insulating layer, and a substrate which is capable of supporting increased semiconductor device densities or increased semiconductor device power. One or more of the layers includes an isotopically enriched semiconductor material having a higher thermal conductivity than semiconductor material having naturally occurring isotopic ratios. The insulating layer may be formed by implanting atoms or ions into a semiconductor layer and subjecting the wafer to heat treatment resulting in the implanted atoms or ions reacting with the semiconductor layer to form an insulating layer.

Abstract: The present invention provides a method for producing semiconductor device having a planarized structure wherein elevational disparities are removed. The semiconductor is produced by forming insulation layer on the transistor device, coating the photo resist layer on the insulator layer, carrying out patterning so that the contact region is opened, forming the region on which the metal is mounted by removing the insulation layer of the contact region, depositing the electrode metal, and removing the photo resist layer by lift-off process.

Abstract: An electrostatic discharge (ESD) protection device for a silicon-on-insulator (SOI) integrated circuit having a silicon substrate with a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer having active regions defined by isolation trenches. The ESD protection device is formed on the SOI integrated circuit and has an anode and a cathode formed within one of the active regions and coupled respectively to a first and a second node; and a backside contact plug adjacent and in thermal contact with at least one of the anode or the cathode, the backside contact plug traversing the buried oxide layer to thermally couple the one of the active regions and the substrate.

Abstract: A writing tablet may be covered with a thermochromic writing surface so that the user may temporarily mark on the writing surface by changing its temperature. In one embodiment, the writing surface may be positioned over a processor-based device. The processor-based device, using a touch screen, for example, may detect the writing on the writing surface and may receive that writing as a touch screen input.

Abstract: A method for growing films on substrates using sequentially pulsed precursors and reactants, system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method.

Abstract: A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the sidewalls of the gate conductor. Extension regions are provided in the substrate which extend under the spacer and the gate conductor. Source and drain diffusion regions are implanted into the substrate adjacent to the extension regions. The disposable part of the spacer is then removed to expose a portion of the extension region. A metal layer is formed at least in the extension regions, resulting in the Schottky contact.

Abstract: An FET device and method of making comprising a first dielectric layer; a substrate layer on the dielectric layer; a channel region of a first conductivity type formed in the substrate layer; a gate formed above the substrate layer over the channel region; FET diffusion regions of a second conductivity type formed in the substrate layer, the diffusion regions each having edges, the edges of the FET diffusion regions being separated by the channel region; and a body contact region of the first conductivity type extending continuously from the channel region. The first conductivity type material in the body contact region is thinner than the first conductivity type material in the channel region. The FET also includes a second dielectric layer formed on the body contact region.

Abstract: A method for producing a semiconductor device including a bipolar transistor, has the steps of: forming an element isolating region in a major surface of a semiconductor substrate to define an element forming region to form a collector region in the element forming region surrounded by the element isolating region; allowing the epitaxial growth of a semiconductor layer on the major surface of the semiconductor substrate to form a base region of the semiconductor layer on the collector region; forming a growth inhibiting film on a region forming the base region of the semiconductor layer; removing the growth inhibiting film to expose a part of the semiconductor layer; covering the upper surface and side wall of the conductive film, which is exposed in the predetermined region, with an insulator film; covering the side wall of the conductive film, which is exposed in the predetermined region; and forming an emitter region in a surface region of the predetermined region of the semiconductor layer, which is surro

Abstract: A deposited film formation method comprises the steps of:(a) feeding a gas of an organometallic compound containing molybdenum atom and hydrogen gas onto a substrate having an electron donative surface; and(b) maintaining the temperature of the electron donative surface within the range of the decomposition temperature of the organometallic compound or lower and 800.degree. C. or lower to form a molybdenum film on the electron donative surface.

Abstract: A method for producing an electronic component with a plurality of layers fabricating in a laminated composite, comprising laterally structuring at least one of the layers having a p or n conductivity characteristic by forming one of the layers in a sieve shape with a multiplicity of openings therein on a second layer of a different p or n conductivity characteristic than that of the one of the layers so that a space charge zone is formed in the second of the layers at boundaries of the one of the layers along the openings in the one of the layers.

Abstract: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.