Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT.

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device.

Abstract: Lateral PNP bipolar junction transistors, methods for fabricating lateral PNP bipolar junction transistors, and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base.

Abstract: Some embodiments include methods of forming BJTs. A first type doped region is formed within semiconductor material. First and second trenches are formed within the semiconductor material to pattern an array of pedestals, and the trenches are filled with electrically insulative material. An upper portion of the first type doped region is counter-doped to form a first stack having a second type doped region over a first type doped region, and an upper portion of the first stack is then counter-doped to form a second stack having a second type doped region between a pair of first type doped regions. Some embodiments include a BJT array. A base implant region is between a pair of emitter/collector implant regions. Electrically insulative material is adjacent the base implant region, and contains at least about 7×1016 atoms/cm3 of base implant region dopant.

Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.

Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

Abstract: Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance Cbc. In the embodiments, a collector region is positioned laterally adjacent to a trench isolation region within a substrate. Mask layer(s) cover the trench isolation region and further extend laterally onto the edge portion of the collector region. A first section of an intrinsic base layer is positioned above a center portion of the collector region and a second section of the intrinsic base layer is positioned above the mask layer(s). During processing these mask layer(s) prevent divot formation in the upper corner of the trench isolation region at the isolation region-collector region interface and further limit dopant diffusion from a subsequently formed raised extrinsic base layer into the collector region.

Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.

Abstract: Some embodiments include methods of forming BJTs. A first type doped region is formed within semiconductor material. First and second trenches are formed within the semiconductor material to pattern an array of pedestals, and the trenches are filled with electrically insulative material. An upper portion of the first type doped region is counter-doped to form a first stack having a second type doped region over a first type doped region, and an upper portion of the first stack is then counter-doped to form a second stack having a second type doped region between a pair of first type doped regions. Some embodiments include a BJT array. A base implant region is between a pair of emitter/collector implant regions. Electrically insulative material is adjacent the base implant region, and contains at least about 7×1016 atoms/cm3 of base implant region dopant.

Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

Abstract: The invention concerns a heterojunction bipolar transistor comprising a support, and epitaxially grown from said support, at least: one collecting, respectively emitting, layer; at least one base layer; and at least one emitting, respectively collecting, layer. The collecting, respectively emitting, layer comprises: at least one first undercoat contacted with said base layer, substantially of similar composition as said emitting, respectively collecting, layer; and at least one second undercoat on the side opposite said base layer relative to said first undercoat.

Abstract: Methods for manufacturing a bipolar transistor semiconductor device are described, along with devices fabricated in accordance with the methods. The methods include the steps of forming a stack of layers over a semiconductor body comprising a window definition layer (18,38), a layer (20) of semiconductor material, a first insulating layer (22), and a second insulating layer (24) which is selectively etchable with respect to the first insulating layer. A trench (26) is then etched into the stack down to the window definition layer. The portion of the trench extending through the second insulating layer is widened to form a wider trench portion (28) therethrough. A window (36) is defined in the window definition layer which is aligned with the wider trench portion, and serves to define the base-collector or base-emitter junction in the finished device.

Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

Abstract: A bipolar junction transistor and a method of manufacturing a bipolar junction transistor are disclosed. An exemplary bipolar junction transistor includes a second conductivity type base region in a first conductivity type substrate, step-shaped recesses in the base region, a polysilicon layer doped with a first conductivity type impurity in the step-shaped recesses, and a step-shaped emitter region between the polysilicon layer and the base region.

Abstract: One or more embodiments of the invention relate to a method of making a heterojunction bipolar transistor, including: forming a collector layer; forming a stack of at least a second dielectric layer overlying a first dielectric layer, the stack formed over the collector layer; removing a portion of each of the dielectric layers to form an opening through the stack; and forming a base layer within the opening.

Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

Abstract: A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an emitter layer on the substrate, and growing a nitride interface layer on the base layer as a base current modulation means, such that the nitride interface layer is arranged between the base layer and the emitter layer.

Abstract: A system and method are disclosed for providing an improved polyemit module for a self aligned heterojunction bipolar transistor architecture. The polyemit module of the transistor of the present invention is formed using a double layer deposition process. In the double layer deposition process, the first layer is a layer of emitter polysilicon and the second layer is a sacrificial layer of silicon germanium (SiGe). The shape and thickness of the emitter polysilicon layer of the polyemit module provides (1) a reduction in the overall resistance of the emitter and (2) an increase in the contact area between the emitter polysilicon layer and a contact structure that is more than three times the contact area that is provided in prior art polyemit modules.

Abstract: Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodiments also relate to a vertically integrated electronic device that includes a first terminal region, a second terminal region and a third terminal region. The second terminal region may be arranged over at least a portion of the third terminal region, and at least two of the first, second and third terminal regions may be formed as epitaxially grown regions.

Abstract: A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge.

Abstract: A process for producing a base connection of a bipolar transistor is provided. The process includes the steps of providing a semiconductor structure that can include a three-dimensional sacrificial structure that is selectively removable with respect to adjacent regions. A first semiconductor layer and a second layer of dielectric material is deposited. The first semiconductor layer is partially exposed by partial removal of the second layer. A first reaction layer is deposited that, together with the first semiconductor layer forms reaction products, which are selectively removable with respect to adjacent regions. Remaining material of the first reaction layer that has not reacted with the material of the first semiconductor layer is removed. A second reaction layer is deposited that, with the first semiconductor layer, forms a low-resistivity compound. Remaining material of the second reaction layer that has not reacted with the material of the first semiconductor layer is removed.

Abstract: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A four-component wet etch mixture is tuned to selectively etch the amorphous region while retaining the epitaxial region, wherein the four-component wet etch mixture comprises an oxidizing agent, an etchant, a buffer and a diluent.

Abstract: A method for enhancing operation of a bipolar light-emitting transistor includes the following steps: providing a bipolar light-emitting transistor having emitter, base, and collector regions; providing electrodes for coupling electrical signals with the emitter, base, and collector regions; and adapting the base region to promote carrier transport from the emitter region toward the collector region by providing, in the base region, several spaced apart quantum size regions of different thicknesses, with the thicknesses of the quantum size regions being graded from thickest near the collector to thinnest near the emitter.

Abstract: A method of fabricating a semiconductor device includes a SiGe(C) heterojunction bipolar transistor using a non-selective epitaxial growth where an insulating layer is formed on a substrate and a layer structure including a conductive layer is provided on the insulating layer. A transistor area opening is etched through the conductive layer, and an SiGe base layer is deposited inside the transistor area opening. An insulator is formed on an upper surface so as to fill the transistor area opening, wherein prior to filling the opening, a nitride layer is formed as an inner layer of the transistor area opening.

Abstract: A bipolar transistor structure includes a collector region having a first conductivity type formed in a semiconductor substrate. A base region is formed over the collector region; the base region includes a highly doped lower layer having a second conductivity type opposite the first conductivity type formed on the collector region and a relatively low doped (or undoped) upper layer formed on the highly doped lower layer. An emitter region having the first conductivity type is formed on the upper layer of the base region.

Abstract: A semiconductor device includes a preferably discrete bipolar transistor with a collector region, a base region, and an emitter region which are provided with connection conductors. A known means of preventing a saturation of the transistor is that the latter is provided with a Schottky clamping diode. The latter is formed in that case in that the connection conductor of the base region is also put into contact with the collector region. Here, the second connection conductor is exclusively connected to the base region, and a partial region of that portion of the base region which lies outside the emitter region, as seen in projection, lying below the second connection conductor is given a smaller flux of dopant atoms. The bipolar transistor is provided with a pn clamping diode which is formed between the partial region and the collector region.

Abstract: A heterojunction bipolar transistor (HBT) device structure is provided which facilitates the reduction of the base-collector capacitance and a method for making the same. The base-collector capacitance is decreased by fabricating a base micro-bridge connecting a base contact to a base mesa on the HBT. The base micro-bridge is oriented along about one of 001, 010, 00{overscore (1)}, and 0{overscore (1)}0 direction to a major flat of the wafer. The HBT device employs a phosphorous based collector material. During removal of the phosphorous based collector material, the base layer is undercut forming the micro-bridge, successfully removing the collector and sub-collector material below the bridge due to the orientation of the micro-bridge. The removal of collector and sub-collector material reduces the base-collector junction area, and therefore reduce the base-collector junction capacitance.

Abstract: Methods and apparatus of forming a semiconductor device using pedestals and sidewalls. The pedestals and sidewalls may provide an etch stop and/or a diffusion barrier during manufacture of a semiconductor device. Processes of forming diode connected vertical cylindrical field effect devices are disclosed to exemplify the use of the pedestals and/or sidewalls. A system for forming the pedestals and sidewalls is described.

Abstract: During the conventional manufacture of HBTs, implant damage occurs which leads to enhanced internal base diffusion. This problem has been overcome by making the base and base contact area from a single, uniformly doped layer of silicon-germanium. Instead of an ion implant step to selectively reduce the resistance of this layer away from the base, a layer of polysilicon is selectively deposited (using selective epi deposition) onto only that part. Additionally, the performance of the polysilicon emitter is enhanced by means a brief thermal anneal that drives a small amount of opposite doping type silicon into the SiGe base layer.

Abstract: A semiconductor layer (10) provided on a BOX (buried oxide) layer (2) includes a first P-type region (11), an N+-type region (12), and an N−type region (13) which together form a diode. A plurality of second P-type regions (14) are provided on a bottom part of the semiconductor layer (10). A plurality of insulating oxide films (21) are interposed between the plurality of second P-type regions (14). When the diode is in a reverse-biased state, the second P-type region (14) directly below the N+-type region (12) is approximately the same in potential as the N+-type region (12). The second P-type region (14) will be lower in potential relative to this second P-type region (14) directly below the N+-type region (12), as the second P-type region (14) gets nearer to the first P-type region (11). Electric field concentration can thus be relaxed at an interface between the semiconductor layer (10) and the BOX layer (2), whereby improvement in breakdown voltage of the diode is realized.

Abstract: A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area.

Abstract: The present disclosure provides a process for producing a SiGe layer in a bipolar device having a reduced amount of gaps or discontinuities on a shallow trench isolation (STI) region use for a base electrode connection. The process is used for forming an SiGe layer for use in a semiconductor device. The process includes doping a single crystal substrate with a first dopant type, baking the doped single crystal substrate at a temperature less than 900° C., and at a pressure less than 100 torr; and depositing the SiGe layer on the baked single crystal substrate (epi SiGe) to serve as the base electrode and on the STI region (poly SiGe) to serve as a connection for the base electrode. The semiconductor device is thereby created from the combination of the doped single crystal substrate and the deposited SiGe layer.

Abstract: A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process.

Abstract: A structure and method of making an NPN heterojunction bipolar transistor (100) includes a semiconductor substrate (11) with a first region (82) containing a dopant (86) for forming a base region of the transistor. A second region (84) adjacent to the first region is used to form an emitter region of the transistor. An interstitial trapping material (81) reduces diffusion of dopants in the base region during subsequent thermal processing.

Abstract: A bipolar transistor having a base semiconductor layer structure to minimize base parasitic resistance and a method of manufacturing the bipolar transistor are provided. In the provided bipolar transistor, a collector region of a second conductivity type, which is defined by isolation regions, is formed on a semiconductor substrate of a first conductivity type. A first base semiconductor layer of the first conductivity type extends from the upper surface of the collector region to the upper surface of the isolation regions. Here, the first base semiconductor layer is formed of a silicon germanium (SiGe) layer. Second base semiconductor layers of the first conductivity type are formed on the portions of the first base semiconductor layer except for the portions having the emitter region and the emitter insulating layers. Base ohmic layers are formed on the second base semiconductor layers.

Abstract: According to one embodiment of the invention, a method for manufacturing bipolar junction transistors includes disposing a first oxide layer between a semiconductor substrate and a base polysilicon layer, forming a dielectric layer outwardly from the base polysilicon layer, and forming an emitter region by removing a portion of the dielectric layer and a portion of the base polysilicon layer. The method further includes removing a portion of the first oxide layer to form undercut regions adjacent the emitter region and to enlarge the emitter region, and forming an oxide pad outwardly from the semiconductor substrate in the emitter region.

Abstract: An epitaxial base bipolar transistor including an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on a portion of the single crystal layer; a raised extrinsic base on a surface of the semiconductor substrate; an insulator between the raised emitter and the raised extrinsic base, wherein the insulator is a spacer; and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in the single crystal layer, wherein the emitter diffusion has an emitter diffusion junction depth.

Abstract: A method of producing a bipolar transistor includes the step of providing a sacrificial mesa over a layer of SiGe in order to prevent a polysilicon covering layer from forming over a predetermined region of the SiGe layer forming the transistor base. After an etching process removes the sacrificial mesa and the SiGe layer is exposed, an oppositely doped material is applied over top of the SiGe layer to form an emitter. This makes it possible to realize a thin layer of silicon germanium to serve as the transistor base. This method prevents the base layer SiGe from being affected, as it otherwise would be using a conventional double-poly process.

Abstract: In one disclosed embodiment, a collector is deposited and a base is grown on the collector, for example, by epitaxially depositing either silicon or silicon-germanium. An emitter is fabricated on the base followed by implant doping an extrinsic base region. For example, the extrinsic base region can be implant doped using boron. The extrinsic base region doping diffuses out during subsequent thermal processing steps in chip fabrication, creating an out diffusion region in the device, which can adversely affect various operating characteristics, such as parasitic capacitance and linearity. The out diffusion is controlled by counter doping the out diffusion region. For example, the counter doped region can be implant doped using arsenic or phosphorous. Also, for example, the counter doped region can be formed using tilt implanting or, alternatively, by implant doping the counter doped region and forming a spacer on the base prior to implanting the extrinsic base region.

Abstract: A method for fabricating a bipolar device, including the steps of forming an epitaxial growth retarding layer on a substrate at a predetermined angle, forming a collector layer on the substrate so that the collector layer is adjacent the epitaxial growth retarding layer and has an inclined portion formed over an edge portion of the epitaxial growth retarding layer, forming a base layer having an inclined portion on the collector layer, and forming an emitter layer on the inclined portion of the base layer.

Abstract: The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer; overetching the silicon nitride under the spacers; filling the overetched layer with highly-doped N-type polysilicon; depositing an N-type doped polysilicon layer; and diffusing the doping contained in the third and fourth layers to form the emitter of the bipolar transistor.

Abstract: The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, opening the protection layer at the base-emitter location of the bipolar transistor, forming a first P-type doped layer of polysilicon, a second layer of silicon nitride and a second oxide layer, opening these last three layers at the center of the emitter-base region of the bipolar transistor, and depositing a third silicon nitride layer, forming spacers, removing the apparent parts of the third layer of silicon nitride, and depositing a third N-type doped polysilicon layer.

Abstract: A method for producing a semiconductor device including a bipolar transistor, has the steps of: forming an element isolating region in a major surface of a semiconductor substrate to define an element forming region to form a collector region in the element forming region surrounded by the element isolating region; allowing the epitaxial growth of a semiconductor layer on the major surface of the semiconductor substrate to form a base region of the semiconductor layer on the collector region; forming a growth inhibiting film on a region forming the base region of the semiconductor layer; removing the growth inhibiting film to expose a part of the semiconductor layer; covering the upper surface and side wall of the conductive film, which is exposed in the predetermined region, with an insulator film; covering the side wall of the conductive film, which is exposed in the predetermined region; and forming an emitter region in a surface region of the predetermined region of the semiconductor layer, which is surro

Abstract: An improved method and an apparatus for forming a self-aligned epitaxial base bipolar transistor in a semiconductor material is disclosed. The method of the invention involves forming an intrinsic base region formed by growing an epitaxial semiconductor material over a collector region. A raised sacrificial emitter core is then formed on the intrinsic base region followed by depositing a substantially conformal spacer layer over the sacrificial emitter core. Next, the spacer material is anisotropically etched such that a protective spacer ring is formed about the sacrificial emitter core. An extrinsic base is then formed by implanting dopant into the epitaxial base region wherein the sacrificial emitter core and the spacer ring preserve an emitter region. The spacer ring also serves to self-align the extrinsic base region to the emitter region. The protective sacrificial emitter core and spacer ring are then removed.

Abstract: The present invention presents a method in which semiconductor heterojunction and homojunction materials are selectively formed on silicon pedestals in an HMIC after the high temperature processing steps in fabricating the HMIC structure are completed.

Abstract: A bipolar transistor has a performance and high reliability, which are by enhancing a withstand voltage between an emitter and a base. The bipolar transistor includes a first impurity diffusion layer in a semiconducting substrate, a first conductive film connected to the first diffusion layer, and an opening disposed in the first conductive film. A second impurity diffusion layer is formed in a portion, exposed from the opening portion, of the semiconducting substrate and is connected to the first impurity diffusion layer. A third impurity diffusion layer is formed so as to contain the second diffusion layer and side walls are formed on the side walls of the opening. A fourth impurity diffusion layer is formed in the third impurity diffusion layer in the opening surrounded by the side walls.