Forming Base Region Of Specified Dopant Concentration Profile (e.g., Inactive Base Region More Heavily Doped Than Active Base Region, Etc.) Patents (Class 438/350)
  • Patent number: 9716117
    Abstract: The invention relates to the field of display technologies, and discloses a method for producing a via, a method for producing an array substrate, an array substrate and a display device to prevent a chamfer from being formed in producing the via, to promote the product quality and improve the display effect of the display device. The method for producing a via comprises: employing a first etching process to partially etch a top film layer in an area that needs to form a via above an electrode, wherein the vertical etching amount achieved by employing the first etching process is less than the thickness of the top film layer; and employing a second etching process for which the vertical etching rate is larger than the lateral etching rate to etch the remaining part in the area that needs to form a via, until the electrode is exposed.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: July 25, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Changjiang Yan, Kai Lu, Jian Guo, Zhenyu Xie
  • Patent number: 9053939
    Abstract: A heterojunction bipolar transistor (HBT) may include an n-type doped crystalline collector formed in an upper portion of a crystalline silicon substrate layer; a p-type doped crystalline p+Si1-xGex layer, formed above the n-type doped collector, that forms a p-type doped internal base of the HBT; a crystalline silicon cap formed on the p-type doped crystalline p+Si1-xGex layer, in which the crystalline silicon cap includes an n-type impurity and forms an n-type doped emitter of the HBT; and an n-type doped crystalline silicon emitter stack formed within an opening through an insulating layer to an upper surface of the crystalline silicon cap.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, David L. Harame, Qizhi Liu, Alexander Reznicek
  • Patent number: 9048280
    Abstract: A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: June 2, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Kevin K. Chan, Wilfried E. Haensch, Tak H. Ning
  • Patent number: 9018069
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated from each other by the first doped region. The third doped region has a first portion and a second portion adjacent to each other. The first portion and the second portion are respectively adjacent to and away from the second doped region. A dopant concentration of the first portion is bigger than a dopant concentration of the second portion.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: April 28, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chieh-Chih Chen, Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu
  • Patent number: 9012291
    Abstract: The present invention discloses a bipolar transistor with an embedded epitaxial external base region, which is designed to solve the problem of the TED effect with the prior art structures. The bipolar transistor with an embedded epitaxial external base region of the present invention comprises at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter. The external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region. A portion of the external base region is located beneath the sidewalls. The present invention discloses a method of forming a bipolar transistor with an embedded epitaxial external base region.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: April 21, 2015
    Assignee: Tsinghua University
    Inventors: Yu-dong Wang, Jun Fu, Jie Cui, Yue Zhao, Zhi-hong Liu, Wei Zhang, Gao-qing Li, Zheng-li Wu, Ping Xu
  • Patent number: 9006864
    Abstract: A semiconductor device containing an NPN bipolar junction transistor may be formed by forming a p-type radiation induced diode structure (RIDS) region in an intrinsic p-type base region of the NPN bipolar junction transistor at a boundary of the intrinsic p-type base region with a dielectric layer over a substrate of the semiconductor device, between an emitter of the NPN bipolar junction transistor and an extrinsic p-type base region of the NPN bipolar junction transistor. The p-type RIDS region has a doping density high enough to prevent inversion of a surface of the p-type RIDS region adjacent to the dielectric layer when trapped charge is accumulated in the dielectric layer, while the intrinsic p-type base region may invert from the trapped charge forming the radiation induced diode structure. The p-type RIDS region is separated from the emitter and from the extrinsic base region by portions of the intrinsic base region.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: April 14, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: James Fred Salzman, Richard Guerra Roybal, Randolph William Kahn
  • Patent number: 8946035
    Abstract: A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Ming-Huan Tsai, Clement Hsingjen Wann
  • Patent number: 8927972
    Abstract: A current-amplifying transistor device is provided, between an emitter electrode and a collector electrode, with two organic semiconductor layers and a sheet-shaped base electrode. One of the organic semiconductor layers is arranged between the emitter electrode and the base collector electrode, and has a diode structure of a p-type organic semiconductor layer and an n-type p-type organic semiconductor layer. A current-amplifying, light-emitting transistor device including the current-amplifying transistor device and an organic EL device portion formed in the current-amplifying transistor device is also disclosed.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: January 6, 2015
    Assignees: Dainichiseika Color & Chemicals Mfg. Co., Ltd.
    Inventors: Ken-ichi Nakayama, Junji Kido, Yong-Jin Pu, Fumito Suzuki, Naomi Oguma, Naoki Hirata
  • Publication number: 20140329368
    Abstract: The present invention discloses a bipolar transistor with an embedded epitaxial external base region, which is designed to solve the problem of the TED effect with the prior art structures. The bipolar transistor with an embedded epitaxial external base region of the present invention comprises at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter. The external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region. A portion of the external base region is located beneath the sidewalls. The present invention discloses a method of forming a bipolar transistor with an embedded epitaxial external base region.
    Type: Application
    Filed: July 18, 2014
    Publication date: November 6, 2014
    Inventors: Yu-dong Wang, Jun Fu, Jie Cui, Yue Zhao, Zhi-hong Liu, Wei Zhang, Gao-qing Li, Zheng-li Wu, Ping Xu
  • Patent number: 8828835
    Abstract: An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Rick L. Wise, Hiroshi Yasuda
  • Publication number: 20140134820
    Abstract: Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface.
    Type: Application
    Filed: January 16, 2014
    Publication date: May 15, 2014
    Inventors: XIN LIN, DANIEL J. BLOMBERG, HONGNING YANG, JIANG-KAI ZUO
  • Publication number: 20140124895
    Abstract: A semiconductor device containing an NPN bipolar junction transistor may be formed by forming a p-type radiation induced diode structure (RIDS) region in an intrinsic p-type base region of the NPN bipolar junction transistor at a boundary of the intrinsic p-type base region with a dielectric layer over a substrate of the semiconductor device, between an emitter of the NPN bipolar junction transistor and an extrinsic p-type base region of the NPN bipolar junction transistor. The p-type RIDS region has a doping density high enough to prevent inversion of a surface of the p-type RIDS region adjacent to the dielectric layer when trapped charge is accumulated in the dielectric layer, while the intrinsic p-type base region may invert from the trapped charge forming the radiation induced diode structure. The p-type RIDS region is separated from the emitter and from the extrinsic base region by portions of the intrinsic base region.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 8, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: James Fred SALZMAN, Richard Guerra ROYBAL, Randolph William KAHN
  • Publication number: 20130307122
    Abstract: The present invention discloses a bipolar transistor with an embedded epitaxial external base region, which is designed to solve the problem of the TED effect with the prior art structures. The bipolar transistor with an embedded epitaxial external base region of the present invention comprises at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter. The external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region. A portion of the external base region is located beneath the sidewalls. The present invention discloses a method of forming a bipolar transistor with an embedded epitaxial external base region.
    Type: Application
    Filed: September 24, 2012
    Publication date: November 21, 2013
    Applicant: TSINGHUA UNIVERSITY
    Inventors: Yu-dong Wang, Jun Fu, Jie Cui, Yue Zhao, Zhi-hong Liu, Wei Zhang, Gao-qing Li, Zheng-li Wu, Ping Xu
  • Patent number: 8581327
    Abstract: A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: November 12, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh-Kun Lai, Yen-Hao Shih, Ling-Wu Yang, Chun-Min Cheng
  • Publication number: 20130193557
    Abstract: The invention relates to an electronic device with a bipolar transistor having an emitter, a base and a collector. The base has a first region of a first concentration of the first dopant for forming an electrically active region of the base and a second region of a second concentration of the first dopant close to the surface of the base region. The first region is separated from the second region by a region of a third concentration of the first dopant and the third concentration is lower than the first and the second concentration.
    Type: Application
    Filed: July 25, 2012
    Publication date: August 1, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philipp MENZ, Berthold STAUFER, Yasuda HIROSHI
  • Patent number: 8486797
    Abstract: Bipolar junction transistors are provided in which at least one of an emitter contact, a base contact, or a collector contact thereof is formed by epitaxially growing a doped SixGe1-x layer, wherein x is 0?x?1, at a temperature of less than 500° C. The doped SixGe1-x layer comprises crystalline portions located on exposed surfaces of a crystalline semiconductor substrate and non-crystalline portions that are located on exposed surfaces of a passivation layer which can be formed and patterned on the crystalline semiconductor substrate. The doped SixGe1-x layer of the present disclosure, including the non-crystalline and crystalline portions, contains from 5 atomic percent to 40 atomic percent hydrogen.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Tak H. Ning, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20130168822
    Abstract: Vertical bipolar junction structures, methods of manufacture and design structures. The method includes forming one or more sacrificial structures for a bipolar junction transistor (BJT) in a first region of a chip. The method includes forming a mask over the one or more sacrificial structures. The method further includes etching an opening in the mask, aligned with the one or more sacrificial structures. The method includes forming a trench through the opening and extending into diffusion regions below the one or more sacrificial structures. The method includes forming a base region of the BJT by depositing an epitaxial material in the trench, in contact with the diffusion regions. The method includes forming an emitter contact by depositing a second epitaxial material on the base region within the trench. The epitaxial material for the emitter region is of an opposite dopant type than the epitaxial material of the base region.
    Type: Application
    Filed: January 4, 2012
    Publication date: July 4, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William F. CLARK, JR., John J. PEKARIK, Yun SHI, Yanli ZHANG
  • Patent number: 8343841
    Abstract: A method for fabricating a semiconductor device includes forming a first semiconductor layer on a front side of the semiconductor substrate. Additional semiconductor layers may be formed on a font side of the first semiconductor layer. The substrate is subsequently removed. In some embodiments, one or more additional semiconductor layers may be formed on the back side of the first semiconductor layer after the semiconductor substrate has been removed. Additionally, in some embodiments, a portion of the first semiconductor layer is removed along with the semiconductor substrate. In such embodiments, the first semiconductor layer is subsequently etched to a known thickness. Source regions and device electrodes may be then be formed.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: January 1, 2013
    Assignee: Purdue Research Foundation
    Inventors: James A. Cooper, Xiaokun Wang
  • Patent number: 8319282
    Abstract: A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: November 27, 2012
    Assignee: Infineon Technologies Austria AG
    Inventors: Christoph Kadow, Thorsten Meyer, Norbert Krischke
  • Patent number: 8263469
    Abstract: A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: September 11, 2012
    Assignee: Analog Devices, Inc.
    Inventors: Bernard Patrick Stenson, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuiness, William Allan Lane
  • Patent number: 8216910
    Abstract: A wafer comprising at least one high Ft HBT and at least one high BVceo HBT having various collector profiles on a common III-V compound semiconductor based wafer. The N+ implant in the collector varies the collector profiles of individual HBTs on the wafer. The method for preparing the device comprises forming of HBT layers up to and including collector layer on non-silicon based substrate, performing ion implantation, annealing for implant activation, and forming remaining HBT layers.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: July 10, 2012
    Assignee: HRL Laboratories, LLC
    Inventors: Mary Chen, Marko Sokolich
  • Patent number: 8211785
    Abstract: A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion may be controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: July 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takaharu Itani, Takayuki Ito, Kyoichi Suguro
  • Patent number: 8168505
    Abstract: A method of fabricating a transistor is provided. The transistor includes a SiGe epitaxial layer formed in a recess region of a substrate at both side of a gate electrode and a SiGe capping layer formed on the SiGe epitaxial layer. The transistor further includes a SiGe seed layer formed under the SiGe epitaxial layer and a silicon capping layer formed on the SiGe capping layer.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: May 1, 2012
    Assignee: Jusung Engineering Co., Ltd.
    Inventors: Cheol Hoon Yang, Yong Han Jeon
  • Patent number: 8168504
    Abstract: An integrated circuit includes a bipolar transistor comprising a substrate and a collector formed in the substrate. The collector includes a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone located between the central zone and the lateral zone 4a of the collector. The substrate includes a lightly doped lateral zone and a highly doped central zone. The dopant species in the zone of the substrate are electrically inactive.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: May 1, 2012
    Assignee: STMicroelectronics SA
    Inventors: Damien Lenoble, Thierry Schwartzmann, Laurence Boissonnet
  • Publication number: 20120007176
    Abstract: A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate.
    Type: Application
    Filed: July 9, 2010
    Publication date: January 12, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Christoph KADOW, Thorsten MEYER, Norbert KRISCHKE
  • Patent number: 8058704
    Abstract: A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: November 15, 2011
    Assignee: Analog Devices, Inc.
    Inventors: Bernard Patrick Stenson, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuiness, William Allan Lane
  • Patent number: 8022506
    Abstract: A semiconductor on insulator device has an insulator layer, an active layer (40) on the insulator layer, a lateral arrangement of collector (10), emitter (30) and base (20) on the active layer, and a high Base-dose region (70) extending under the emitter towards the insulator to suppress vertical current flowing under the emitter. This region (70) reduces the dependence of current-gain and other properties on the substrate (Handle-wafer) voltage. This region can be formed of the same doping type as the base, but having a stronger doping. It can be formed by masked alignment in the same step as an n type layer used as the body for a P-type DMOS transistor.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: September 20, 2011
    Assignee: NXP B.V.
    Inventor: Adrianus W. Ludikhuize
  • Publication number: 20110143513
    Abstract: The disclosed subject matter provides a method of forming a bipolar transistor. The method includes depositing a first insulating layer over a first layer of material that is doped with a dopant of a first type. The first layer is formed over a substrate. The method also includes modifying a thickness of the first oxide layer based on a target dopant profile and implanting a dopant of the first type in the first layer. The dopant is implanted at an energy selected based on the modified thickness of the first insulating layer and the target dopant profile.
    Type: Application
    Filed: February 15, 2011
    Publication date: June 16, 2011
    Inventors: Thomas J. Krutsick, Christopher J. Speyer
  • Publication number: 20110121428
    Abstract: An improved bipolar transistor (40, 40?) is provided, manufacturable by a CMOS IC process without added steps. The improved transistor (40, 40?) comprises an emitter (48) having first (482) and second (484) portions of different depths (4821, 4841), a base (46) underlying the emitter (48) having a central portion (462) of a first base width (4623) underlying the first portion (482) of the emitter (48), a peripheral portion (464) having a second base width (4643) larger than the first base width (4623) partly underlying the second portion (484) of the emitter (48), and a transition zone (466) of a third base width (4644) and lateral extent (4661) lying laterally between the first (462) and second (464) portions of the base (46), and a collector (44) underlying the base (46). The gain of the transistor (40, 40?) is much larger than a conventional bipolar transistor (20) made using the same CMOS process.
    Type: Application
    Filed: November 20, 2009
    Publication date: May 26, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 7943969
    Abstract: A transistor and a method of fabricating the same are provided. The transistor includes a SiGe epitaxial layer formed in a recess region of a substrate at both side of a gate electrode and a SiGe capping layer formed on the SiGe epitaxial layer. The transistor further includes a SiGe seed layer formed under the SiGe epitaxial layer and a silicon capping layer formed on the SiGe capping layer.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: May 17, 2011
    Assignee: Jusung Engineering Co. Ltd.
    Inventors: Cheol Hoon Yang, Yong Han Jeon
  • Patent number: 7939414
    Abstract: Methods for forming a bipolar junction transistor device are described herein. A method for forming the bipolar junction transistor device may include doping a first portion of a substrate with a first dopant to form a base pick-up region, and after doping the first portion of the substrate, doping a second portion of the substrate with a second dopant to form at least one emitter region. A bipolar junction transistor device may include a floating collector, in which case the bipolar junction transistor device may be operated as a diode for improved emitter current.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: May 10, 2011
    Assignee: Marvell International Ltd.
    Inventors: Pantas Sutardja, Albert Wu, Chien-Chuan Wei, Runzi Chang, Winston Lee, Peter Lee
  • Patent number: 7880272
    Abstract: Aspects of the present invention include a semiconductor device and method. In a transition region of a semiconductor material region, a near-surface compensation doping area with a conductivity type, which is different than the conductivity type of a transition doping area of the semiconductor material region, is provided in the surface region of the semiconductor material region. The doping of the near-surface compensation doping area of the semiconductor device at least partially compensates for the doping in the transition doping area.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventor: Gerhard Schmidt
  • Patent number: 7879706
    Abstract: A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: February 1, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh-Kun Lai, Yen-Hao Shih, Ling-Wu Yang, Chun-Min Cheng
  • Patent number: 7851890
    Abstract: By a non-selective epitaxial growth method, an SiGe film is grown on the whole surface of a silicon oxide film so as to cover an inner wall of a base opening. Here, such film forming conditions are selected that, inside the base opening, a bottom portion is formed of single crystal, other portions such as a sidewall portion are formed of polycrystalline, and a film thickness of the sidewall portion is less than or equal to 1.5 times the film thickness of the bottom portion. In this non-selective epitaxial growth, monosilane, hydrogen, diborane, and germane are used as source gases. Then, flow rates of monosilane and hydrogen are set to 20 sccm and 20 slm respectively. Also, a growth temperature is set to 650° C., a flow rate of diborane is set to 75 sccm, and a flow rate of germane is set to 35 sccm.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: December 14, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hidekazu Sato, Toshihiro Wakabayashi
  • Patent number: 7816706
    Abstract: The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The gate base region has the same nominal doping density as the cathode base region in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region, which is opposite the cathode metallization. The gate base region has a higher doping density than the cathode base region and/or the gate base region has a greater depth than the cathode base region in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: October 19, 2010
    Assignee: ABB Technology AG
    Inventors: Munaf Rahimo, Peter Streit
  • Patent number: 7811894
    Abstract: An improved bipolar junction transistor and a method for manufacturing the same are provided. The bipolar junction transistor includes: a buried layer and a high concentration N-type collector region in a P-type semiconductor substrate; a low concentration P-type base region in the semiconductor substrate above the buried layer; a first high concentration P-type base region along an edge of the low concentration P-type base region; a second high concentration P-type base region at a center of the low concentration P-type base region; a high concentration N-type emitter region between the first and second high concentration base regions; and insulating layer spacers between the high concentration base regions and the high concentration emitter regions. In the bipolar junction transistor, the emitter-base distance can be reduced using a trench and an insulating layer spacer. This may improve base voltage and high-speed response characteristics.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: October 12, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Nam Joo Kim
  • Patent number: 7807539
    Abstract: Methods for forming a bipolar junction transistor device are described herein. A method for forming the bipolar junction transistor device may include doping a first portion of a substrate with a first dopant to form a base pick-up region, and after doping the first portion of the substrate, doping a second portion of the substrate with a second dopant to form at least one emitter region. A bipolar junction transistor device may include a floating collector, in which case the bipolar junction transistor device may be operated as a diode for improved emitter current.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: October 5, 2010
    Assignee: Marvell International Ltd.
    Inventors: Pantas Sutardja, Albert Wu, Chien-Chuan Wei, Runzi Chang, Winston Lee, Peter Lee
  • Patent number: 7772079
    Abstract: A vertical organic transistor and a method for fabricating the same are provided, wherein an emitter, a grid with openings and a collector are sequentially arranged above a substrate. Two organic semiconductor layers are interposed respectively between the emitter and the grid with openings and between the grid with openings and the collector. The channel length is simply decided by the thickness of the organic semiconductor layers. The collector current depends on the space-charge-limited current contributed by the potential difference between the emitter and the openings of the grid. And the grid voltage can thus effectively control the collector current. Further, the fabrication process of the vertical organic transistor of the present invention is simple and exempt from using the photolithographic process.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: August 10, 2010
    Assignee: National Chiao Tung University
    Inventors: Hsin-Fei Meng, Sheng-Fu Horng, Yu-Chiang Chao
  • Publication number: 20100167488
    Abstract: An integrated circuit includes a bipolar transistor comprising a substrate and a collector formed in the substrate. The collector includes a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone located between the central zone and the lateral zone 4a of the collector. The substrate includes a lightly doped lateral zone and a highly doped central zone. The dopant species in the zone of the substrate are electrically inactive.
    Type: Application
    Filed: March 9, 2010
    Publication date: July 1, 2010
    Applicant: STMICROELECTRONICS SA.
    Inventors: Damien Lenoble, Thierry Schwartzmann, Laurence Boissonnet
  • Patent number: 7732256
    Abstract: A method of fabrication a non-volatile memory is provided. A stacked structure is formed on a substrate, the stacked structure including a gate dielectric layer and a control gate. Then, a first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed on the top and sidewalls of the stacked structure and the exposed substrate. Thereafter, a pair of charge storage layers are formed over the substrate to respectively cover a portion of the top and sidewalls of the stacked structure, and a gap exists between each of the charge storage layers.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: June 8, 2010
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Ming-Chang Kuo
  • Publication number: 20100129975
    Abstract: An improved base for a NPN bipolar transistor. The base region is formed with Boron and Indium dopants for improved beta early voltage product and reduced base resistance.
    Type: Application
    Filed: February 1, 2010
    Publication date: May 27, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventor: James D. Beasom
  • Patent number: 7692269
    Abstract: A vertical organic transistor and a method for fabricating the same are provided, wherein an emitter, a grid with openings and a collector are sequentially arranged above a substrate. Two organic semiconductor layers are interposed respectively between the emitter and the grid with openings and between the grid with openings and the collector. The channel length is simply decided by the thickness of the organic semiconductor layers. The collector current depends on the space-charge-limited current contributed by the potential difference between the emitter and the openings of the grid. And the grid voltage can thus effectively control the collector current. Further, the fabrication process of the vertical organic transistor of the present invention is simple and exempt from using the photolithographic process.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: April 6, 2010
    Assignee: National Chiao Tung University
    Inventors: Hsin-Fei Meng, Sheng-Fu Horng, Yu-Chiang Chao
  • Patent number: 7651919
    Abstract: A method for fabricating a heterojunction bipolar transistor (HBT) is provided. The method includes providing a substrate including a collector region; forming a compound base region over the collector region; and forming an emitter region over the compound base region including forming a first emitter layer within the emitter region and doping the first emitter layer with a pre-determined percentage of at least one element associated with the compound base region. In one implementation, an emitter region is formed including multiple emitter layers to enhance a surface recombination surface area within the emitter region.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: January 26, 2010
    Assignee: Atmel Corporation
    Inventors: Darwin Gene Enicks, Damian Carver
  • Patent number: 7629211
    Abstract: A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material comprising a first chemical element and a second chemical element. A first concentration ratio between a concentration of the first chemical element in a first portion of the strain-creating element and a concentration of the second chemical element in the first portion of the strain-creating element is different from a second concentration ratio between a concentration of the first chemical element in a second portion of the strain-creating element and a concentration of the second chemical element in the second strain-creating element.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: December 8, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sven Beyer, Thorsten Kammler, Rolf Stephan, Manfred Horstmann
  • Patent number: 7615457
    Abstract: A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: November 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Akatsu, Rama Divakaruni, Gregory G. Freeman, David R. Greenberg, Marwan H. Khater, William R. Tonti
  • Publication number: 20090250724
    Abstract: A bipolar transistor is formed on a heavily doped silicon substrate (1). An epitaxially grown collector (12) is formed on the substrate (1) and comprises silicon containing germanium at least at the top of the collector (12). An epitaxial base (13) is formed on the collector (12) to have the opposite polarity and also comprises silicon containing germanium at least at the bottom of the base (13). An emitter is formed at the top of the base (13) and comprises polysilicon doped to have the same polarity as the collector (12).
    Type: Application
    Filed: December 14, 2005
    Publication date: October 8, 2009
    Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventor: John Nigel Ellis
  • Publication number: 20090200577
    Abstract: The invention relates to a semiconductor device with a substrate (11) and a semiconductor body (11) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) comprising a first, a second and a third connection conductor, which emitter region (1) comprises a mesa-shaped emitter connection region (1A) provided with spacers (4) and adjacent thereto a base connection region (2A) comprising a conductive region (2AA) of poly crystalline silicon. In a device (10) according to the invention, the base connection region (2A) comprises a further conducting region (2AB), which is positioned between the conductive region (2AA) of poly crystalline silicon and the base region (2) and which is made of a material with respect to which the conducting region (2AA) of polycrystalline silicon is selectively etchable. Such a device (10) is easy to manufacture by means of a method according to the invention and its bipolar transistor possesses excellent RF properties.
    Type: Application
    Filed: June 20, 2006
    Publication date: August 13, 2009
    Applicant: NXP B.V.
    Inventors: Erwin Hijzen, Joost Melai, Francois Neuilly
  • Publication number: 20090181513
    Abstract: A vertical organic transistor and a method for fabricating the same are provided, wherein an emitter, a grid with openings and a collector are sequentially arranged above a substrate. Two organic semiconductor layers are interposed respectively between the emitter and the grid with openings and between the grid with openings and the collector. The channel length is simply decided by the thickness of the organic semiconductor layers. The collector current depends on the space-charge-limited current contributed by the potential difference between the emitter and the openings of the grid. And the grid voltage can thus effectively control the collector current. Further, the fabrication process of the vertical organic transistor of the present invention is simple and exempt from using the photolithographic process.
    Type: Application
    Filed: February 20, 2009
    Publication date: July 16, 2009
    Inventors: Hsin-Fei Meng, Sheng-Fu Horng, Yu-Chiang Chao
  • Patent number: 7538412
    Abstract: A semiconductor device includes a semiconductor material, the semiconductor material including a base region and a field stop zone including a first side adjacent the base region and a second side opposite the first side. The field stop zone includes a first dopant implant and a second dopant implant. The first dopant implant has a first dopant concentration maximum and the second dopant implant has a second dopant concentration maximum with the first dopant concentration maximum being less than the second dopant concentration maximum, and being located closer to the second side than the second dopant concentration maximum.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: May 26, 2009
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Helmut Strack, Carsten Schaeffer, Frank Pfirsch
  • Patent number: 7495313
    Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: February 24, 2009
    Assignees: Board of Trustees of the Leland Stanford Junior University, Canon Kabushiki Kaisha
    Inventors: Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara