Abstract: A method for making a semiconductor device, includes forming an oxide layer on a silicon substrate, forming a nitride layer over the oxide layer; depositing one of a doped oxide layer and an undoped porous oxide layer on the nitride layer, etching trenches through the one of the doped layer and the undoped porous oxide layer, the nitride layer, and the oxide layer, depositing an undoped oxide layer to fill the trenches, and patterning the undoped oxide by chemical mechanical polishing (CMP).

Abstract: A novel method for forming contact holes is disclosed. According to the present invention, a silicon substrate is prevented from being over-etched by performing a two-step etching process. The first step is to etch a thick interlayer insulating layer until a thin etch stopper layer, formed beneath the interlayer insulating layer, is exposed. The second step is to over-etch the thin etch stopper layer. With this method, a lower capacitor electrode or a bit line can be prevented from being short-circuited with a well region of the silicon substrate, thereby reducing leakage currents.

Abstract: In one embodiment, a first dielectric layer (16) is formed overlying a semiconductor substrate (4). A portion of the first dielectric layer (16) is then etched using a patterned masking layer (18). The patterned masking layer (18) is removed and an intermediate polishing layer (20) is formed overlying the first dielectric layer (16). A second dielectric layer (22) is formed overlying the intermediate polishing layer (20), and the second dielectric layer (22) is polished to expose a portion of the intermediate polishing layer (20), and to determine a polishing rate for the second dielectric layer (22). The polishing rate for the second dielectric layer (22) is then used to calculate a polishing time for the first dielectric layer (16), and the first dielectric layer (16) is polished for the calculated time.

Abstract: A high Q inductor and its forming method is disclosed. In this forming method, a semiconductor substrate is first provided with a trench formed thereon. The trench is defined by dry etching and formed to a depth of 3˜5 &mgr;m. A material having a higher resistivity than that of the semiconductor is then provided to fill the trench. The material can be formed by first depositing an epitaxy layer with a lower dopant concentration than that of the semiconductor substrate by several orders of magnitude on the semiconductor substrate, then etching back the epitaxy layer to expose the surface of the semiconductor substrate. Thereafter, a dielectric layer is formed on the semiconductor substrate and the trench, and an inductor winding is formed on the dielectric layer above the trench to form the high Q inductor.

Abstract: A method for forming a capped shallow trench isolation (CaSTI) structure begin by etching a trench opening (210). The opening (210) is filled with an oxide or like trench fill material (216b) via a deposition and chemical mechanical polish (CMP) step. The plug (216b) is reactive ion etched (RIE) to recess a top of the plug (216b) into the trench opening (210) to form a recessed plug region (216c). A silicon nitride or oxynitride capping layer (218b) is then formed over the recessed plug region (216c) via another deposition and polishing step. The nitride cap layer (218b) protects the underlying region (216c) from erosion due to active area preparation, cleaning, and processing.

Abstract: A method of forming a shallow trench isolation trenches in a silicon substrate of an integrated circuit device is achieved. A silicon substrate is provided. A buffer layer is deposited overlying the silicon substrate. An etching endpoint layer is deposited overlying the buffer layer. A silicon layer is deposited layer overlying the etching endpoint layer. A photoresist layer is coated overlying the silicon layer. The photoresist layer is developed wherein the photoresist layer is removed where the trenches are planned. The silicon layer, the etching endpoint layer, and the buffer layer are etched through to expose the top surface of the silicon substrate. The silicon layer and the silicon substrate layer are etched until the top surface of the etching endpoint layer is exposed, and the trenches are thereby formed. The integrated circuit device is completed.

Abstract: A contact structure of a semiconductor device includes an impurity-doped region formed in the semiconductor substrate, a trench having a groove in the semiconductor substrate, with the groove being in contact with at least one side face of the impurity-doped region, a conductive layer buried in the trench, and a contact region formed on at least one side face of the impurity-doped region, for connecting the impurity-doped region and the conductive layer. Thus, the area occupied by a unit cell is reduced and integration density can be increased accordingly.

Abstract: A method for fabricating a STI structure includes a pad oxide layer and a hard masking layer are sequentially formed over a semiconductor substrate. A trench is formed in the substrate by patterning over the substrate. A liner oxide layer is formed over a side-wall of the trench in the substrate. An isolating layer by APCVD and an isolating layer by HDPCVD are sequentially formed over the substrate, in which the height of the CVD isolating layer within the trench is lower than the height of the hard masking layer. A CMP process is performed, using the hard masking layer as a polishing stop. The hard masking layer and the pad oxide layer are removed to accomplish the STI structure.

Abstract: A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxide layer is formed over the silicon nitride layer and the silicon dioxide and silicon nitride layers are patterned using a patterned mask having a width, thereby forming sidewalls in the two layers. The nitride and oxide layers are subjected to an oxygen plasma which treats the sidewalls and leaves a portion of the silicon nitride layer between the sidewalls untreated. The silicon dioxide and the untreated portion of the silicon nitride layer are removed thereby resulting in pillars of treated silicon nitride. Finally, the polycrystalline silicon is etched using the pillars as a mask. The patterned polycrystalline silicon layer thereby comprises features having widths narrower than the width of the original mask.

Abstract: A trench isolation structure featuring a shallow trench overlying a deep trench is fabricated avoiding creation of irregularities on the deep trench sidewalls. Such sidewall irregularities are conventionally associated with interaction between etchant and unexposed positive photoresist formed at the bottom of the deep trench during prior shallow trench photolithography steps. In one embodiment of the present invention, a deep trench is created and then a positive photoresist mask is patterned. The positive photoresist mask is utilized to etch a barrier selective to underlying single crystal silicon in anticipated shallow trench regions. Once the barrier has been removed, the positive photoresist mask is stripped, removing any unexposed positive photoresist remaining within the deep trench. Single crystal silicon revealed by removal of the barrier is etched to create the shallow trench, with remaining barrier material sacrificed to protect the underlying surface against this etching.

Abstract: A thin silicon epitaxial layer, formed on a silicon substrate, is subdivided into electrically isolated pockets by a grid of oxidized regions of epitaxial silicon material which extend through the epitaxial layer to a laterally extending PN junction.

Abstract: A method of forming a shallow trench isolation structure is disclosed. A dielectric layer deposited by chemical vapor deposition is used as a sacrificial layer instead of conventional sacrificial oxide layer formed by thermal oxidation. Therefore, the oxide in the trench is further protected and less damaged.

Abstract: A semiconductor device and method having shallow trench isolation. A pad oxide 24 and silicon 42 are formed on a substrate 20 to form a mask, and the pad oxide 24/silicon 42 mask is then patterned. Portions of the pad oxide 24/silicon 42 mask and the substrate 20 are removed to form trenches 22 in the substrate 20. A nitride fill 40 is deposited over the pad oxide 24/silicon 42 mask and the trenches 22. Advantages of the invention include a more robust STI device without central voids 34 and without edge voids 36 in the trench fill material.

Abstract: The present invention is directed to am improved chemical mechanical polish etch stop for a trench isolation and a method for making same. The method comprises forming at least four process layers above a surface of a semiconducting substrate. The method further comprises patterning said plurality of process layers to define an opening exposing a portion of the surface of the substrate. A trench is formed in the substrate, and the trench and the opening are then filled with a dielectric material. The surface of the dielectric material and the surface of the top process layer are then planarized. The present inventive structure is comprised of at least four process layers positioned above a substrate, an opening formed in said plurality of layers, a trench formed in said substrate, and a dielectric material positioned in said opening and said.

Abstract: The tendency of mobile positive ions to be transported into device regions of a bipolar transistor is effectively minimized by surrounding the transistor with a `positive ion`-attracting electric field, preferably by applying a prescribed bias to the fill material of a conductive trench that surrounds the device. The trench which surrounds a respective device to be protected contains dielectric material disposed along sidewalls of the trench. The trench contains material such as undoped polysilicon, which is capable of distributing a voltage, so that the material in the trench is insulated by dielectric material from an adjacent portion of the semiconductor substrate surrounded by the trench. In order to prevent mobile positive ions from moving into a device region in response to temperature bias stress and thereby degrade an operational parameter of the transistor, a predefined (relatively negative) bias voltage is applied to the material in the trench.

Abstract: A semiconductor structure having a first conductive trace fabricated adjacent to a second conductive trace over an insulating layer. A dielectric material is located over and between the first and second conductive traces. A borderless contact extends through the dielectric material to contact the first conductive trace. An air gap is formed in the dielectric material between the first and second conductive traces, thereby increasing the capacitance between the first and second traces. The air gap has a first portion with a first width adjacent to the borderless contact, and a second portion with a second width away from the borderless contact. The second width is greater than the first width, and the second portion of the air gap is substantially longer than the first portion of the air gap. The first portion of the air gap is offset toward the second trace.

Abstract: A semiconductor device and method for manufacturing the same includes a plurality of memory cells, each cell having a transistor formed on a first semiconductor substrate and comprising first and second impurity regions and a gate electrode, and a compacitor comprising a first electrode connected with the first impurity region of the transistor and a second electrode formed on the first electrode with a dielectric film disposed therebetween, wherein a channel region formed between the first impurity region and the second impurity region of the transistor is vertically located on the capacitor, and a contact hole connecting the second impurity region of the transistor with the bit-line is vertically located on the channel region, thus achieving the cell area required for one-giga-bit memory devices and beyond and enabling increased capacitance.

Abstract: The first trench is formed in the region of the semiconductor substrate, in which an element isolation region is to be formed, and the first buried member, which is insulative, is buried in the first trench. Then, the second trench, having a width smaller than that of the first trench, is made in the first buried member, and the portion of the semiconductor substrate which is located at the bottom portion of the first trench, and the insulating second buried member is buried in the second trench, thereby forming the element isolation region.

Abstract: A method for making planar silicon-based inductor structure with improved Q is disclosed. This method includes the steps of: (a) providing a lightly-doped P-type substrate as a starting wafer; (b) forming a preliminary oxide layer on the lightly-doped P-type substrate; (c) forming a first oxide layer from the preliminary oxide layer enclosing a predetermined epitaxial area; (d) depositing an epitaxial layer in the epitaxial area using intrinsic doping; (e) forming a second oxide layer which covers both the epitaxial layer and the first oxide layer, and is merged with the first oxide layer to thus form a contiguous inter-connected inductor oxide layer; (f) forming a metal line according to a planar inductor pattern so as to form a silicon-based inductor structure. The epitaxial layer has a resistivity of at least 2 K ohm-cm. The planar silicon-based inductor improves the Q value by reducing or stopping current losses into the substrate.

Abstract: This invention provides a thin metallic sheet structure having excellent sound damping characteristics which can lower the sound pressure level of a sound inherent to a thin metallic sheet structure when this structure is patted, and can quickly damp the sound by a simple structure. In a flat sheet-like or box-like structure comprising a thin metallic external sheet and beams for reinforcing the external sheet, a thin metallic sheet structure having excellent sound damping characteristics according to the present invention employs the construction wherein the reinforcing beams 2 are brought into contact with one of the surfaces of the thin metallic external sheet 1 through a sound damping sheet 3, and the coupling state between the sound damping sheet 3 and the thin metallic external plate 1 or the reinforcing beams 2 is a non-coupling state or a discrete coupling state on at least one of the surfaces of the sound damping sheet 3.

Abstract: A new method of forming simultaneously both shallow and deep trenches is described. A pad oxide layer is provided over a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A silicon dioxide layer is deposited overlying the silicon nitride layer. A photoresist mask is formed over the silicon dioxide layer wherein the photoresist mask has a first opening having a first width and a second opening having a second width and wherein the second width is larger than the first width. Trench openings are etched through the silicon dioxide, silicon nitride, and pad oxide layers to the underlying semiconductor substrate within the first and second openings. The photoresist mask is removed.

Abstract: A semiconductor device includes at least one passive device and is configured such that parasitic capacitances associated with the passive device are minimized. A substrate layer of the semiconductor device is formed of a substrate material characterized by a first dielectric constant. The substrate layer has at least one deep trench formed therein, and the deep trench is filled with a trench fill material characterized by a second, effective, dielectric constant that is lower than the first dielectric constant. A field layer is formed on a surface of the substrate layer over the deep trench. Finally, the passive device is formed on a surface of the field layer.