Abstract: A method for forming a self-aligned contact for a trench DMOS transistor comprises: providing a semiconductor substrate; etching a trench into the semiconductor substrate at a selected location on the surface of the semiconductor substrate; forming a first dielectric layer that covers the semiconductor substrate and walls of the trench; forming a plug in the trench, which comprises a step of depositing a semiconductor layer that covers the semiconductor substrate and fills in the trench, and a step of etching the semiconductor layer until the plug is below the trench for about 0.2 to 0.3 micron; forming a second dielectric layer on the plug; and forming a conductive layer over the second dielectric layer and the surface of the semiconductor substrate for ohmic contact regions.

Abstract: A method of fabricating a high power bipolar junction transistor. A P-type substrate having an N-type buried region is provided and a trench is formed within the substrate to expose the buried region. N-type ions are implanted and driven into the sidewall of the trench to form a sinker. Since the area and the depth of implantation are larger and deeper than that in prior art, the concentration of the sinker is more uniform and the diffusion range is easily controlled. An N-type epitaxial layer is then formed in the trench and an emitter, a base and their contacts are formed by conventional technique.

Abstract: A small-area, high-resistance load device is fabricated in the same area used for the shallow trench isolation region. In an example embodiment, the load device comprises a series resistor coupled to a poly-silicon diode. In one example application, the load device acts as a pull-up device replacing standard PMOS pull-up loads used in connection with static memory cells, thereby increasing the cell density of a static memory array.

Abstract: A contact structure of a semiconductor device includes an impurity-doped region formed in the semiconductor substrate, a trench having a groove in the semiconductor substrate, with the groove being in contact with at least one side face of the impurity-doped region, a conductive layer buried in the trench, and a contact region formed on at least one side face of the impurity-doped region, for connecting the impurity-doped region and the conductive layer. Thus, the area occupied by a unit cell is reduced and integration density can be increased accordingly.

Abstract: In order to produce an electrical connection to an inner layer such as a bottom diffusion (103), which has a good electrical conductivity and is located inside a bipolar semiconductor device isolated by trenches (119) and which for example forms a subcollector of a NPN-transistor, a hole (157) in a trench is used. The hole is filled with electrically conducting material and extends from the surface of the device to the bottom diffusion (103), so that the electrically conducting material in the hole is in contact therewith. The hole (157) is made aligned with a sidewall of the trench (119) by using selective etching. The hole can be made at the same time as contact holes for metallization are made and then also be filled in the metallization step, to contact the bottom diffusion. For a lateral PNP-transistor the hole can be made as a closed groove constituting the outer confinement of the base area, passing all around the transistor.

Abstract: The present invention relates to an integrated circuit including a lateral well isolation bipolar transistor. A first portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor base, to form a base contacting region. A second portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor emitter, to form an emitter contacting region.

Abstract: The tendency of mobile positive ions to be transported into device regions of a bipolar transistor is effectively minimized by surrounding the transistor with a `positive ion`-attracting electric field, preferably by applying a prescribed bias to the fill material of a conductive trench that surrounds the device. The trench which surrounds a respective device to be protected contains dielectric material disposed along sidewalls of the trench. The trench contains material such as undoped polysilicon, which is capable of distributing a voltage, so that the material in the trench is insulated by dielectric material from an adjacent portion of the semiconductor substrate surrounded by the trench. In order to prevent mobile positive ions from moving into a device region in response to temperature bias stress and thereby degrade an operational parameter of the transistor, a predefined (relatively negative) bias voltage is applied to the material in the trench.

Abstract: A process for producing a small shallow-depth high-performance bipolar structure having low parasitic capacitance is disclosed wherein an active base region of a P-type material is first defined in a substrate, a portion of which is of N-type material in a device formation area surrounded by an isolating oxide regions, such as trenches or the like. An N-doped polysilicon layer is then defined over the active base region and over field oxide regions located atop the isolating trenches. This N-poly region, when treated, will provide an interdigitated collector with self aligning emitter region aligned over the active base region. After appropriate spaced isolation layers are placed, a P-poly layer is laid down and heat treated to cause the P-type doping material to diffuse into the substrate contact to the active base region. A thin buried collector layer, approximately 1.

Abstract: A bipolar transistor and a method of fabricating the same are provided which are adapted to reduce chip size and production costs. To produce the transistor, a second conductive type well region is formed in a first conductive type semiconductor substrate and isolation trenches are formed at both sides of the well region. A high density second conductive type buried layer is formed in the semiconductor substrate which is formed at the bottom of the isolation trench. The buried layer is formed in two regions surrounding respective bottoms of two adjacent isolation trenches. The two regions are electrically connected with each other and in direct contact with the well region. An extrinsic base region and a device isolation region are formed sequentially onto the semiconductor substrate using a nitration layer pattern as a mask, wherein the nitration layer pattern is formed on the surface of semiconductor substrate.

Abstract: The present invention relates to a method of forming deep trenches in a BICMOS-type integrated circuit wherein the formation of a bipolar transistor includes the steps of depositing a base polysilicon layer, depositing a protection oxide layer, forming an emitter-base opening, and etching the silicon oxide protection layer and the base polysilicon layer outside the bipolar transistor areas. The formation of the trenches includes the steps of opening the protection oxide and base polysilicon layers above a thick oxide region while the emitter-base opening is being made, etching the thick oxide layer while the protection oxide layer is being etched, and etching the silicon under the thick oxide while the base polysilicon is being etched.

Abstract: The first trench is formed in the region of the semiconductor substrate, in which an element isolation region is to be formed, and the first buried member, which is insulative, is buried in the first trench. Then, the second trench, having a width smaller than that of the first trench, is made in the first buried member, and the portion of the semiconductor substrate which is located at the bottom portion of the first trench, and the insulating second buried member is buried in the second trench, thereby forming the element isolation region.

Abstract: The present invention provides a method of manufacturing a semiconductor device to prevent the generation of crystalline defects due to shorting between interconnects resulting from etch residue as a result of the generation of vertical bird's beaks on top of the trench during field oxidation layer formation. The method includes forming an epitaxial layer over a semiconductor substrate, depositing a first SiO.sub.2 layer, an SiN layer and a second SiO.sub.2 layer in that order upon said epitaxial layer and forming a trench from the second SiO.sub.2 layer extending into the semiconductor substrate. A third SiO.sub.2 layer is formed coating said trench with a region of said third Si0.sub.2 layer removed adjacent to said first SiO.sub.2 layer to expose a portion of said epitaxial layer within said trench. The trench is then filled with a first polysilicon layer to coat the third SiO.sub.2 layer and the first SiO.sub.2 layer followed by removal of the second SiO.sub.

Abstract: A new method of forming simultaneously both shallow and deep trenches is described. A pad oxide layer is provided over a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A silicon dioxide layer is deposited overlying the silicon nitride layer. A photoresist mask is formed over the silicon dioxide layer wherein the photoresist mask has a first opening having a first width and a second opening having a second width and wherein the second width is larger than the first width. Trench openings are etched through the silicon dioxide, silicon nitride, and pad oxide layers to the underlying semiconductor substrate within the first and second openings. The photoresist mask is removed.